* [Qemu-devel] about cache model in ARM emulation
@ 2007-10-18 13:57 Boy Dfx
2007-10-18 14:09 ` Daniel Jacobowitz
0 siblings, 1 reply; 2+ messages in thread
From: Boy Dfx @ 2007-10-18 13:57 UTC (permalink / raw)
To: qemu-devel
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Hello
I'm a newbie in the use of ARM simulators.
I got yesterday a question from my teacher and can't find the answer.
I would like to know weather QEMU simulates a cache miss (cache miss holds a penalty in terms of clock cycles or clock cycles counted) for an ARM-type core.
>From what I can see instructions are loaded from memory without a clock cycle penalty, but I wanted to be sure.
Thanks
Gabi V.
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^ permalink raw reply [flat|nested] 2+ messages in thread
* Re: [Qemu-devel] about cache model in ARM emulation
2007-10-18 13:57 [Qemu-devel] about cache model in ARM emulation Boy Dfx
@ 2007-10-18 14:09 ` Daniel Jacobowitz
0 siblings, 0 replies; 2+ messages in thread
From: Daniel Jacobowitz @ 2007-10-18 14:09 UTC (permalink / raw)
To: qemu-devel
On Thu, Oct 18, 2007 at 06:57:19AM -0700, Boy Dfx wrote:
> From what I can see instructions are loaded from memory without a
> clock cycle penalty, but I wanted to be sure.
Yes. Qemu is absolutely useless for performance questions about
real hardware; it does not model any cycles.
--
Daniel Jacobowitz
CodeSourcery
^ permalink raw reply [flat|nested] 2+ messages in thread
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