From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1IiW4D-0005GI-Hy for qemu-devel@nongnu.org; Thu, 18 Oct 2007 10:09:41 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1IiW49-0005CJ-0y for qemu-devel@nongnu.org; Thu, 18 Oct 2007 10:09:38 -0400 Received: from [199.232.76.173] (helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1IiW48-0005C7-S8 for qemu-devel@nongnu.org; Thu, 18 Oct 2007 10:09:36 -0400 Received: from nan.false.org ([208.75.86.248]) by monty-python.gnu.org with esmtp (Exim 4.60) (envelope-from ) id 1IiW48-0004UR-7J for qemu-devel@nongnu.org; Thu, 18 Oct 2007 10:09:36 -0400 Received: from nan.false.org (localhost [127.0.0.1]) by nan.false.org (Postfix) with ESMTP id 2265B982CA for ; Thu, 18 Oct 2007 14:09:35 +0000 (GMT) Received: from caradoc.them.org (22.svnf5.xdsl.nauticom.net [209.195.183.55]) by nan.false.org (Postfix) with ESMTP id 0CC48981F1 for ; Thu, 18 Oct 2007 14:09:35 +0000 (GMT) Received: from drow by caradoc.them.org with local (Exim 4.68) (envelope-from ) id 1IiW46-00030E-B1 for qemu-devel@nongnu.org; Thu, 18 Oct 2007 10:09:34 -0400 Date: Thu, 18 Oct 2007 10:09:34 -0400 From: Daniel Jacobowitz Subject: Re: [Qemu-devel] about cache model in ARM emulation Message-ID: <20071018140934.GA11519@caradoc.them.org> References: <533915.11425.qm@web37011.mail.mud.yahoo.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <533915.11425.qm@web37011.mail.mud.yahoo.com> Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org On Thu, Oct 18, 2007 at 06:57:19AM -0700, Boy Dfx wrote: > From what I can see instructions are loaded from memory without a > clock cycle penalty, but I wanted to be sure. Yes. Qemu is absolutely useless for performance questions about real hardware; it does not model any cycles. -- Daniel Jacobowitz CodeSourcery