From: Thiemo Seufer <ths@networkno.de>
To: Blue Swirl <blauwirbel@gmail.com>
Cc: qemu-devel <qemu-devel@nongnu.org>
Subject: Re: [Qemu-devel] [PATCH, RFC] Disable implicit self-modifying code support for RISC CPUs
Date: Sat, 3 Nov 2007 20:37:07 +0000 [thread overview]
Message-ID: <20071103203707.GG14756@networkno.de> (raw)
In-Reply-To: <f43fc5580711031315q590b7ae6t534a9c6e5ef72770@mail.gmail.com>
Blue Swirl wrote:
> Hi,
>
> RISC CPUs don't support self-modifying code unless the affected area
> is flushed explicitly.
Not entirely true. There are cacheless MIPS CPUs (the m4k), and also
cache-snooping MIPS CPUs (the R1x000).
> This patch disables the extra effort for SMC.
> The changes in this version would affect all CPUs except x86, but I'd
> like to see if there are problems with some target, so that the
> committed change can be limited. Without comments, I'll just disable
> SMC for Sparc, as there are no problems. So please comment, especially
> if you want to "opt in".
I prefer at least MIPS to stay as is.
Thiemo
next prev parent reply other threads:[~2007-11-03 20:37 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2007-11-03 20:15 [Qemu-devel] [PATCH, RFC] Disable implicit self-modifying code support for RISC CPUs Blue Swirl
2007-11-03 20:37 ` Thiemo Seufer [this message]
2007-11-03 22:13 ` Fabrice Bellard
2007-11-04 7:12 ` Blue Swirl
2007-11-04 7:36 ` J. Mayer
2007-11-04 7:49 ` Blue Swirl
2007-11-03 23:30 ` Paul Brook
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