From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1IopC7-0006re-Kr for qemu-devel@nongnu.org; Sun, 04 Nov 2007 18:47:55 -0500 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1IopC6-0006qw-3V for qemu-devel@nongnu.org; Sun, 04 Nov 2007 18:47:54 -0500 Received: from [199.232.76.173] (helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1IopC6-0006qt-0k for qemu-devel@nongnu.org; Sun, 04 Nov 2007 18:47:54 -0500 Received: from mail.codesourcery.com ([65.74.133.4]) by monty-python.gnu.org with esmtps (TLS-1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.60) (envelope-from ) id 1IopC5-0006sn-RL for qemu-devel@nongnu.org; Sun, 04 Nov 2007 18:47:54 -0500 From: Paul Brook Subject: Re: [Qemu-devel] sparc hflags support? Date: Sun, 4 Nov 2007 23:47:46 +0000 References: <472E5919.80307@earthlink.net> In-Reply-To: <472E5919.80307@earthlink.net> MIME-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: 7bit Content-Disposition: inline Message-Id: <200711042347.48438.paul@codesourcery.com> Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Robert Reif On Sunday 04 November 2007, Robert Reif wrote: > I'm looking at adding more complete support for different sparc32 > CPUs, MMUs, cache controllers and systems. > > Each CPU/MMU/cache controller combination is slightly different and > requires its own unique state. For example the two CPUs currently > supported save the boot mode in different bits in the MMU control > register: 0x2000 for the SuperSparc and 0x4000 for the TurboSparc. > Others bits will need to be saved in the MMU and cache controllers > as better hardware emulation is added. If it's something that only changes rarely (e.g. when switching from early boot to a real OS environment) you can just do a tb flush. Does mmu/cache mode actually effect the instruction semantics? Paul