From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1IvjPk-0007JT-Gs for qemu-devel@nongnu.org; Fri, 23 Nov 2007 20:02:32 -0500 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1IvjPj-0007JG-Oz for qemu-devel@nongnu.org; Fri, 23 Nov 2007 20:02:32 -0500 Received: from [199.232.76.173] (helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1IvjPj-0007JB-LU for qemu-devel@nongnu.org; Fri, 23 Nov 2007 20:02:31 -0500 Received: from server2linux.rebelnetworks.com ([66.135.41.201]) by monty-python.gnu.org with esmtps (TLS-1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.60) (envelope-from ) id 1IvjPj-0002bU-AS for qemu-devel@nongnu.org; Fri, 23 Nov 2007 20:02:31 -0500 Received: from p5b167f31.dip.t-dialin.net ([91.22.127.49] helo=phoenix2.frop.org) by server2linux.rebelnetworks.com with esmtpa (Exim 4.68) (envelope-from ) id 1IvjPf-0001hf-3q for qemu-devel@nongnu.org; Fri, 23 Nov 2007 19:02:27 -0600 From: Julian Seward Subject: Re: [Qemu-devel] qemu hw/ppc_oldworld.c target-ppc/cpu.h target-... Date: Sat, 24 Nov 2007 02:02:08 +0100 References: <1195861001.24893.40.camel@rapid> <200711240052.31546.paul@codesourcery.com> In-Reply-To: <200711240052.31546.paul@codesourcery.com> MIME-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: 7bit Content-Disposition: inline Message-Id: <200711240202.08750.jseward@acm.org> Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org > Well, I admit I've invented the term "ppc32", but there are dozens of > 32-bit PowerPC chips. I'd be amazed if they do 64-bit computations or have > 64-bit GPRs. Indeed not. Valgrind implements the 32-bit PPC user-space instruction set quite adequately using 32-bit computations throughout. No need for 64-bit computations. J