From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1IyH0x-0000Kh-7o for qemu-devel@nongnu.org; Fri, 30 Nov 2007 20:19:27 -0500 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1IyH0u-0000JT-MB for qemu-devel@nongnu.org; Fri, 30 Nov 2007 20:19:26 -0500 Received: from [199.232.76.173] (helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1IyH0u-0000JQ-JN for qemu-devel@nongnu.org; Fri, 30 Nov 2007 20:19:24 -0500 Received: from pip10.gyao.ne.jp ([61.122.117.248] helo=mx.gate01.com) by monty-python.gnu.org with esmtps (TLS-1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.60) (envelope-from ) id 1IyH0u-00044A-Fo for qemu-devel@nongnu.org; Fri, 30 Nov 2007 20:19:24 -0500 Received: from [124.34.33.190] (helo=master.linux-sh.org) by smtp32.isp.us-com.jp with esmtp (Mail 4.41) id 1IyH0p-0003kZ-1d for qemu-devel@nongnu.org; Sat, 01 Dec 2007 10:19:19 +0900 Received: from localhost (unknown [127.0.0.1]) by master.linux-sh.org (Postfix) with ESMTP id 1CC4864C7C for ; Sat, 1 Dec 2007 01:19:07 +0000 (UTC) Received: from master.linux-sh.org ([127.0.0.1]) by localhost (master.linux-sh.org [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id PR+zluKIg5Mp for ; Sat, 1 Dec 2007 10:19:06 +0900 (JST) Date: Sat, 1 Dec 2007 10:19:06 +0900 From: Paul Mundt Subject: Re: [Qemu-devel] [PATCH] sh4: define explicitly that the target CPU is 32 bit Message-ID: <20071201011906.GB15027@linux-sh.org> References: <20071130162329.GF28369@tapir> <200711301628.09857.paul@codesourcery.com> <20071130170002.GG28369@tapir> <200711301715.21956.paul@codesourcery.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <200711301715.21956.paul@codesourcery.com> Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org On Fri, Nov 30, 2007 at 05:15:21PM +0000, Paul Brook wrote: > On Friday 30 November 2007, Carlo Marcelo Arenas Belon wrote: > > On Fri, Nov 30, 2007 at 04:28:09PM +0000, Paul Brook wrote: > > in the sh4 specific case, it doesn't make sense for sh4 to print an access > > error to a physical address that is 64 bit long when it is a 32 bit CPU and > > that is what would happen unless the patch is applied. > > > > if anything the following definition from cpu-defs.h is invalid for a > > representation of a 32 bit physical address : > > > > #define TARGET_FMT_plx "%016" PRIx64 > > Before you can fix that you probably need to fix the bits of qemu (TLB code) > that store a host pointer in a phys_addr_t. Or at least distance > TARGET_PHYS_ADDR_BITS from the definition of phys_addr_t, and include > appropriate comments. > > In that case TARGET_PHYS_ADDR_BITS could be a precise value, rather than the > next multiple of 32. e.g. I think sparc32 has a 40-bit physical address > space. > It also depends on how precise you want to make this. SH has configurable 29-bit and 32-bit physical, while MIPS and PPC both have 32 and 36-bit physical implementations. Setting things to an arbitrary upper ceiling at least prevents this from quickly entering ifdef hell territory.