From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1J2clD-0006Bv-Rt for qemu-devel@nongnu.org; Wed, 12 Dec 2007 20:21:11 -0500 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1J2clB-000682-OD for qemu-devel@nongnu.org; Wed, 12 Dec 2007 20:21:10 -0500 Received: from [199.232.76.173] (helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1J2clB-00067d-HK for qemu-devel@nongnu.org; Wed, 12 Dec 2007 20:21:09 -0500 Received: from mail.codesourcery.com ([65.74.133.4]) by monty-python.gnu.org with esmtps (TLS-1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.60) (envelope-from ) id 1J2clB-0008NN-Im for qemu-devel@nongnu.org; Wed, 12 Dec 2007 20:21:09 -0500 From: Paul Brook Subject: Re: [Qemu-devel] [PATCH] arm eabi TLS Date: Thu, 13 Dec 2007 01:21:03 +0000 References: <1197420297.2947.94.camel@phantasm.home.enterpriseandprosperity.com> <476068AA.80001@bellard.org> In-Reply-To: <476068AA.80001@bellard.org> MIME-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: 7bit Content-Disposition: inline Message-Id: <200712130121.04204.paul@codesourcery.com> Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: thayne@c2.net > - It would be good to limit the changes in the CPU emulation code to > handle the TLS. For example, on MIPS, the TLS register must not be > stored in the CPU state. Same for ARM. I disagree. The TLS register is part of the CPU state. On many machines (including ARMv6 CPUs) it's an actual CPU register. I'm fairly sure the same is true for recent MIPS revisions. Paul