From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1J4PwB-0005Sb-VW for qemu-devel@nongnu.org; Mon, 17 Dec 2007 19:03:56 -0500 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1J4PwA-0005Rx-4W for qemu-devel@nongnu.org; Mon, 17 Dec 2007 19:03:55 -0500 Received: from [199.232.76.173] (helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1J4Pw9-0005Rr-Uy for qemu-devel@nongnu.org; Mon, 17 Dec 2007 19:03:53 -0500 Received: from mail.codesourcery.com ([65.74.133.4]) by monty-python.gnu.org with esmtps (TLS-1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.60) (envelope-from ) id 1J4Pw9-0007ha-6c for qemu-devel@nongnu.org; Mon, 17 Dec 2007 19:03:53 -0500 From: Paul Brook Subject: Re: [Qemu-devel] [PATCH 2/2 v2][UPDATED] Direct IDE I/O Date: Tue, 18 Dec 2007 00:03:48 +0000 References: <11979293592467@bull.net> <47670010.6090409@bellard.org> In-Reply-To: <47670010.6090409@bellard.org> MIME-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: 7bit Content-Disposition: inline Message-Id: <200712180003.49328.paul@codesourcery.com> Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Laurent Vivier On Monday 17 December 2007, Fabrice Bellard wrote: > Laurent Vivier wrote: > > This patch enhances the "-drive ,cache=off" mode with IDE drive emulation > > by removing the buffer used in the IDE emulation. > > --- > > block.c | 10 +++ > > block.h | 2 > > block_int.h | 1 > > cpu-all.h | 1 > > exec.c | 19 ++++++ > > hw/ide.c | 176 > > +++++++++++++++++++++++++++++++++++++++++++++++++++++++++--- vl.c > > | 1 > > 7 files changed, 204 insertions(+), 6 deletions(-) > > [...] > > Unfortunately it is more complicated to write to the CPU memory. In > particular, specific action should be done when translated code is > present. A consistent API must include something like cpu_page_lock() / > unlock(). Look at cpu_physical_memory_rw() to see the various issues > which must be handled. Moreover, it would be better to add bus specific > APIs (at least for PCI), but I can accept a CPU memory API for now. In general it may also be unsafe to do async writes directly to guest memory because you break the atomicity of loads/stores. Paul