From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1JV1jz-0004sQ-QY for qemu-devel@nongnu.org; Fri, 29 Feb 2008 04:41:19 -0500 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1JV1jy-0004rI-Jg for qemu-devel@nongnu.org; Fri, 29 Feb 2008 04:41:19 -0500 Received: from [199.232.76.173] (helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1JV1jy-0004r4-7B for qemu-devel@nongnu.org; Fri, 29 Feb 2008 04:41:18 -0500 Received: from os.inf.tu-dresden.de ([141.76.48.99]) by monty-python.gnu.org with esmtps (TLS-1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.60) (envelope-from ) id 1JV1jx-0000dd-G0 for qemu-devel@nongnu.org; Fri, 29 Feb 2008 04:41:17 -0500 Received: from erwin.inf.tu-dresden.de ([141.76.48.80] helo=chrom.inf.tu-dresden.de) by os.inf.tu-dresden.de with esmtps (TLSv1:AES256-SHA:256) (Exim 4.69) id 1JV1ju-00013F-BZ for qemu-devel@nongnu.org; Fri, 29 Feb 2008 10:41:14 +0100 Received: from kauer by chrom.inf.tu-dresden.de with local (Exim 4.69) (envelope-from ) id 1JV1jt-0005ch-KG for qemu-devel@nongnu.org; Fri, 29 Feb 2008 10:41:13 +0100 Date: Fri, 29 Feb 2008 10:41:13 +0100 From: Bernhard Kauer Subject: Re: [Qemu-devel] [PATCH] allow update of MSR_EFER_SVM Message-ID: <20080229094113.GB9305@chrom.inf.tu-dresden.de> References: <20080227160716.GA9305@chrom.inf.tu-dresden.de> <50E1BA25-AC2A-48A2-AFF2-83630AE4BF9E@csgraf.de> MIME-Version: 1.0 Content-Type: multipart/mixed; boundary="H+4ONPRPur6+Ovig" Content-Disposition: inline In-Reply-To: <50E1BA25-AC2A-48A2-AFF2-83630AE4BF9E@csgraf.de> Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org --H+4ONPRPur6+Ovig Content-Type: text/plain; charset=us-ascii Content-Disposition: inline On Wed, Feb 27, 2008 at 06:03:49PM +0100, Alexander Graf wrote: > MSR_EFER_SVM is not defined in my qemu version. What does the bit change > if set? The AMD vol2 reads like this: Secure Virtual Machine Enable (SVME) Bit. Bit 12. Enables the SVM extensions. When this bit is zero, the SVM instructions cause #UD exceptions. The bit was called MSR_EFER_SVME_MASK in svm.h before, I renamed it in the attached patch to MSR_EFER_SVME to match the style of the other definitions in cpu.h. BTW, triggering the above mentioned #UD is missing in the code... Bernhard Kauer --H+4ONPRPur6+Ovig Content-Type: text/x-diff; charset=us-ascii Content-Disposition: attachment; filename="qemu_efer.diff" Index: target-i386/helper.c =================================================================== RCS file: /sources/qemu/qemu/target-i386/helper.c,v retrieving revision 1.101 diff -u -r1.101 helper.c --- target-i386/helper.c 3 Feb 2008 03:26:30 -0000 1.101 +++ target-i386/helper.c 29 Feb 2008 09:33:41 -0000 @@ -2802,6 +2802,8 @@ update_mask |= MSR_EFER_FFXSR; if (env->cpuid_ext2_features & CPUID_EXT2_NX) update_mask |= MSR_EFER_NXE; + if (env->cpuid_ext3_features & CPUID_EXT3_SVM) + update_mask |= MSR_EFER_SVME; env->efer = (env->efer & ~update_mask) | (val & update_mask); } Index: target-i386/svm.h =================================================================== RCS file: /sources/qemu/qemu/target-i386/svm.h,v retrieving revision 1.1 diff -u -r1.1 svm.h --- target-i386/svm.h 23 Sep 2007 15:30:28 -0000 1.1 +++ target-i386/svm.h 29 Feb 2008 09:33:41 -0000 @@ -179,7 +179,7 @@ #define SVM_CPUID_FEATURE_SHIFT 2 #define SVM_CPUID_FUNC 0x8000000a -#define MSR_EFER_SVME_MASK (1ULL << 12) +#define MSR_EFER_SVME (1ULL << 12) #define SVM_SELECTOR_S_SHIFT 4 #define SVM_SELECTOR_DPL_SHIFT 5 --H+4ONPRPur6+Ovig--