From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1JfucN-0003gh-TY for qemu-devel@nongnu.org; Sun, 30 Mar 2008 06:18:28 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1JfucI-0003bX-0v for qemu-devel@nongnu.org; Sun, 30 Mar 2008 06:18:24 -0400 Received: from [199.232.76.173] (helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1JfucH-0003bO-NO for qemu-devel@nongnu.org; Sun, 30 Mar 2008 06:18:21 -0400 Received: from mail.codesourcery.com ([65.74.133.4]) by monty-python.gnu.org with esmtps (TLS-1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.60) (envelope-from ) id 1JfucH-00033U-7q for qemu-devel@nongnu.org; Sun, 30 Mar 2008 06:18:21 -0400 From: Paul Brook Subject: Re: [Qemu-devel] [PATCH 2/6] PCI DMA API Date: Sun, 30 Mar 2008 10:18:14 +0000 References: <1206827760-4566-1-git-send-email-aliguori@us.ibm.com> <1206827760-4566-2-git-send-email-aliguori@us.ibm.com> In-Reply-To: <1206827760-4566-2-git-send-email-aliguori@us.ibm.com> MIME-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: 7bit Content-Disposition: inline Message-Id: <200803301118.15663.paul@codesourcery.com> Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: kvm-devel@lists.sourceforge.net, Marcelo Tosatti , Anthony Liguori , Aurelien Jarno On Saturday 29 March 2008, Anthony Liguori wrote: > This patch introduces a PCI DMA API and some generic code to support other > DMA APIs. Two types are introduced: PhysIOVector and IOVector. A DMA API > maps a PhysIOVector, which is composed of target_phys_addr_t, into an > IOVector, which is composed of void *. Devices should not be using IOVector. They should either use the DMA copy routines to copy from a PhysIOVector into a local buffer, or they should pass a PhysIOVector to a block/network read/write routine. The DMA API should allow devices to be agnostic about how DMA is implemented. They should not be trying to manually implement zero copy. > This enables zero-copy IO to be preformed without introducing assumptions > of phys_ram_base. This API is at the PCI device level to enable support of > per-device IOMMU remapping. By my reading it *requires* bridges be zero-copy. For big-endian targets we need to ability to byteswap accesses. Some description (in the form of source comments) of how it's meant to be used would also be helpful. Paul