From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1Jg28O-0001Z0-3E for qemu-devel@nongnu.org; Sun, 30 Mar 2008 14:20:00 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1Jg28N-0001XW-1n for qemu-devel@nongnu.org; Sun, 30 Mar 2008 14:19:59 -0400 Received: from [199.232.76.173] (helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1Jg28M-0001XD-Sw for qemu-devel@nongnu.org; Sun, 30 Mar 2008 14:19:58 -0400 Received: from mail.codesourcery.com ([65.74.133.4]) by monty-python.gnu.org with esmtps (TLS-1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.60) (envelope-from ) id 1Jg28M-0004o9-Fi for qemu-devel@nongnu.org; Sun, 30 Mar 2008 14:19:58 -0400 From: Paul Brook Subject: Re: [Qemu-devel] [PATCH 2/6] PCI DMA API Date: Sun, 30 Mar 2008 18:19:53 +0000 References: <1206827760-4566-1-git-send-email-aliguori@us.ibm.com> <200803301118.15663.paul@codesourcery.com> <47EFA6E1.7020401@us.ibm.com> In-Reply-To: <47EFA6E1.7020401@us.ibm.com> MIME-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: 7bit Content-Disposition: inline Message-Id: <200803301919.54780.paul@codesourcery.com> Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Anthony Liguori Cc: kvm-devel@lists.sourceforge.net, Marcelo Tosatti , qemu-devel@nongnu.org, Aurelien Jarno On Sunday 30 March 2008, Anthony Liguori wrote: > Paul Brook wrote: > > On Saturday 29 March 2008, Anthony Liguori wrote: > >> This patch introduces a PCI DMA API and some generic code to support > >> other DMA APIs. Two types are introduced: PhysIOVector and IOVector. A > >> DMA API maps a PhysIOVector, which is composed of target_phys_addr_t, > >> into an IOVector, which is composed of void *. > > > > Devices should not be using IOVector. They should either use the DMA copy > > routines to copy from a PhysIOVector into a local buffer, or they should > > pass a PhysIOVector to a block/network read/write routine. The DMA API > > should allow devices to be agnostic about how DMA is implemented. They > > should not be trying to manually implement zero copy. > > Someone has to do the translation of PhysIOVector => IOVector. It > doesn't seem logical to me to do it in the IO backend level because the > block subsystem doesn't know how to do that translation. You would have > to pass the PhysIOVector although with a translation function and an > opaque pointer. The entity processing the data shouldn't need to know or care how the translation is done. PhysIOVector should describe everything it need to know. > What could work is if the DMA API functions mapped PhysIOVector => > PhysIOVector and then the network and block subsystems could operate on > a PhysIOVector. I have patches that implement vector IO for net and > block but didn't want to include them in this series to keep things simple. IMHO this is the only sane way to implement zero-copy. > >> This enables zero-copy IO to be preformed without introducing > >> assumptions of phys_ram_base. This API is at the PCI device level to > >> enable support of per-device IOMMU remapping. > > > > By my reading it *requires* bridges be zero-copy. For big-endian targets > > we need to ability to byteswap accesses. > > You mean via ld/st_phys? By whatever means the bridge deems necessary. The whole point of the DMA API is that you're transferring a block of data. The API allows intermediate busses to transform that data (and address) without the block handler needing to know or care. With your current scheme a byteswapping bus has to allocate a single large buffer for the whole vector, even if the device then ends up copying unto a local buffer in small chunks. Paul