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Date: Fri, 4 Apr 2008 16:29:44 +0200
From: Samuel Thibault <samuel.thibault@eu.citrix.com>
Subject: Re: [Qemu-devel] [PATCH] Asynchronous reliable and configurable cache
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To: qemu-devel@nongnu.org

Ian Jackson, le Wed 02 Apr 2008 15:21:32 +0100, a écrit :
> Samuel Thibault writes ("Re: [Qemu-devel] [PATCH] Asynchronous reliable and configurable cache flush"):
> > Oh, by the way, shouldn't this:
> > Ian Jackson, le Tue 01 Apr 2008 18:18:59 +0100, a écrit :
> > >      put_le16(p + 81, 0x16); /* conforms to ata5 */
> > > -    put_le16(p + 82, (1 << 14));
> > > +    /* 14=nop 5=write_cache */
> > > +    put_le16(p + 82, (1 << 14) | (1 << 5));
> > >      /* 13=flush_cache_ext,12=flush_cache,10=lba48 */
> > 
> > use s->write_cache instead of always 1?  Else when using hdparm -i one
> > would think that write cache is always enabled.
> 
> No.  According to the ATA-7 draft I have in front of me, the meaning
> of word 82 is `Command set supported' and the meaning of bit 5 is is
> `write cache supported'.

Oh, I was actually talking about word 85 indeed.  In Xen we lack the
word 82 bit, I'll make a patch.

Samuel