From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1JiyKd-0007cn-U1 for qemu-devel@nongnu.org; Mon, 07 Apr 2008 16:52:47 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1JiyKc-0007bp-5z for qemu-devel@nongnu.org; Mon, 07 Apr 2008 16:52:47 -0400 Received: from [199.232.76.173] (helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1JiyKc-0007bj-0M for qemu-devel@nongnu.org; Mon, 07 Apr 2008 16:52:46 -0400 Received: from binaervarianz.de ([213.239.198.218]) by monty-python.gnu.org with esmtps (TLS-1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.60) (envelope-from ) id 1JiyKb-0003Xv-Fw for qemu-devel@nongnu.org; Mon, 07 Apr 2008 16:52:45 -0400 Received: from localhost ([127.0.0.1] helo=binaervarianz.de) by binaervarianz.de with esmtp (Exim 4.63) (envelope-from ) id 1JiyKW-0007Su-Fb for qemu-devel@nongnu.org; Mon, 07 Apr 2008 22:52:40 +0200 Message-ID: <20080407225240.0c3a69hscko0go0c@mail.binaervarianz.de> Date: Mon, 07 Apr 2008 22:52:40 +0200 From: ulfsen@binaervarianz.de MIME-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; DelSp="Yes"; format="flowed" Content-Disposition: inline Content-Transfer-Encoding: quoted-printable Subject: [Qemu-devel] problems running QEMU as ARM RealView EB _Rev. C_ Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Hello, in the latest CVS snapshot the emulation for the ARM RealView Emulation Baseboard is based on board revision B. After changing the SCU base address from 0x10100000 (Board Rev.B) to 0x1F000000 (Board Rev.C) I was able to boot a non SMP linux kernel(2.6.22). --- ../../qemu-snapshot-2008-04-07_05/hw/mpcore.c 2008-04-07 12:59:11.000000000 +0200 +++ ../hw/mpcore.c 2008-04-01 17:58:58.000000000 +0200 @@ -11,7 +11,11 @@ #include "qemu-timer.h" #include "primecell.h" -#define MPCORE_PRIV_BASE 0x10100000 +/* Rev.C fix: + * SCU registers on Rev.B =3D 0x10100000 + * on Rev.C =3D 0x1F000000 + */ +#define MPCORE_PRIV_BASE 0x1F000000 #define NCPU 4 /* ??? The MPCore TRM says the on-chip controller has 224 external IRQ lines (+ 32 internal). However my test chip only exposes/reports 32. After that I tried a SMP kernel. The boot process on the Bootstrap Processor is running fine but it fails initialising the Application Processors. ... Calibrating local timer... 95.58MHz. CPU1: processor failed to boot CPU2: processor failed to boot CPU3: processor failed to boot Brought up 1 CPUs SMP: Total of 1 processors activated (399.76 BogoMIPS). ... Now I am not sure if the softirq that is sent by the Bootstrap Processor (done by the function calling smp_cross_call() in arch/arm/mach-realview/platsmp.c) is received by the Application Processors. Now my main problem is that I coundn't find any information about multicore debugging with the help of QEMU an GDB. Even after changing the current CPU from 0 to 1 in QEMU console the QEMU GDB stub is still running on CPU0. Is there a way to do some debugging on CPU 1,2 or 3? Or is there a way to monitor interupts in QEMU? Or maybe I just missed to change an other base address while migrating from Board Rev.B to rev.C? Any ideas or comments are welcome! --- Regards Ulf