From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1Jt86Q-0003Xh-NR for qemu-devel@nongnu.org; Mon, 05 May 2008 17:20:06 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1Jt86P-0003X5-Tg for qemu-devel@nongnu.org; Mon, 05 May 2008 17:20:06 -0400 Received: from [199.232.76.173] (port=56786 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1Jt86P-0003Wy-H1 for qemu-devel@nongnu.org; Mon, 05 May 2008 17:20:05 -0400 Received: from hall.aurel32.net ([91.121.138.14]) by monty-python.gnu.org with esmtps (TLS-1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.60) (envelope-from ) id 1Jt86P-0008WB-48 for qemu-devel@nongnu.org; Mon, 05 May 2008 17:20:05 -0400 Date: Mon, 5 May 2008 23:20:04 +0200 From: Aurelien Jarno Subject: Re: [Qemu-devel] [PATCH] ide: Enable byte&word access to DMA address register Message-ID: <20080505212004.GA25810@volta.aurel32.net> References: <481EC357.9030401@siemens.com> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-15 Content-Disposition: inline In-Reply-To: <481EC357.9030401@siemens.com> Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Jan Kiszka Cc: qemu-devel@nongnu.org On Mon, May 05, 2008 at 10:20:39AM +0200, Jan Kiszka wrote: > According to the specs, also byte- and word-wise access to the busmaster > DMA address register is allowed. Patch below fixes the IDE emulation > in this regard (avoiding to touch the existing common case of 32-bit > access) and makes our guest happy. > > Signed-off-by: Jan Kiszka > --- > hw/ide.c | 25 +++++++++++++++++++++++++ > 1 file changed, 25 insertions(+) > > Index: b/hw/ide.c > =================================================================== > --- a/hw/ide.c > +++ b/hw/ide.c > @@ -2838,6 +2838,29 @@ static void bmdma_writeb(void *opaque, u > } > } > > +static uint32_t bmdma_addr_readb(void *opaque, uint32_t addr) > +{ > + BMDMAState *bm = opaque; > + uint32_t val; > + val = (bm->addr >> ((addr & 3) * 8)) & 0xff; > +#ifdef DEBUG_IDE > + printf("%s: 0x%08x\n", __func__, val); > +#endif > + return val; > +} > + > +static void bmdma_addr_writeb(void *opaque, uint32_t addr, uint32_t val) > +{ > + BMDMAState *bm = opaque; > + int shift = (addr & 3) * 8; > +#ifdef DEBUG_IDE > + printf("%s: 0x%08x\n", __func__, val); > +#endif > + bm->addr &= ~(0xFF << shift); > + bm->addr |= (val & 0xfc) << shift; Are you sure it is correct? If you want to make sure the 2 lowest bits are 0, it should be instead: bm->addr |= ((val & 0xFF) << shift) & ~3; > + bm->cur_addr = bm->addr; > +} > + > static uint32_t bmdma_addr_readl(void *opaque, uint32_t addr) > { > BMDMAState *bm = opaque; > @@ -2876,6 +2899,8 @@ static void bmdma_map(PCIDevice *pci_dev > register_ioport_write(addr + 1, 3, 1, bmdma_writeb, bm); > register_ioport_read(addr, 4, 1, bmdma_readb, bm); > > + register_ioport_write(addr + 4, 4, 1, bmdma_addr_writeb, bm); > + register_ioport_read(addr + 4, 4, 1, bmdma_addr_readb, bm); > register_ioport_write(addr + 4, 4, 4, bmdma_addr_writel, bm); > register_ioport_read(addr + 4, 4, 4, bmdma_addr_readl, bm); > addr += 8; > Otherwise, looks ok. Are word accesses supported? If yes it may be nice to implement bmdma_addr_writew and bmdma_addr_readw at the same time. -- .''`. Aurelien Jarno | GPG: 1024D/F1BCDB73 : :' : Debian developer | Electrical Engineer `. `' aurel32@debian.org | aurelien@aurel32.net `- people.debian.org/~aurel32 | www.aurel32.net