[Qemu-devel] Support For Octeon/Cavium CPU (MIPS system)

[Qemu-devel] Support For Octeon/Cavium CPU (MIPS system)

[octane indice]

Hello

I own a cavium/octeon board. I run a linux on it.

I want to usr qemu for convenience in order to continue my developpements.

I know that Cavium/octeon board are MIPS CPU. 
But I didn't manage to boot my kernel in qemu. I tried several possibilities
with -M and -cpu but my kernel never loads.

Info I have:
cpu model               : Cavium Networks Octeon CN38XX/CN36XX V0.3
BogoMIPS                : 1000.60
wait instruction        : yes
microsecond timers      : yes
tlb_entries             : 32
extra interrupt vector  : yes
hardware watchpoint     : yes
ASEs implemented        :
VCED exceptions         : not available
VCEI exceptions         : not available

Is there any way to boot my kernel inside qemu?

Thanks for help, I read the linux-mips wiki without much help

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Re: [Qemu-devel] Support For Octeon/Cavium CPU (MIPS system)

[Paul Brook]

> I own a cavium/octeon board. I run a linux on it.
>
> I want to usr qemu for convenience in order to continue my developpements.
>
> I know that Cavium/octeon board are MIPS CPU.

Not really. They're MIPS with extra weirdness.

Your kernel needs to match the exact CPU and board that you're emulating. i.e. 
if you want to use an unmodified kernel you need to add support for both the 
CPU and board to qemu.

Paul

Re: [Qemu-devel] Support For Octeon/Cavium CPU (MIPS system)

[M. Warner Losh]

In message: <200805221427.26860.paul@codesourcery.com>
            Paul Brook <paul@codesourcery.com> writes:
: > I own a cavium/octeon board. I run a linux on it.
: >
: > I want to usr qemu for convenience in order to continue my developpements.
: >
: > I know that Cavium/octeon board are MIPS CPU.
: 
: Not really. They're MIPS with extra weirdness.

All SoCs are MIPS with extra documented weirdness.  The OCTEON CPUs
aren't documented in a public...

: Your kernel needs to match the exact CPU and board that you're
: emulating. i.e.  if you want to use an unmodified kernel you need to
: add support for both the CPU and board to qemu.

This is true.  fortunately, many other SoCs have had their support
added to QEMU...

Warner

Re: [Qemu-devel] Support For Octeon/Cavium CPU (MIPS system)

[Paul Brook]

> : > I know that Cavium/octeon board are MIPS CPU.
> :
> : Not really. They're MIPS with extra weirdness.
>
> All SoCs are MIPS with extra documented weirdness.  The OCTEON CPUs
> aren't documented in a public...

The Cavium cores are weirder than most. It doesn't use the normal MIPS ISA. 
Most SoC are a standard mips core (r4k, etc.) with a bunch of peripherals.

Paul

Re: [Qemu-devel] Support For Octeon/Cavium CPU (MIPS system)

[M. Warner Losh]

In message: <200805221704.00480.paul@codesourcery.com>
            Paul Brook <paul@codesourcery.com> writes:
: > : > I know that Cavium/octeon board are MIPS CPU.
: > :
: > : Not really. They're MIPS with extra weirdness.
: >
: > All SoCs are MIPS with extra documented weirdness.  The OCTEON CPUs
: > aren't documented in a public...
: 
: The Cavium cores are weirder than most. It doesn't use the normal MIPS ISA. 
: Most SoC are a standard mips core (r4k, etc.) with a bunch of peripherals.

Yes, they do use the noraml MIPS ISA.  It is a MIPS64r2 part.  It does
have a bunch of additional instructions that are leveraged off the CP2
coprocessor for crypto and related things.  Its cache is different
too, but every platform's cache is different.  There's a number of
hacks present to allow different images to run on different core.

Or maybe this is what you are saying :-

Warner

Re: [Qemu-devel] Support For Octeon/Cavium CPU (MIPS system)

[Thiemo Seufer]

M. Warner Losh wrote:
> In message: <200805221704.00480.paul@codesourcery.com>
>             Paul Brook <paul@codesourcery.com> writes:
> : > : > I know that Cavium/octeon board are MIPS CPU.
> : > :
> : > : Not really. They're MIPS with extra weirdness.
> : >
> : > All SoCs are MIPS with extra documented weirdness.  The OCTEON CPUs
> : > aren't documented in a public...
> : 
> : The Cavium cores are weirder than most. It doesn't use the normal MIPS ISA. 
> : Most SoC are a standard mips core (r4k, etc.) with a bunch of peripherals.
> 
> Yes, they do use the noraml MIPS ISA.  It is a MIPS64r2 part.

AFAIU they invented a mode in their core which replaces (d)lwl/(d)lwr
with different instructions for unaligned load/stores. :-(


Thiemo

Re: [Qemu-devel] Support For Octeon/Cavium CPU (MIPS system)

[Jamie Lokier]

Thiemo Seufer wrote:
> > Yes, they do use the noraml MIPS ISA.  It is a MIPS64r2 part.
> 
> AFAIU they invented a mode in their core which replaces (d)lwl/(d)lwr
> with different instructions for unaligned load/stores. :-(

The Alteon Tigon 2 gigabit ethernet processor did something similar,
except it wasn't a mode but fixed.

The documentation said it was because those particular instructions
are covered by a patent, so they couldn't implement them.

-- Jaie

Re: [Qemu-devel] Support For Octeon/Cavium CPU (MIPS system)

[M. Warner Losh]

In message: <1211453314.48354f82621a1@webmail.alinto.com>
            octane indice <octane@alinto.com> writes:
: Is there any way to boot my kernel inside qemu?

No.  Cavium CPU support isn't present in QEMU, even though the CPU is
mostly MISP64r2.  The technical specs are available under NDA only,
and the network and serial ports are different from anything else.

Warner