From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1JzDVe-00067P-JS for qemu-devel@nongnu.org; Thu, 22 May 2008 12:19:18 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1JzDVc-00066b-P4 for qemu-devel@nongnu.org; Thu, 22 May 2008 12:19:18 -0400 Received: from [199.232.76.173] (port=34762 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1JzDVc-00066V-HP for qemu-devel@nongnu.org; Thu, 22 May 2008 12:19:16 -0400 Received: from bsdimp.com ([199.45.160.85]:62927 helo=harmony.bsdimp.com) by monty-python.gnu.org with esmtps (TLS-1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.60) (envelope-from ) id 1JzDVb-0003p2-G2 for qemu-devel@nongnu.org; Thu, 22 May 2008 12:19:16 -0400 Date: Thu, 22 May 2008 10:17:15 -0600 (MDT) Message-Id: <20080522.101715.-233685094.imp@bsdimp.com> Subject: Re: [Qemu-devel] Support For Octeon/Cavium CPU (MIPS system) From: "M. Warner Losh" In-Reply-To: <200805221704.00480.paul@codesourcery.com> References: <200805221427.26860.paul@codesourcery.com> <20080522.095542.-1350511548.imp@bsdimp.com> <200805221704.00480.paul@codesourcery.com> Mime-Version: 1.0 Content-Type: Text/Plain; charset=us-ascii Content-Transfer-Encoding: 7bit Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: paul@codesourcery.com Cc: qemu-devel@nongnu.org, octane@alinto.com In message: <200805221704.00480.paul@codesourcery.com> Paul Brook writes: : > : > I know that Cavium/octeon board are MIPS CPU. : > : : > : Not really. They're MIPS with extra weirdness. : > : > All SoCs are MIPS with extra documented weirdness. The OCTEON CPUs : > aren't documented in a public... : : The Cavium cores are weirder than most. It doesn't use the normal MIPS ISA. : Most SoC are a standard mips core (r4k, etc.) with a bunch of peripherals. Yes, they do use the noraml MIPS ISA. It is a MIPS64r2 part. It does have a bunch of additional instructions that are leveraged off the CP2 coprocessor for crypto and related things. Its cache is different too, but every platform's cache is different. There's a number of hacks present to allow different images to run on different core. Or maybe this is what you are saying :- Warner