From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1JzE22-0004vs-W2 for qemu-devel@nongnu.org; Thu, 22 May 2008 12:52:47 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1JzE21-0004rD-Ac for qemu-devel@nongnu.org; Thu, 22 May 2008 12:52:46 -0400 Received: from [199.232.76.173] (port=53626 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1JzE21-0004r2-7b for qemu-devel@nongnu.org; Thu, 22 May 2008 12:52:45 -0400 Received: from relay01.mx.bawue.net ([193.7.176.67]:51426) by monty-python.gnu.org with esmtps (TLS-1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.60) (envelope-from ) id 1JzE21-0001N4-0z for qemu-devel@nongnu.org; Thu, 22 May 2008 12:52:45 -0400 Date: Thu, 22 May 2008 17:52:41 +0100 From: Thiemo Seufer Subject: Re: [Qemu-devel] Support For Octeon/Cavium CPU (MIPS system) Message-ID: <20080522165241.GA20195@networkno.de> References: <200805221427.26860.paul@codesourcery.com> <20080522.095542.-1350511548.imp@bsdimp.com> <200805221704.00480.paul@codesourcery.com> <20080522.101715.-233685094.imp@bsdimp.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20080522.101715.-233685094.imp@bsdimp.com> Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: paul@codesourcery.com, octane@alinto.com M. Warner Losh wrote: > In message: <200805221704.00480.paul@codesourcery.com> > Paul Brook writes: > : > : > I know that Cavium/octeon board are MIPS CPU. > : > : > : > : Not really. They're MIPS with extra weirdness. > : > > : > All SoCs are MIPS with extra documented weirdness. The OCTEON CPUs > : > aren't documented in a public... > : > : The Cavium cores are weirder than most. It doesn't use the normal MIPS ISA. > : Most SoC are a standard mips core (r4k, etc.) with a bunch of peripherals. > > Yes, they do use the noraml MIPS ISA. It is a MIPS64r2 part. AFAIU they invented a mode in their core which replaces (d)lwl/(d)lwr with different instructions for unaligned load/stores. :-( Thiemo