From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1JzItn-0006as-Gb for qemu-devel@nongnu.org; Thu, 22 May 2008 18:04:35 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1JzItl-0006Ze-QC for qemu-devel@nongnu.org; Thu, 22 May 2008 18:04:35 -0400 Received: from [199.232.76.173] (port=60928 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1JzItl-0006ZT-LY for qemu-devel@nongnu.org; Thu, 22 May 2008 18:04:33 -0400 Received: from mail2.shareable.org ([80.68.89.115]:50768) by monty-python.gnu.org with esmtps (TLS-1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.60) (envelope-from ) id 1JzItl-0000mu-Db for qemu-devel@nongnu.org; Thu, 22 May 2008 18:04:33 -0400 Date: Thu, 22 May 2008 23:04:27 +0100 From: Jamie Lokier Subject: Re: [Qemu-devel] Support For Octeon/Cavium CPU (MIPS system) Message-ID: <20080522220427.GA26229@shareable.org> References: <200805221427.26860.paul@codesourcery.com> <20080522.095542.-1350511548.imp@bsdimp.com> <200805221704.00480.paul@codesourcery.com> <20080522.101715.-233685094.imp@bsdimp.com> <20080522165241.GA20195@networkno.de> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20080522165241.GA20195@networkno.de> Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: paul@codesourcery.com, octane@alinto.com Thiemo Seufer wrote: > > Yes, they do use the noraml MIPS ISA. It is a MIPS64r2 part. > > AFAIU they invented a mode in their core which replaces (d)lwl/(d)lwr > with different instructions for unaligned load/stores. :-( The Alteon Tigon 2 gigabit ethernet processor did something similar, except it wasn't a mode but fixed. The documentation said it was because those particular instructions are covered by a patent, so they couldn't implement them. -- Jaie