[Qemu-devel] [PATCH] ARM: ldrex/strex only valid v6

[Qemu-devel] [PATCH] ARM: ldrex/strex only valid v6

[Adam Lackorzynski]

Hi,

ldrex and strex are only valid instructions for v6 and up.


Index: target-arm/translate.c
===================================================================
--- target-arm/translate.c	(revision 4571)
+++ target-arm/translate.c	(working copy)
@@ -6221,6 +6221,7 @@
                     rd = (insn >> 12) & 0xf;
                     if (insn & (1 << 23)) {
                         /* load/store exclusive */
+                        ARCH(6);
                         gen_movl_T1_reg(s, rn);
                         addr = cpu_T[1];
                         if (insn & (1 << 20)) {

Adam
-- 
Adam                 adam@os.inf.tu-dresden.de
  Lackorzynski         http://os.inf.tu-dresden.de/~adam/

Re: [Qemu-devel] [PATCH] ARM: ldrex/strex only valid v6

[Laurent Desnogues]

On Sun, May 25, 2008 at 11:51 AM, Adam Lackorzynski
<adam@os.inf.tu-dresden.de> wrote:
>
> ldrex and strex are only valid instructions for v6 and up.

There are many other places in translate.c that deal with the various
ldrex/strex instructions.  Some are v6, some others are v6K, some
are v6T2 and some are v7.  Did you check all of them? :-)


Laurent

Re: [Qemu-devel] [PATCH] ARM: ldrex/strex only valid v6

[Adam Lackorzynski]

On Sun May 25, 2008 at 13:18:07 +0200, Laurent Desnogues wrote:
> On Sun, May 25, 2008 at 11:51 AM, Adam Lackorzynski
> <adam@os.inf.tu-dresden.de> wrote:
> >
> > ldrex and strex are only valid instructions for v6 and up.
> 
> There are many other places in translate.c that deal with the various
> ldrex/strex instructions.  Some are v6, some others are v6K, some
> are v6T2 and some are v7.  Did you check all of them? :-)

No, that's just the one I stumbled upon. This should be better but I
probably didn't catch all of them.

Index: target-arm/translate.c
===================================================================
--- target-arm/translate.c	(revision 4586)
+++ target-arm/translate.c	(working copy)
@@ -6221,6 +6221,7 @@
                     rd = (insn >> 12) & 0xf;
                     if (insn & (1 << 23)) {
                         /* load/store exclusive */
+                        ARCH(6);
                         gen_movl_T1_reg(s, rn);
                         addr = cpu_T[1];
                         if (insn & (1 << 20)) {
@@ -6973,6 +6974,7 @@
                 }
             } else if ((insn & (1 << 23)) == 0) {
                 /* Load/store exclusive word.  */
+                ARCH(6);
                 gen_movl_T1_reg(s, rn);
                 addr = cpu_T[1];
                 if (insn & (1 << 20)) {
@@ -7017,6 +7019,7 @@
                 /* ??? These are not really atomic.  However we know
                    we never have multiple CPUs running in parallel,
                    so it is good enough.  */
+                ARCH(6);
                 op = (insn >> 4) & 0x3;
                 /* Must use a global reg for the address because we have
                    a conditional branch in the store instruction.  */
@@ -7070,6 +7073,7 @@
         } else {
             /* Load/store multiple, RFE, SRS.  */
             if (((insn >> 23) & 1) == ((insn >> 24) & 1)) {
+                ARCH(6);
                 /* Not available in user mode.  */
                 if (IS_USER(s))
                     goto illegal_op;


Adam
-- 
Adam                 adam@os.inf.tu-dresden.de
  Lackorzynski         http://os.inf.tu-dresden.de/~adam/