From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1K0XXp-0000F3-Dh for qemu-devel@nongnu.org; Mon, 26 May 2008 03:55:01 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1K0XXn-0000Ej-HB for qemu-devel@nongnu.org; Mon, 26 May 2008 03:55:00 -0400 Received: from [199.232.76.173] (port=44067 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1K0XXn-0000Eg-AQ for qemu-devel@nongnu.org; Mon, 26 May 2008 03:54:59 -0400 Received: from mx20.gnu.org ([199.232.41.8]:63594) by monty-python.gnu.org with esmtps (TLS-1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.60) (envelope-from ) id 1K0XXm-0003ka-RV for qemu-devel@nongnu.org; Mon, 26 May 2008 03:54:59 -0400 Received: from os.inf.tu-dresden.de ([141.76.48.99]) by mx20.gnu.org with esmtp (Exim 4.60) (envelope-from ) id 1K0XXl-0000aS-KZ for qemu-devel@nongnu.org; Mon, 26 May 2008 03:54:57 -0400 Received: from erwin.inf.tu-dresden.de ([141.76.48.80] helo=os.inf.tu-dresden.de) by os.inf.tu-dresden.de with esmtps (TLSv1:AES128-SHA:128) (Exim 4.69) id 1K0XXj-0000zI-Le for qemu-devel@nongnu.org; Mon, 26 May 2008 09:54:55 +0200 Date: Mon, 26 May 2008 09:54:53 +0200 From: Adam Lackorzynski Subject: Re: [Qemu-devel] [PATCH] ARM: ldrex/strex only valid v6 Message-ID: <20080526075453.GA6062@os.inf.tu-dresden.de> References: <20080525095106.GA7834@os.inf.tu-dresden.de> <761ea48b0805250418w2801a9ecta06985c63e719f79@mail.gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline In-Reply-To: <761ea48b0805250418w2801a9ecta06985c63e719f79@mail.gmail.com> Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org On Sun May 25, 2008 at 13:18:07 +0200, Laurent Desnogues wrote: > On Sun, May 25, 2008 at 11:51 AM, Adam Lackorzynski > wrote: > > > > ldrex and strex are only valid instructions for v6 and up. > > There are many other places in translate.c that deal with the various > ldrex/strex instructions. Some are v6, some others are v6K, some > are v6T2 and some are v7. Did you check all of them? :-) No, that's just the one I stumbled upon. This should be better but I probably didn't catch all of them. Index: target-arm/translate.c =================================================================== --- target-arm/translate.c (revision 4586) +++ target-arm/translate.c (working copy) @@ -6221,6 +6221,7 @@ rd = (insn >> 12) & 0xf; if (insn & (1 << 23)) { /* load/store exclusive */ + ARCH(6); gen_movl_T1_reg(s, rn); addr = cpu_T[1]; if (insn & (1 << 20)) { @@ -6973,6 +6974,7 @@ } } else if ((insn & (1 << 23)) == 0) { /* Load/store exclusive word. */ + ARCH(6); gen_movl_T1_reg(s, rn); addr = cpu_T[1]; if (insn & (1 << 20)) { @@ -7017,6 +7019,7 @@ /* ??? These are not really atomic. However we know we never have multiple CPUs running in parallel, so it is good enough. */ + ARCH(6); op = (insn >> 4) & 0x3; /* Must use a global reg for the address because we have a conditional branch in the store instruction. */ @@ -7070,6 +7073,7 @@ } else { /* Load/store multiple, RFE, SRS. */ if (((insn >> 23) & 1) == ((insn >> 24) & 1)) { + ARCH(6); /* Not available in user mode. */ if (IS_USER(s)) goto illegal_op; Adam -- Adam adam@os.inf.tu-dresden.de Lackorzynski http://os.inf.tu-dresden.de/~adam/