From: Jamie Lokier <jamie@shareable.org>
To: qemu-devel@nongnu.org
Subject: Re: [Qemu-devel] Threading Qemu
Date: Wed, 28 May 2008 13:39:59 +0100 [thread overview]
Message-ID: <20080528123959.GD19738@shareable.org> (raw)
In-Reply-To: <483D4FC8.5080708@bellard.org>
Fabrice Bellard wrote:
> I confirm, the general case is quite complicated. It is simpler to begin
> with an implementation where the host and guest CPUs have the same
> memory ordering constraints (e.g. x86 on x86 case).
I have just realised it is not _always_ correct even for x86 on x86,
for some flavours of x86 host CPU.
Qemu emulates a standard x86 with writes fully ordered. Guest code
will assume that.
But a few types of x86 host don't fully order writes. See
CONFIG_X86_OOSTORE and CONFIG_X86_PPRO_FENCE in Linux kernels - look
in linux/arch/x86/Kconfig.cpu.
On those, running multiple target CPUs as host threads on a
multiprocessor host may not be correct.
I'm not sure if the "sfence" instruction means this could apply to
some modern, mainstream x86 hosts too.
-- Jamie
next prev parent reply other threads:[~2008-05-28 12:40 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2008-05-28 6:31 [Qemu-devel] Threading Qemu mixado
2008-05-28 7:40 ` Izik Eidus
2008-05-28 12:27 ` Fabrice Bellard
2008-05-28 12:39 ` Jamie Lokier [this message]
2008-05-28 12:28 ` Jamie Lokier
2008-05-28 13:31 ` Paul Brook
-- strict thread matches above, loose matches on Subject: below --
2008-05-28 10:40 Mikael Regnell
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