From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1K2b5e-0002Df-DS for qemu-devel@nongnu.org; Sat, 31 May 2008 20:06:26 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1K2b5c-0002Cv-Qx for qemu-devel@nongnu.org; Sat, 31 May 2008 20:06:26 -0400 Received: from [199.232.76.173] (port=49631 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1K2b5c-0002Cr-I6 for qemu-devel@nongnu.org; Sat, 31 May 2008 20:06:24 -0400 Received: from mail.codesourcery.com ([65.74.133.4]:58247) by monty-python.gnu.org with esmtps (TLS-1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.60) (envelope-from ) id 1K2b5c-0004Xy-0I for qemu-devel@nongnu.org; Sat, 31 May 2008 20:06:24 -0400 From: Paul Brook Subject: Re: [Qemu-devel] Re: [PATCH 0/5] Debugger enhancements Date: Sun, 1 Jun 2008 01:06:14 +0100 References: <48414AC8.7080206@web.de> <484188D4.70103@web.de> <48419C01.2040607@bellard.org> In-Reply-To: <48419C01.2040607@bellard.org> MIME-Version: 1.0 Content-Type: text/plain; charset="iso-8859-15" Content-Transfer-Encoding: 7bit Content-Disposition: inline Message-Id: <200806010106.14958.paul@codesourcery.com> Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org > I don't think it is a good idea to say that breakpoints/watchpoints > apply to all processors. Such behavior should be handled at a higher level. > > It would also be interesting if the watchpoint/breakpoint implementation > could be used to implement CPU watchpoints and breakpoints (I am > thinking about the x86 DRx registers here). Watchpoints and breakpoints are architecture independent debugger features. The gdb break/watchpoints should be independent of any user visible debug hardware. I agree it probably makes sense for both to share an implementation though. > If this is the wanted behavior then the same system as the Self > Modifying Code on x86 should be used. Basically it consists in doing as > a MMU fault and single stepping one instruction after. Unfortunately I > fear the implementation will be complicated. FWIW I'm planning on reviving the instruction counting patches and making some modifications to the mmio TLB handling, which should provide infrastructure for doing this in a better way. Paul