From mboxrd@z Thu Jan  1 00:00:00 1970
Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43)
	id 1K6sFf-00034a-M7
	for qemu-devel@nongnu.org; Thu, 12 Jun 2008 15:14:27 -0400
Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43)
	id 1K6sFd-00034O-Dz
	for qemu-devel@nongnu.org; Thu, 12 Jun 2008 15:14:26 -0400
Received: from [199.232.76.173] (port=54290 helo=monty-python.gnu.org)
	by lists.gnu.org with esmtp (Exim 4.43) id 1K6sFd-00034H-1L
	for qemu-devel@nongnu.org; Thu, 12 Jun 2008 15:14:25 -0400
Received: from smtp6-g19.free.fr ([212.27.42.36]:51877)
	by monty-python.gnu.org with esmtp (Exim 4.60)
	(envelope-from <vincent.palatin_qemu@polytechnique.org>)
	id 1K6sFc-0001mn-Pg
	for qemu-devel@nongnu.org; Thu, 12 Jun 2008 15:14:25 -0400
Received: from smtp6-g19.free.fr (localhost.localdomain [127.0.0.1])
	by smtp6-g19.free.fr (Postfix) with ESMTP id 7316A5FE5D
	for <qemu-devel@nongnu.org>; Thu, 12 Jun 2008 21:14:20 +0200 (CEST)
Received: from [192.168.0.20] (adsl.palats.com [82.233.120.18])
	by smtp6-g19.free.fr (Postfix) with ESMTP id 552FA5FE47
	for <qemu-devel@nongnu.org>; Thu, 12 Jun 2008 21:14:20 +0200 (CEST)
From: Vincent Palatin <vincent.palatin_qemu@polytechnique.org>
Date: Thu, 12 Jun 2008 21:17:53 +0200
MIME-Version: 1.0
Content-Type: Multipart/Mixed;
  boundary="Boundary-00=_iZXUIrVILIg0Si5"
Message-Id: <200806122117.54077.vincent.palatin_qemu@polytechnique.org>
Subject: [Qemu-devel] [PATCH] ARM: fix CPS instruction
Reply-To: qemu-devel@nongnu.org
List-Id: qemu-devel.nongnu.org
List-Unsubscribe: <http://lists.nongnu.org/mailman/listinfo/qemu-devel>,
	<mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>
List-Archive: <http://lists.gnu.org/pipermail/qemu-devel>
List-Post: <mailto:qemu-devel@nongnu.org>
List-Help: <mailto:qemu-devel-request@nongnu.org?subject=help>
List-Subscribe: <http://lists.nongnu.org/mailman/listinfo/qemu-devel>,
	<mailto:qemu-devel-request@nongnu.org?subject=subscribe>
To: qemu-devel@nongnu.org

--Boundary-00=_iZXUIrVILIg0Si5
Content-Type: text/plain;
  charset="us-ascii"
Content-Transfer-Encoding: 7bit
Content-Disposition: inline

Dear developers,

I attach a patch with 2 fixes for the ARMv6 instruction "CPS".
According to ARM Reference Manual (DDI0100 A4.1.16), 
bit 5 is fixed to 0 (bit 4 is the MSB of the mode), so the instruction mask 
should be  0x0ff10020 not 0x0ff10010.
Besides, mmod flag is bit 17 (b14 is SBZ)

-- 
Vincent

--Boundary-00=_iZXUIrVILIg0Si5
Content-Type: text/x-diff;
  charset="us-ascii";
  name="arm_cps.patch"
Content-Transfer-Encoding: 7bit
Content-Disposition: attachment;
	filename="arm_cps.patch"

Index: target-arm/translate.c
===================================================================
--- target-arm/translate.c	(revision 4740)
+++ target-arm/translate.c	(working copy)
@@ -5801,7 +5801,7 @@
             /* Coprocessor double register transfer.  */
         } else if ((insn & 0x0f000010) == 0x0e000010) {
             /* Additional coprocessor register transfer.  */
-        } else if ((insn & 0x0ff10010) == 0x01000000) {
+        } else if ((insn & 0x0ff10020) == 0x01000000) {
             uint32_t mask;
             uint32_t val;
             /* cps (privileged) */
@@ -5818,7 +5818,7 @@
                 if (insn & (1 << 18))
                     val |= mask;
             }
-            if (insn & (1 << 14)) {
+            if (insn & (1 << 17)) {
                 mask |= CPSR_M;
                 val |= (insn & 0x1f);
             }

--Boundary-00=_iZXUIrVILIg0Si5--