Re: [Qemu-devel] Re: [PATCH][ARM] Fix wrong destination register for smuad, smusd, smlad, smlsd

[Vincent Palatin <vincent.palatin_qemu@polytechnique.org>]

[-- Attachment #1: Type: text/plain, Size: 1685 bytes --]

Paul wrote:
> I'm generally more interested in the description/explanation of the patches
> themselves.  Saying "FOO works" is nice, but not as nice as convincing me
> that you understand both the code you're changing, the arm architecture,
> and that the two agree :-)

That's fairly right, but I'm not sure that the problem lays here.
Indeed, as Laurent mentioned in his mail on monday, my 2 previous patchs with 
fixes for ARM instructions were not integrated too while I hope I've put a 
fairly descriptive text with them ( I re-attach them if you have any comment)

--  
Vincent

---------- Forwarded message  ----------
Suject : [PATCH] ARM: fix carry flags for ARMv6 unsigned SIMD operations

[PATCH] ARM: fix carry flags for ARMv6 unsigned SIMD operations
On ARMv6 emulation, I have caught some cases where the GE flags were
badly set after a "uadd8" operation.
After a quick code review, it seems to be a bad cut-n-paste between
16-bit and 8-bit UADD/USUB, indeed UADD8/USUB8 tries to set GE bits by
pair instead of one at a time.
Besides, the addition operations (UADD8/UADD16) set GE bits to "NOT
carry" instead of "carry" (probably once again due to a copy of the 
substraction code which sets flags to "NOT borrow")

I attach a patch to fix those issues. (arith_ge.patch)


---------- Forwarded message  ----------
Subject: [PATCH] ARM: fix CPS instruction

I attach a patch with 2 fixes for the ARMv6 instruction "CPS".
According to ARM Reference Manual (DDI0100 A4.1.16), 
bit 5 is fixed to 0 (bit 4 is the MSB of the mode), so the instruction mask 
should be  0x0ff10020 not 0x0ff10010.
Besides, mmod flag is bit 17 (b14 is SBZ)


[-- Attachment #2: arith_ge.patch --]
[-- Type: text/x-diff, Size: 935 bytes --]

Index: target-arm/helper.c
===================================================================
--- target-arm/helper.c	(revision 4740)
+++ target-arm/helper.c	(working copy)
@@ -2059,7 +2059,7 @@
     uint32_t sum; \
     sum = (uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b); \
     RESULT(sum, n, 16); \
-    if ((sum >> 16) == 0) \
+    if ((sum >> 16) == 1) \
         ge |= 3 << (n * 2); \
     } while(0)
 
@@ -2067,8 +2067,8 @@
     uint32_t sum; \
     sum = (uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b); \
     RESULT(sum, n, 8); \
-    if ((sum >> 8) == 0) \
-        ge |= 3 << (n * 2); \
+    if ((sum >> 8) == 1) \
+        ge |= 1 << n; \
     } while(0)
 
 #define SUB16(a, b, n) do { \
@@ -2084,7 +2084,7 @@
     sum = (uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b); \
     RESULT(sum, n, 8); \
     if ((sum >> 8) == 0) \
-        ge |= 3 << (n * 2); \
+        ge |= 1 << n; \
     } while(0)
 
 #define PFX u


[-- Attachment #3: arm_cps.patch --]
[-- Type: text/x-diff, Size: 858 bytes --]

Index: target-arm/translate.c
===================================================================
--- target-arm/translate.c	(revision 4740)
+++ target-arm/translate.c	(working copy)
@@ -5801,7 +5801,7 @@
             /* Coprocessor double register transfer.  */
         } else if ((insn & 0x0f000010) == 0x0e000010) {
             /* Additional coprocessor register transfer.  */
-        } else if ((insn & 0x0ff10010) == 0x01000000) {
+        } else if ((insn & 0x0ff10020) == 0x01000000) {
             uint32_t mask;
             uint32_t val;
             /* cps (privileged) */
@@ -5818,7 +5818,7 @@
                 if (insn & (1 << 18))
                     val |= mask;
             }
-            if (insn & (1 << 14)) {
+            if (insn & (1 << 17)) {
                 mask |= CPSR_M;
                 val |= (insn & 0x1f);
             }