From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1KBaLA-0003eR-CR for qemu-devel@nongnu.org; Wed, 25 Jun 2008 15:07:36 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1KBaL8-0003eF-Sq for qemu-devel@nongnu.org; Wed, 25 Jun 2008 15:07:35 -0400 Received: from [199.232.76.173] (port=51489 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1KBaL8-0003eC-Na for qemu-devel@nongnu.org; Wed, 25 Jun 2008 15:07:34 -0400 Received: from smtp6-g19.free.fr ([212.27.42.36]:53283) by monty-python.gnu.org with esmtp (Exim 4.60) (envelope-from ) id 1KBaL8-00025u-5U for qemu-devel@nongnu.org; Wed, 25 Jun 2008 15:07:34 -0400 From: Vincent Palatin Subject: Re: [Qemu-devel] Re: [PATCH][ARM] Fix wrong destination register for smuad, smusd, smlad, smlsd Date: Wed, 25 Jun 2008 21:11:17 +0200 References: <761ea48b0806230240h31745caaj24e9c6f9ce80eea2@mail.gmail.com> <761ea48b0806251015t4088f674hcacbc256b7a6dc0f@mail.gmail.com> <200806251827.37618.paul@codesourcery.com> In-Reply-To: <200806251827.37618.paul@codesourcery.com> MIME-Version: 1.0 Content-Type: Multipart/Mixed; boundary="Boundary-00=_VhpYImzBwbeUbQT" Message-Id: <200806252111.17831.vincent.palatin_qemu@polytechnique.org> Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Laurent Desnogues , Paul Brook --Boundary-00=_VhpYImzBwbeUbQT Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Content-Disposition: inline Paul wrote: > I'm generally more interested in the description/explanation of the patch= es > themselves. Saying "FOO works" is nice, but not as nice as convincing me > that you understand both the code you're changing, the arm architecture, > and that the two agree :-) That's fairly right, but I'm not sure that the problem lays here. Indeed, as Laurent mentioned in his mail on monday, my 2 previous patchs wi= th=20 fixes for ARM instructions were not integrated too while I hope I've put a= =20 fairly descriptive text with them ( I re-attach them if you have any commen= t) =2D- =20 Vincent =2D--------- Forwarded message ---------- Suject : [PATCH] ARM: fix carry flags for ARMv6 unsigned SIMD operations [PATCH] ARM: fix carry flags for ARMv6 unsigned SIMD operations On ARMv6 emulation, I have caught some cases where the GE flags were badly set after a "uadd8" operation. After a quick code review, it seems to be a bad cut-n-paste between 16-bit and 8-bit UADD/USUB, indeed UADD8/USUB8 tries to set GE bits by pair instead of one at a time. Besides, the addition operations (UADD8/UADD16) set GE bits to "NOT carry" instead of "carry" (probably once again due to a copy of the=20 substraction code which sets flags to "NOT borrow") I attach a patch to fix those issues. (arith_ge.patch) =2D--------- Forwarded message ---------- Subject: [PATCH] ARM: fix CPS instruction I attach a patch with 2 fixes for the ARMv6 instruction "CPS". According to ARM Reference Manual (DDI0100 A4.1.16),=20 bit 5 is fixed to 0 (bit 4 is the MSB of the mode), so the instruction mask= =20 should be =A00x0ff10020 not 0x0ff10010. Besides, mmod flag is bit 17 (b14 is SBZ) --Boundary-00=_VhpYImzBwbeUbQT Content-Type: text/x-diff; charset="iso-8859-1"; name="arith_ge.patch" Content-Transfer-Encoding: 7bit Content-Disposition: attachment; filename="arith_ge.patch" Index: target-arm/helper.c =================================================================== --- target-arm/helper.c (revision 4740) +++ target-arm/helper.c (working copy) @@ -2059,7 +2059,7 @@ uint32_t sum; \ sum = (uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b); \ RESULT(sum, n, 16); \ - if ((sum >> 16) == 0) \ + if ((sum >> 16) == 1) \ ge |= 3 << (n * 2); \ } while(0) @@ -2067,8 +2067,8 @@ uint32_t sum; \ sum = (uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b); \ RESULT(sum, n, 8); \ - if ((sum >> 8) == 0) \ - ge |= 3 << (n * 2); \ + if ((sum >> 8) == 1) \ + ge |= 1 << n; \ } while(0) #define SUB16(a, b, n) do { \ @@ -2084,7 +2084,7 @@ sum = (uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b); \ RESULT(sum, n, 8); \ if ((sum >> 8) == 0) \ - ge |= 3 << (n * 2); \ + ge |= 1 << n; \ } while(0) #define PFX u --Boundary-00=_VhpYImzBwbeUbQT Content-Type: text/x-diff; charset="iso-8859-1"; name="arm_cps.patch" Content-Transfer-Encoding: 7bit Content-Disposition: attachment; filename="arm_cps.patch" Index: target-arm/translate.c =================================================================== --- target-arm/translate.c (revision 4740) +++ target-arm/translate.c (working copy) @@ -5801,7 +5801,7 @@ /* Coprocessor double register transfer. */ } else if ((insn & 0x0f000010) == 0x0e000010) { /* Additional coprocessor register transfer. */ - } else if ((insn & 0x0ff10010) == 0x01000000) { + } else if ((insn & 0x0ff10020) == 0x01000000) { uint32_t mask; uint32_t val; /* cps (privileged) */ @@ -5818,7 +5818,7 @@ if (insn & (1 << 18)) val |= mask; } - if (insn & (1 << 14)) { + if (insn & (1 << 17)) { mask |= CPSR_M; val |= (insn & 0x1f); } --Boundary-00=_VhpYImzBwbeUbQT--