From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1KCxjx-0001p8-WA for qemu-devel@nongnu.org; Sun, 29 Jun 2008 10:18:54 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1KCxjx-0001nf-9m for qemu-devel@nongnu.org; Sun, 29 Jun 2008 10:18:53 -0400 Received: from [199.232.76.173] (port=60354 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1KCxjx-0001nV-40 for qemu-devel@nongnu.org; Sun, 29 Jun 2008 10:18:53 -0400 Received: from il.qumranet.com ([212.179.150.194]:47106) by monty-python.gnu.org with esmtp (Exim 4.60) (envelope-from ) id 1KCxjw-0004gh-Pv for qemu-devel@nongnu.org; Sun, 29 Jun 2008 10:18:53 -0400 Date: Sun, 29 Jun 2008 17:18:52 +0300 From: Gleb Natapov Subject: Re: [Qemu-devel] [PATCH 1/3] Change qemu_set_irq() to return status information. Message-ID: <20080629141852.GD31298@minantech.com> References: <20080629140120.5626.1590.stgit@gleb-debian.qumranet.com.qumranet.com> <20080629140220.5626.33071.stgit@gleb-debian.qumranet.com.qumranet.com> <486798A9.7060308@qumranet.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <486798A9.7060308@qumranet.com> Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Avi Kivity Cc: qemu-devel@nongnu.org On Sun, Jun 29, 2008 at 05:14:01PM +0300, Avi Kivity wrote: > Gleb Natapov wrote: >> The return value is less then zero if interrupt is masked, zero if it >> is known that interrupt is lost (due to coalescing) or greater then zero >> if interrupt is delivered or was successfully queued for delivery by >> interrupt controller. Device emulation can use this info as it pleases. >> Included patch adds detection of interrupt coalescing into PIC and APIC >> code for edge triggered interrupts. >> > > Instead of negative/positive/zero, consider returning an enum for > readability. > I thought about that, but I sometimes do arithmetics on those values (when delivering interrupt to multiple CPUs), so result can be more then 1 sometimes. -- Gleb.