From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1KD1Mh-0008Cr-NF for qemu-devel@nongnu.org; Sun, 29 Jun 2008 14:11:07 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1KD1Mg-0008Be-Rt for qemu-devel@nongnu.org; Sun, 29 Jun 2008 14:11:06 -0400 Received: from [199.232.76.173] (port=49921 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1KD1Mg-0008BU-AC for qemu-devel@nongnu.org; Sun, 29 Jun 2008 14:11:06 -0400 Received: from mail.codesourcery.com ([65.74.133.4]:50299) by monty-python.gnu.org with esmtps (TLS-1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.60) (envelope-from ) id 1KD1Mf-0007i8-Lr for qemu-devel@nongnu.org; Sun, 29 Jun 2008 14:11:05 -0400 From: Paul Brook Subject: Re: [Qemu-devel] [PATCH 1/3] Change qemu_set_irq() to return status information. Date: Sun, 29 Jun 2008 19:11:01 +0100 References: <20080629140120.5626.1590.stgit@gleb-debian.qumranet.com.qumranet.com> <200806291538.10664.paul@codesourcery.com> <20080629154025.GB12972@minantech.com> In-Reply-To: <20080629154025.GB12972@minantech.com> MIME-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: 7bit Content-Disposition: inline Message-Id: <200806291911.02093.paul@codesourcery.com> Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Gleb Natapov Cc: qemu-devel@nongnu.org On Sunday 29 June 2008, Gleb Natapov wrote: > On Sun, Jun 29, 2008 at 03:38:10PM +0100, Paul Brook wrote: > > On Sunday 29 June 2008, Gleb Natapov wrote: > > > The return value is less then zero if interrupt is masked, zero if it > > > is known that interrupt is lost (due to coalescing) or greater then > > > zero if interrupt is delivered or was successfully queued for delivery > > > by interrupt controller. Device emulation can use this info as it > > > pleases. Included patch adds detection of interrupt coalescing into PIC > > > and APIC code for edge triggered interrupts. > > > > This is woefully incomplete, and obviously hasn't been tested on anything > > other than x86 targets. > > Yes, you are right. It was not tested on anything other than x86. Do you > see why this approach will not work on other architectures? Can you > elaborate on what current patch is missing for other architectures > support? Well, if nothing else there's 40+ interrupt controllers that need fixing up before it'll even compile cleanly (mismatching function prototypes are IMHO not acceptable). > The initial goal is to fix RTC/PIT problem on x86 while do not > hurt any other architectures in any way. Well, you're introducing a fair amount of churn, so it'd better work for other architectures too. Otherwise we're liable to have to rewrite it later. I can't say offhand whether your approach will work on other architectures. qemu has quite a wide variety of interrupt controllers and timers, you should check whether they fit into your model. Paul