From mboxrd@z Thu Jan  1 00:00:00 1970
Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43)
	id 1KM1PG-0002q5-Of
	for qemu-devel@nongnu.org; Thu, 24 Jul 2008 10:02:58 -0400
Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43)
	id 1KM1PF-0002p8-7A
	for qemu-devel@nongnu.org; Thu, 24 Jul 2008 10:02:58 -0400
Received: from [199.232.76.173] (port=37574 helo=monty-python.gnu.org)
	by lists.gnu.org with esmtp (Exim 4.43) id 1KM1PF-0002p4-3K
	for qemu-devel@nongnu.org; Thu, 24 Jul 2008 10:02:57 -0400
Received: from mail.codesourcery.com ([65.74.133.4]:33233)
	by monty-python.gnu.org with esmtps
	(TLS-1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.60)
	(envelope-from <paul@codesourcery.com>) id 1KM1PE-0002Nt-Op
	for qemu-devel@nongnu.org; Thu, 24 Jul 2008 10:02:57 -0400
From: Paul Brook <paul@codesourcery.com>
Subject: Re: [Qemu-devel] Weird behavior while using the instruction counter
Date: Thu, 24 Jul 2008 15:02:52 +0100
References: <3e1533500807240342s15e6e508kd1d49152b0892e9f@mail.gmail.com>
	<200807241344.35106.paul@codesourcery.com>
	<3e1533500807240654x67920d8ao55c420390f421ee3@mail.gmail.com>
In-Reply-To: <3e1533500807240654x67920d8ao55c420390f421ee3@mail.gmail.com>
MIME-Version: 1.0
Content-Type: text/plain;
  charset="iso-8859-1"
Content-Transfer-Encoding: 7bit
Content-Disposition: inline
Message-Id: <200807241502.53396.paul@codesourcery.com>
Reply-To: qemu-devel@nongnu.org
List-Id: qemu-devel.nongnu.org
List-Unsubscribe: <http://lists.nongnu.org/mailman/listinfo/qemu-devel>,
	<mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>
List-Archive: <http://lists.gnu.org/pipermail/qemu-devel>
List-Post: <mailto:qemu-devel@nongnu.org>
List-Help: <mailto:qemu-devel-request@nongnu.org?subject=help>
List-Subscribe: <http://lists.nongnu.org/mailman/listinfo/qemu-devel>,
	<mailto:qemu-devel-request@nongnu.org?subject=subscribe>
To: qemu-devel@nongnu.org
Cc: Luis Pureza <pureza@student.dei.uc.pt>

> > No. You're assuming the IO trap occurs on the last instruction, which not
> > true.  The problem is that cpu_exec_nocache introduces a second TB with
> > the same lookup key(pc+flags). cpu_io_recompile (and possibly other
> > places) assume the currently executing TB is the only tb that matches. It
> > needs to invalidate the original TB (if it exists) as well as the
> > uncached one.
>
> Obviously, you're right. I was testing with blocks of a single
> instruction. What do you think of this:
>
>  if (tb != &tbs[0] && (tb - 1)->pc == tb->pc) {
>         tb_phys_invalidate(tb - 1, -1);
>  }

No. There's no guarantee that the TBs are consecutive.

Paul