From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1KTIzV-0003cB-OX for qemu-devel@nongnu.org; Wed, 13 Aug 2008 12:14:29 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1KTIzU-0003bD-3F for qemu-devel@nongnu.org; Wed, 13 Aug 2008 12:14:29 -0400 Received: from [199.232.76.173] (port=39968 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1KTIzT-0003b2-O2 for qemu-devel@nongnu.org; Wed, 13 Aug 2008 12:14:27 -0400 Received: from smtp.eu.citrix.com ([62.200.22.115]:9709) by monty-python.gnu.org with esmtp (Exim 4.60) (envelope-from ) id 1KTIzT-0003hw-9b for qemu-devel@nongnu.org; Wed, 13 Aug 2008 12:14:27 -0400 Received: from samy by implementation.famille.thibault.fr with local (Exim 4.69) (envelope-from ) id 1KTIzR-0003iU-RZ for qemu-devel@nongnu.org; Wed, 13 Aug 2008 18:14:25 +0200 Date: Wed, 13 Aug 2008 17:14:25 +0100 From: Samuel Thibault Subject: Re: [Qemu-devel] [PATCH] Flush pending AIO on reboot and shutdown. Message-ID: <20080813161425.GV6165@implementation.uk.xensource.com> References: <20080813132358.17672.68212.stgit@gleb-debian.qumranet.com.qumranet.com> <20080813134608.GN6165@implementation.uk.xensource.com> <20080813135941.GB17567@minantech.com> <20080813140641.GP6165@implementation.uk.xensource.com> <20080813142557.GD17567@minantech.com> <20080813142904.GR6165@implementation.uk.xensource.com> <20080813144148.GE17567@minantech.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20080813144148.GE17567@minantech.com> Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Avi Kivity wrote: > Why not? IIUC triple fault is exported as a cpu pin, which the chipset/ > motherboard wires into the board-level reset line. Ah ok, I didn't know it was propagated further than the cpu. Probably a good thing actually :) > I think the bios can expect the IDE hardware (or any other device) to be > quiescent on entry. It doesn't make sense to initiate an explicit reset > immediately after boot; that would slow things down. Well, the Bios reset entry could be entered by "accident" too :) Actually windows drivers used to break my video board so badly that I had to manually reset my machine before booting Linux. Well, anyway, I agree with Anthony: the IDE emulation should behave like hardware: try to cancel pending requests and wait for everything to finish, instead of possibly writing what the bios puts in the being written pages :) And it should reset the DMA engines too. The block layer itself could have a last sync check. Samuel