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Date: Thu, 21 Aug 2008 17:14:51 +0300
From: Gleb Natapov <gleb@qumranet.com>
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Subject: [Qemu-devel] Re: [Bochs-developers] BIOS, ACPI,
	CMOS and Windows EvenID: 4
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To: Kevin O'Connor <kevin@koconnor.net>
Cc: bochs-developers@lists.sourceforge.net, qemu-devel@nongnu.org, Sebastian Herbszt <herbszt@gmx.de>

On Thu, Aug 21, 2008 at 07:45:37AM -0400, Kevin O'Connor wrote:
> The ACPI support in bochs bios is already 440fx specific, so I don't
> see a problem with adding another chipset specific rule.
So is something like this should be OK:


Index: acpi-dsdt.dsl
===================================================================
RCS file: /cvsroot/bochs/bochs/bios/acpi-dsdt.dsl,v
retrieving revision 1.3
diff -u -r1.3 acpi-dsdt.dsl
--- acpi-dsdt.dsl	26 Jan 2008 09:15:27 -0000	1.3
+++ acpi-dsdt.dsl	21 Aug 2008 14:13:35 -0000
@@ -27,20 +27,6 @@
 {
     Scope (\)
     {
-        /* CMOS memory access */
-        OperationRegion (CMS, SystemIO, 0x70, 0x02)
-        Field (CMS, ByteAcc, NoLock, Preserve)
-        {
-            CMSI,   8,
-            CMSD,   8
-        }
-        Method (CMRD, 1, NotSerialized)
-        {
-            Store (Arg0, CMSI)
-            Store (CMSD, Local0)
-            Return (Local0)
-        }
-
         /* Debug Output */
         OperationRegion (DBG, SystemIO, 0xb044, 0x04)
         Field (DBG, DWordAcc, NoLock, Preserve)
@@ -56,6 +42,12 @@
             Name (_HID, EisaId ("PNP0A03"))
             Name (_ADR, 0x00)
             Name (_UID, 1)
+            OperationRegion (I440, PCI_Config, 0x60, 0x02)
+            Field (I440, ByteAcc, NoLock, Preserve)
+            {
+                 CM34,   8,
+                 CM35,   8,
+            }
             Name(_PRT, Package() {
                 /* PCI IRQ routing table, example from ACPI 2.0a specification,
                    section 6.2.8.1 */
@@ -149,7 +141,9 @@
                 CreateDWordField (MEMP, \_SB.PCI0._CRS.MEMF._MAX, PMAX)
                 CreateDWordField (MEMP, \_SB.PCI0._CRS.MEMF._LEN, PLEN)
                 /* compute available RAM */
-                Add(CMRD(0x34), ShiftLeft(CMRD(0x35), 8), Local0)
+                Store(CM34, Local1)
+                Store(CM35, Local2)
+                Add(Local1, ShiftLeft(Local2, 8), Local0)
                 ShiftLeft(Local0, 16, Local0)
                 Add(Local0, 0x1000000, Local0)
                 /* update field of last region */
Index: rombios32.c
===================================================================
RCS file: /cvsroot/bochs/bochs/bios/rombios32.c,v
retrieving revision 1.29
diff -u -r1.29 rombios32.c
--- rombios32.c	30 Jul 2008 15:13:40 -0000	1.29
+++ rombios32.c	21 Aug 2008 14:13:36 -0000
@@ -677,6 +677,8 @@
                 elcr[0], elcr[1]);
     } else if (vendor_id == PCI_VENDOR_ID_INTEL && device_id == PCI_DEVICE_ID_INTEL_82441) {
         /* i440 PCI bridge */
+        pci_config_writeb(d, 0x60, cmos_readb(0x34));
+        pci_config_writeb(d, 0x61, cmos_readb(0x35));
         bios_shadow_init(d);
     }
 }
--
			Gleb.