Re: [Qemu-devel] [PATCH] Ignore IDE command if issued while IDE is busy.

[Gleb Natapov <gleb@qumranet.com>]

On Thu, Aug 21, 2008 at 02:46:49PM -0500, Anthony Liguori wrote:
>> @@ -2539,6 +2561,10 @@ static uint32_t ide_data_readl(void *opaque, uint32_t addr)
>>      uint8_t *p;
>>      int ret;
>>  +    /* PIO data access allowed only when DRQ bit is set */
>> +    if (!(s->status & DRQ_STAT))
>> +        return;
>>   
>
> This function returns a uint32_t but you just have a return; here.
>
Well, the behavior is undefined, so why not return garbage? ;)

---

    Ignore IDE command if issued while IDE is busy.
    
    Feature, Sector Count, LBA Low/Mid/High and Device registers should be
    written only when both BSY and DRQ are cleared to zero.
    Command register shall only be written when BSY and DRQ are set to zero
    for all commands except DEVICE RESET.
    Data Port register shall be accessed for host PIO data transfer only when
    DRQ is set to one.
    
    Signed-off-by: Gleb Natapov <gleb@qumranet.com>

diff --git a/hw/ide.c b/hw/ide.c
index 6b14e8f..1e60591 100644
--- a/hw/ide.c
+++ b/hw/ide.c
@@ -1981,6 +1981,11 @@ static void ide_ioport_write(void *opaque, uint32_t addr, uint32_t val)
 #endif
 
     addr &= 7;
+
+    /* ignore writes to command block while busy with previous command */
+    if (addr != 7 && (ide_if->cur_drive->status & (BUSY_STAT|DRQ_STAT)))
+        return;
+
     switch(addr) {
     case 0:
         break;
@@ -2040,6 +2045,10 @@ static void ide_ioport_write(void *opaque, uint32_t addr, uint32_t val)
         if (s != ide_if && !s->bs)
             break;
 
+        /* Only DEVICE RESET is allowed while BSY or/and DRQ are set */
+        if ((s->status & (BUSY_STAT|DRQ_STAT)) && val != WIN_DEVICE_RESET)
+            break;
+
         switch(val) {
         case WIN_IDENTIFY:
             if (s->bs && !s->is_cdrom) {
@@ -2498,6 +2507,10 @@ static void ide_data_writew(void *opaque, uint32_t addr, uint32_t val)
     IDEState *s = ((IDEState *)opaque)->cur_drive;
     uint8_t *p;
 
+    /* PIO data access allowed only when DRQ bit is set */
+    if (!(s->status & DRQ_STAT))
+        return;
+
     p = s->data_ptr;
     *(uint16_t *)p = le16_to_cpu(val);
     p += 2;
@@ -2511,6 +2524,11 @@ static uint32_t ide_data_readw(void *opaque, uint32_t addr)
     IDEState *s = ((IDEState *)opaque)->cur_drive;
     uint8_t *p;
     int ret;
+
+    /* PIO data access allowed only when DRQ bit is set */
+    if (!(s->status & DRQ_STAT))
+        return 0;
+
     p = s->data_ptr;
     ret = cpu_to_le16(*(uint16_t *)p);
     p += 2;
@@ -2525,6 +2543,10 @@ static void ide_data_writel(void *opaque, uint32_t addr, uint32_t val)
     IDEState *s = ((IDEState *)opaque)->cur_drive;
     uint8_t *p;
 
+    /* PIO data access allowed only when DRQ bit is set */
+    if (!(s->status & DRQ_STAT))
+        return;
+
     p = s->data_ptr;
     *(uint32_t *)p = le32_to_cpu(val);
     p += 4;
@@ -2539,6 +2561,10 @@ static uint32_t ide_data_readl(void *opaque, uint32_t addr)
     uint8_t *p;
     int ret;
 
+    /* PIO data access allowed only when DRQ bit is set */
+    if (!(s->status & DRQ_STAT))
+        return 0;
+
     p = s->data_ptr;
     ret = cpu_to_le32(*(uint32_t *)p);
     p += 4;
--
			Gleb.