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Date: Sat, 23 Aug 2008 19:22:53 +0300
From: Gleb Natapov <gleb@qumranet.com>
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Subject: [Qemu-devel] Re: [Bochs-developers] BIOS, ACPI,
	CMOS and Windows EvenID: 4
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To: Sebastian Herbszt <herbszt@gmx.de>
Cc: bochs-developers@lists.sourceforge.net, Kevin O'Connor <kevin@koconnor.net>, qemu-devel@nongnu.org

On Fri, Aug 22, 2008 at 12:37:32AM +0200, Sebastian Herbszt wrote:
>> diff -u -r1.29 rombios32.c
>> --- rombios32.c 30 Jul 2008 15:13:40 -0000 1.29
>> +++ rombios32.c 21 Aug 2008 14:13:36 -0000
>> @@ -677,6 +677,8 @@
>>                 elcr[0], elcr[1]);
>>     } else if (vendor_id == PCI_VENDOR_ID_INTEL && device_id == PCI_DEVICE_ID_INTEL_82441) {
>>         /* i440 PCI bridge */
>> +        pci_config_writeb(d, 0x60, cmos_readb(0x34));
>> +        pci_config_writeb(d, 0x61, cmos_readb(0x35));
>>         bios_shadow_init(d);
>>     }
>> }
>
> I am not sure writing arbitrary values to those registers is such a good idea. Some OS,
> driver or application could rely on the information stored there.
Currently nothing is written to memory configuration registers at all,
so if there is an application that depend on this values to be correct
it will be broken today too.

> It would also be possible to program those DRBx registers correctly up to memory
> value of 1GB (or 2GB by using the info from the 440GX) and compute the pci hole properly,
> then just fall back to 0xe0000000 if the memory size does exceed 1GB.
Is there a need for 3GB pci hole especially on a system with only 1GB
of main memory?

> Hard coding the hole start to 0xe0000000, like you did in your first patch, looks like the
> easiest solution tho.
Yes, and I think it is good enough. What is the procedure of pushing the
patch into bochs tree?

--
			Gleb.