[Qemu-devel] sparc 64-bit fsr problem

[Vince Weaver <vince@csl.cornell.edu>]

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Hello

on SPARC v9 the floating point status register (fsr) was extended 
to 64-bits, and 3 additional condtion codes were added in the upper 
32-bits (fcc1-fcc3).

The current qemu code doesn't handle this properly, using 32-bit shifts to 
access the condition codes which doesn't work unless you are only using 
fcc0.

Attached is code that shows the problem.

I've attempted to fix this myself but I am having trouble trying to get 
the gen_mov_reg_FCC0() and gen_mov_reg_FCC1() functions in 
target-sparc/translate.c to use 64-bit shifts.

In addition the floating point compare instructions need to be fixed.
Below is my attempt to make them work properly.

Vince


--- op_helper.c.orig	2008-08-28 17:25:22.000000000 -0400
+++ op_helper.c	2008-08-28 17:27:42.000000000 -0400
@@ -746,10 +746,10 @@
      {                                                                   \
          target_ulong new_fsr;                                           \
                                                                          \
-        env->fsr &= ~((FSR_FCC1 | FSR_FCC0) << FS);                     \
+        env->fsr &= ~((target_ulong) (FSR_FCC1 | FSR_FCC0) << FS);      \
          switch (glue(size, _compare) (reg1, reg2, &env->fp_status)) {   \
          case float_relation_unordered:                                  \
-            new_fsr = (FSR_FCC1 | FSR_FCC0) << FS;                      \
+            new_fsr = (target_ulong)(FSR_FCC1 | FSR_FCC0) << FS;        \
              if ((env->fsr & FSR_NVM) || TRAP) {                         \
                  env->fsr |= new_fsr;                                    \
                  env->fsr |= FSR_NVC;                                    \
@@ -760,10 +760,10 @@
              }                                                           \
              break;                                                      \
          case float_relation_less:                                       \
-            new_fsr = FSR_FCC0 << FS;                                   \
+            new_fsr = (target_ulong)FSR_FCC0 << FS;                     \
              break;                                                      \
          case float_relation_greater:                                    \
-            new_fsr = FSR_FCC1 << FS;                                   \
+	   new_fsr = (target_ulong)FSR_FCC1 << FS;                      \
              break;                                                      \
          default:                                                        \
              new_fsr = 0;                                                \


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! Compile with: 
! as -Av8plus -o fcc2_test.o fcc2_test.s ; ld -o fcc2_test fcc2_test.o

!     + Syscalls have number in %g1, options in %o0,%o1,...
!	Result returned in %o0
!	Linux syscall is called by "ta 0x10"

.equ SYSCALL_EXIT,1	
.equ SYSCALL_WRITE,4

.equ STDOUT,1

	.globl _start
_start:
       set	float1,%g1
       ldd	[%g1],%f6
       set	float2,%g1
       ldd	[%g1],%f8

       fcmped  %fcc2, %f6, %f8

       set     float3,%g1
       stx     %fsr,[%g1]
       ldd     [%g1],%g2 
loaded:       
       fbule,pn   %fcc2, less_equal
       
       nop
       ba	greater
       nop
       
less_equal:
       set	lessequal_string,%o1
       ba	write_stdout
       nop

greater:
       set	greater_string,%o1
       
	#================================
	# WRITE_STDOUT
	#================================
	# %o1 has string

write_stdout:

	set	SYSCALL_WRITE,%g1	! Write syscall in %g1
	set	STDOUT,%o0		! 1 in %o0 (stdout)
	set	0,%o2			! 0 (count) in %o2

str_loop1:
	ldub	[%o1+%o2],%l0		! load byte
	cmp	%l0,%g0			! compare against zero
	bnz	str_loop1		! if not nul, repeat
	# BRANCH DELAY SLOT
	inc	%o2			! increment count

	dec	%o2			! correct count	
	ta	0x10			! run the syscall

exit:		
        mov	0,%o0			! exit value
        mov	SYSCALL_EXIT,%g1        ! put the exit syscall number in g1
        ta      0x10			! and exit




!===========================================================================
.data
!===========================================================================

data_region:		
float1: .double 0.025132741
float2: .double 0.0
float3:	.double 0.0

greater_string:		.ascii  "Greater\n\0"
lessequal_string:	.ascii  "Less Equal\n\0"

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