Hello

on SPARC v9 the floating point status register (fsr) was extended 
to 64-bits, and 3 additional condtion codes were added in the upper 
32-bits (fcc1-fcc3).

The current qemu code doesn't handle this properly, using 32-bit shifts to 
access the condition codes which doesn't work unless you are only using 
fcc0.

Attached is code that shows the problem.

I've attempted to fix this myself but I am having trouble trying to get 
the gen_mov_reg_FCC0() and gen_mov_reg_FCC1() functions in 
target-sparc/translate.c to use 64-bit shifts.

In addition the floating point compare instructions need to be fixed.
Below is my attempt to make them work properly.

Vince


--- op_helper.c.orig	2008-08-28 17:25:22.000000000 -0400
+++ op_helper.c	2008-08-28 17:27:42.000000000 -0400
@@ -746,10 +746,10 @@
      {                                                                   \
          target_ulong new_fsr;                                           \
                                                                          \
-        env->fsr &= ~((FSR_FCC1 | FSR_FCC0) << FS);                     \
+        env->fsr &= ~((target_ulong) (FSR_FCC1 | FSR_FCC0) << FS);      \
          switch (glue(size, _compare) (reg1, reg2, &env->fp_status)) {   \
          case float_relation_unordered:                                  \
-            new_fsr = (FSR_FCC1 | FSR_FCC0) << FS;                      \
+            new_fsr = (target_ulong)(FSR_FCC1 | FSR_FCC0) << FS;        \
              if ((env->fsr & FSR_NVM) || TRAP) {                         \
                  env->fsr |= new_fsr;                                    \
                  env->fsr |= FSR_NVC;                                    \
@@ -760,10 +760,10 @@
              }                                                           \
              break;                                                      \
          case float_relation_less:                                       \
-            new_fsr = FSR_FCC0 << FS;                                   \
+            new_fsr = (target_ulong)FSR_FCC0 << FS;                     \
              break;                                                      \
          case float_relation_greater:                                    \
-            new_fsr = FSR_FCC1 << FS;                                   \
+	   new_fsr = (target_ulong)FSR_FCC1 << FS;                      \
              break;                                                      \
          default:                                                        \
              new_fsr = 0;                                                \