From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1KZABp-0005P8-Th for qemu-devel@nongnu.org; Fri, 29 Aug 2008 16:03:26 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1KZABm-0005Mo-DG for qemu-devel@nongnu.org; Fri, 29 Aug 2008 16:03:24 -0400 Received: from [199.232.76.173] (port=52001 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1KZABl-0005MP-Ns for qemu-devel@nongnu.org; Fri, 29 Aug 2008 16:03:22 -0400 Received: from csl.cornell.edu ([128.84.224.10]:2321 helo=vlsi.csl.cornell.edu) by monty-python.gnu.org with esmtp (Exim 4.60) (envelope-from ) id 1KZABk-0000vS-LR for qemu-devel@nongnu.org; Fri, 29 Aug 2008 16:03:20 -0400 Received: from stanley.csl.cornell.edu (stanley.csl.cornell.edu [128.84.224.15]) by vlsi.csl.cornell.edu (8.13.4/8.13.4) with ESMTP id m7TK3F9C083332 for ; Fri, 29 Aug 2008 16:03:20 -0400 (EDT) Date: Fri, 29 Aug 2008 16:03:15 -0400 (EDT) From: Vince Weaver Subject: Re: [Qemu-devel] sparc 64-bit fsr problem In-Reply-To: <20080828172114.V64752@stanley.csl.cornell.edu> Message-ID: <20080829160107.N71741@stanley.csl.cornell.edu> References: <20080828172114.V64752@stanley.csl.cornell.edu> MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII; format=flowed Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org > I've attempted to fix this myself but I am having trouble trying to get the > gen_mov_reg_FCC0() and gen_mov_reg_FCC1() functions in > target-sparc/translate.c to use 64-bit shifts. I've managed to get things working, at least enough to run equake from the spec2k benchmarks. The patch is below. Vince --- op_helper.c.orig 2008-08-28 17:25:22.000000000 -0400 +++ op_helper.c 2008-08-28 17:27:42.000000000 -0400 @@ -746,10 +746,10 @@ { \ target_ulong new_fsr; \ \ - env->fsr &= ~((FSR_FCC1 | FSR_FCC0) << FS); \ + env->fsr &= ~((target_ulong) (FSR_FCC1 | FSR_FCC0) << FS); \ switch (glue(size, _compare) (reg1, reg2, &env->fp_status)) { \ case float_relation_unordered: \ - new_fsr = (FSR_FCC1 | FSR_FCC0) << FS; \ + new_fsr = (target_ulong)(FSR_FCC1 | FSR_FCC0) << FS; \ if ((env->fsr & FSR_NVM) || TRAP) { \ env->fsr |= new_fsr; \ env->fsr |= FSR_NVC; \ @@ -760,10 +760,10 @@ } \ break; \ case float_relation_less: \ - new_fsr = FSR_FCC0 << FS; \ + new_fsr = (target_ulong)FSR_FCC0 << FS; \ break; \ case float_relation_greater: \ - new_fsr = FSR_FCC1 << FS; \ + new_fsr = (target_ulong)FSR_FCC1 << FS; \ break; \ default: \ new_fsr = 0; \ --- translate.c.orig 2008-08-29 15:59:15.000000000 -0400 +++ translate.c 2008-08-29 15:59:57.000000000 -0400 @@ -999,7 +999,7 @@ static inline void gen_mov_reg_FCC0(TCGv reg, TCGv src, unsigned int fcc_offset) { - tcg_gen_extu_i32_tl(reg, src); + tcg_gen_mov_tl(reg, src); tcg_gen_shri_tl(reg, reg, FSR_FCC0_SHIFT + fcc_offset); tcg_gen_andi_tl(reg, reg, 0x1); } @@ -1007,7 +1007,7 @@ static inline void gen_mov_reg_FCC1(TCGv reg, TCGv src, unsigned int fcc_offset) { - tcg_gen_extu_i32_tl(reg, src); + tcg_gen_mov_tl(reg, src); tcg_gen_shri_tl(reg, reg, FSR_FCC1_SHIFT + fcc_offset); tcg_gen_andi_tl(reg, reg, 0x1); }