* [Qemu-devel] sparc 64-bit fsr problem
@ 2008-08-28 21:32 Vince Weaver
2008-08-29 20:03 ` Vince Weaver
0 siblings, 1 reply; 3+ messages in thread
From: Vince Weaver @ 2008-08-28 21:32 UTC (permalink / raw)
To: qemu-devel
[-- Attachment #1: Type: TEXT/PLAIN, Size: 2634 bytes --]
Hello
on SPARC v9 the floating point status register (fsr) was extended
to 64-bits, and 3 additional condtion codes were added in the upper
32-bits (fcc1-fcc3).
The current qemu code doesn't handle this properly, using 32-bit shifts to
access the condition codes which doesn't work unless you are only using
fcc0.
Attached is code that shows the problem.
I've attempted to fix this myself but I am having trouble trying to get
the gen_mov_reg_FCC0() and gen_mov_reg_FCC1() functions in
target-sparc/translate.c to use 64-bit shifts.
In addition the floating point compare instructions need to be fixed.
Below is my attempt to make them work properly.
Vince
--- op_helper.c.orig 2008-08-28 17:25:22.000000000 -0400
+++ op_helper.c 2008-08-28 17:27:42.000000000 -0400
@@ -746,10 +746,10 @@
{ \
target_ulong new_fsr; \
\
- env->fsr &= ~((FSR_FCC1 | FSR_FCC0) << FS); \
+ env->fsr &= ~((target_ulong) (FSR_FCC1 | FSR_FCC0) << FS); \
switch (glue(size, _compare) (reg1, reg2, &env->fp_status)) { \
case float_relation_unordered: \
- new_fsr = (FSR_FCC1 | FSR_FCC0) << FS; \
+ new_fsr = (target_ulong)(FSR_FCC1 | FSR_FCC0) << FS; \
if ((env->fsr & FSR_NVM) || TRAP) { \
env->fsr |= new_fsr; \
env->fsr |= FSR_NVC; \
@@ -760,10 +760,10 @@
} \
break; \
case float_relation_less: \
- new_fsr = FSR_FCC0 << FS; \
+ new_fsr = (target_ulong)FSR_FCC0 << FS; \
break; \
case float_relation_greater: \
- new_fsr = FSR_FCC1 << FS; \
+ new_fsr = (target_ulong)FSR_FCC1 << FS; \
break; \
default: \
new_fsr = 0; \
[-- Attachment #2: Type: TEXT/PLAIN, Size: 1746 bytes --]
! Compile with:
! as -Av8plus -o fcc2_test.o fcc2_test.s ; ld -o fcc2_test fcc2_test.o
! + Syscalls have number in %g1, options in %o0,%o1,...
! Result returned in %o0
! Linux syscall is called by "ta 0x10"
.equ SYSCALL_EXIT,1
.equ SYSCALL_WRITE,4
.equ STDOUT,1
.globl _start
_start:
set float1,%g1
ldd [%g1],%f6
set float2,%g1
ldd [%g1],%f8
fcmped %fcc2, %f6, %f8
set float3,%g1
stx %fsr,[%g1]
ldd [%g1],%g2
loaded:
fbule,pn %fcc2, less_equal
nop
ba greater
nop
less_equal:
set lessequal_string,%o1
ba write_stdout
nop
greater:
set greater_string,%o1
#================================
# WRITE_STDOUT
#================================
# %o1 has string
write_stdout:
set SYSCALL_WRITE,%g1 ! Write syscall in %g1
set STDOUT,%o0 ! 1 in %o0 (stdout)
set 0,%o2 ! 0 (count) in %o2
str_loop1:
ldub [%o1+%o2],%l0 ! load byte
cmp %l0,%g0 ! compare against zero
bnz str_loop1 ! if not nul, repeat
# BRANCH DELAY SLOT
inc %o2 ! increment count
dec %o2 ! correct count
ta 0x10 ! run the syscall
exit:
mov 0,%o0 ! exit value
mov SYSCALL_EXIT,%g1 ! put the exit syscall number in g1
ta 0x10 ! and exit
!===========================================================================
.data
!===========================================================================
data_region:
float1: .double 0.025132741
float2: .double 0.0
float3: .double 0.0
greater_string: .ascii "Greater\n\0"
lessequal_string: .ascii "Less Equal\n\0"
[-- Attachment #3: Type: APPLICATION/octet-stream, Size: 1109 bytes --]
^ permalink raw reply [flat|nested] 3+ messages in thread* Re: [Qemu-devel] sparc 64-bit fsr problem
2008-08-28 21:32 [Qemu-devel] sparc 64-bit fsr problem Vince Weaver
@ 2008-08-29 20:03 ` Vince Weaver
2008-08-29 20:31 ` Blue Swirl
0 siblings, 1 reply; 3+ messages in thread
From: Vince Weaver @ 2008-08-29 20:03 UTC (permalink / raw)
To: qemu-devel
> I've attempted to fix this myself but I am having trouble trying to get the
> gen_mov_reg_FCC0() and gen_mov_reg_FCC1() functions in
> target-sparc/translate.c to use 64-bit shifts.
I've managed to get things working, at least enough to run equake from the
spec2k benchmarks. The patch is below.
Vince
--- op_helper.c.orig 2008-08-28 17:25:22.000000000 -0400
+++ op_helper.c 2008-08-28 17:27:42.000000000 -0400
@@ -746,10 +746,10 @@
{ \
target_ulong new_fsr; \
\
- env->fsr &= ~((FSR_FCC1 | FSR_FCC0) << FS); \
+ env->fsr &= ~((target_ulong) (FSR_FCC1 | FSR_FCC0) << FS); \
switch (glue(size, _compare) (reg1, reg2, &env->fp_status)) { \
case float_relation_unordered: \
- new_fsr = (FSR_FCC1 | FSR_FCC0) << FS; \
+ new_fsr = (target_ulong)(FSR_FCC1 | FSR_FCC0) << FS; \
if ((env->fsr & FSR_NVM) || TRAP) { \
env->fsr |= new_fsr; \
env->fsr |= FSR_NVC; \
@@ -760,10 +760,10 @@
} \
break; \
case float_relation_less: \
- new_fsr = FSR_FCC0 << FS; \
+ new_fsr = (target_ulong)FSR_FCC0 << FS; \
break; \
case float_relation_greater: \
- new_fsr = FSR_FCC1 << FS; \
+ new_fsr = (target_ulong)FSR_FCC1 << FS; \
break; \
default: \
new_fsr = 0; \
--- translate.c.orig 2008-08-29 15:59:15.000000000 -0400
+++ translate.c 2008-08-29 15:59:57.000000000 -0400
@@ -999,7 +999,7 @@
static inline void gen_mov_reg_FCC0(TCGv reg, TCGv src,
unsigned int fcc_offset)
{
- tcg_gen_extu_i32_tl(reg, src);
+ tcg_gen_mov_tl(reg, src);
tcg_gen_shri_tl(reg, reg, FSR_FCC0_SHIFT + fcc_offset);
tcg_gen_andi_tl(reg, reg, 0x1);
}
@@ -1007,7 +1007,7 @@
static inline void gen_mov_reg_FCC1(TCGv reg, TCGv src,
unsigned int fcc_offset)
{
- tcg_gen_extu_i32_tl(reg, src);
+ tcg_gen_mov_tl(reg, src);
tcg_gen_shri_tl(reg, reg, FSR_FCC1_SHIFT + fcc_offset);
tcg_gen_andi_tl(reg, reg, 0x1);
}
^ permalink raw reply [flat|nested] 3+ messages in thread* Re: [Qemu-devel] sparc 64-bit fsr problem
2008-08-29 20:03 ` Vince Weaver
@ 2008-08-29 20:31 ` Blue Swirl
0 siblings, 0 replies; 3+ messages in thread
From: Blue Swirl @ 2008-08-29 20:31 UTC (permalink / raw)
To: qemu-devel
On 8/29/08, Vince Weaver <vince@csl.cornell.edu> wrote:
>
>
> > I've attempted to fix this myself but I am having trouble trying to get
> the gen_mov_reg_FCC0() and gen_mov_reg_FCC1() functions in
> target-sparc/translate.c to use 64-bit shifts.
I think the fsr bit definitions in cpu.h need to be changed from 1<<x
to 1ULL << x, then the (target_ulong) cast should not be needed
anymore.
> I've managed to get things working, at least enough to run equake from the
> spec2k benchmarks. The patch is below.
Thanks for the debugging by the way!
>
>
> Vince
>
> --- op_helper.c.orig 2008-08-28 17:25:22.000000000 -0400
> +++ op_helper.c 2008-08-28 17:27:42.000000000 -0400
> @@ -746,10 +746,10 @@
> { \
> target_ulong new_fsr; \
> \
> - env->fsr &= ~((FSR_FCC1 | FSR_FCC0) << FS); \
> + env->fsr &= ~((target_ulong) (FSR_FCC1 | FSR_FCC0) << FS); \
> switch (glue(size, _compare) (reg1, reg2, &env->fp_status)) { \
> case float_relation_unordered: \
> - new_fsr = (FSR_FCC1 | FSR_FCC0) << FS; \
> + new_fsr = (target_ulong)(FSR_FCC1 | FSR_FCC0) << FS; \
> if ((env->fsr & FSR_NVM) || TRAP) { \
> env->fsr |= new_fsr; \
> env->fsr |= FSR_NVC; \
> @@ -760,10 +760,10 @@
> } \
> break; \
> case float_relation_less: \
> - new_fsr = FSR_FCC0 << FS; \
> + new_fsr = (target_ulong)FSR_FCC0 << FS; \
> break; \
> case float_relation_greater: \
> - new_fsr = FSR_FCC1 << FS; \
> + new_fsr = (target_ulong)FSR_FCC1 << FS; \
> break; \
> default: \
> new_fsr = 0; \
> --- translate.c.orig 2008-08-29 15:59:15.000000000 -0400
> +++ translate.c 2008-08-29 15:59:57.000000000 -0400
> @@ -999,7 +999,7 @@
> static inline void gen_mov_reg_FCC0(TCGv reg, TCGv src,
> unsigned int fcc_offset)
> {
> - tcg_gen_extu_i32_tl(reg, src);
> + tcg_gen_mov_tl(reg, src);
> tcg_gen_shri_tl(reg, reg, FSR_FCC0_SHIFT + fcc_offset);
Drop the mov and:
tcg_gen_shri_tl(reg, src FSR_FCC0_SHIFT + fcc_offset);
> tcg_gen_andi_tl(reg, reg, 0x1);
> }
> @@ -1007,7 +1007,7 @@
> static inline void gen_mov_reg_FCC1(TCGv reg, TCGv src,
> unsigned int fcc_offset)
> {
> - tcg_gen_extu_i32_tl(reg, src);
> + tcg_gen_mov_tl(reg, src);
> tcg_gen_shri_tl(reg, reg, FSR_FCC1_SHIFT + fcc_offset);
Same here.
> tcg_gen_andi_tl(reg, reg, 0x1);
> }
^ permalink raw reply [flat|nested] 3+ messages in thread
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2008-08-28 21:32 [Qemu-devel] sparc 64-bit fsr problem Vince Weaver
2008-08-29 20:03 ` Vince Weaver
2008-08-29 20:31 ` Blue Swirl
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