* [Qemu-devel] [PATCH] [ppc] Convert gen_set_{T0,T1} to TCG
@ 2008-09-02 13:36 Andreas Färber
2008-09-02 14:32 ` [Qemu-devel] [PATCH] [ppc] Convert op_reset_T0, op_set_{T0, T1} " Andreas Färber
2008-09-02 16:18 ` [Qemu-devel] [PATCH] [ppc] Convert gen_set_{T0,T1} " Aurelien Jarno
0 siblings, 2 replies; 42+ messages in thread
From: Andreas Färber @ 2008-09-02 13:36 UTC (permalink / raw)
To: qemu-devel
[-- Attachment #1: Type: text/plain, Size: 4306 bytes --]
Hello,
The attached patch replaces gen_set_T0 and gen_set_T1 with
tcg_gen_movi_tl.
Signed-off-by: Andreas Faerber <andreas.faerber@web.de>
It compiles, boots Rob's PReP kernel and runs linux-user-test-0.3's
ls, on Linux/amd64. Any further instructions to test?
Andreas
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index bde538a..205993a 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -80,26 +80,6 @@ static uint16_t *gen_fprf_buf[OPC_BUF_SIZE];
static uint16_t **gen_fprf_ptr;
#endif
-static always_inline void gen_set_T0 (target_ulong val)
-{
-#if defined(TARGET_PPC64)
- if (val >> 32)
- gen_op_set_T0_64(val >> 32, val);
- else
-#endif
- gen_op_set_T0(val);
-}
-
-static always_inline void gen_set_T1 (target_ulong val)
-{
-#if defined(TARGET_PPC64)
- if (val >> 32)
- gen_op_set_T1_64(val >> 32, val);
- else
-#endif
- gen_op_set_T1(val);
-}
-
#define GEN8(func,
NAME) \
static GenOpFunc *NAME ## _table [8] =
{ \
NAME ## 0, NAME ## 1, NAME ## 2, NAME ##
3, \
@@ -1004,7 +984,7 @@ GEN_HANDLER(addi, 0x0E, 0xFF, 0xFF, 0x00000000,
PPC_INTEGER)
if (rA(ctx->opcode) == 0) {
/* li case */
- gen_set_T0(simm);
+ tcg_gen_movi_tl(cpu_T[0], simm);
} else {
gen_op_load_gpr_T0(rA(ctx->opcode));
if (likely(simm != 0))
@@ -1060,7 +1040,7 @@ GEN_HANDLER(addis, 0x0F, 0xFF, 0xFF, 0x00000000,
PPC_INTEGER)
if (rA(ctx->opcode) == 0) {
/* lis case */
- gen_set_T0(simm << 16);
+ tcg_gen_movi_tl(cpu_T[0], simm << 16);
} else {
gen_op_load_gpr_T0(rA(ctx->opcode));
if (likely(simm != 0))
@@ -1161,7 +1141,7 @@ GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001,
PPC_ISEL)
uint32_t mask;
if (rA(ctx->opcode) == 0) {
- gen_set_T0(0);
+ tcg_gen_movi_tl(cpu_T[0], 0);
} else {
gen_op_load_gpr_T1(rA(ctx->opcode));
}
@@ -2100,7 +2080,7 @@ static always_inline void gen_addr_imm_index
(DisasContext *ctx,
simm &= ~maskl;
if (rA(ctx->opcode) == 0) {
- gen_set_T0(simm);
+ tcg_gen_movi_tl(cpu_T[0], simm);
} else {
gen_op_load_gpr_T0(rA(ctx->opcode));
if (likely(simm != 0))
@@ -2823,7 +2803,7 @@ static always_inline void gen_goto_tb
(DisasContext *ctx, int n,
if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK) &&
likely(!ctx->singlestep_enabled)) {
tcg_gen_goto_tb(n);
- gen_set_T1(dest);
+ tcg_gen_movi_tl(cpu_T[1], dest);
#if defined(TARGET_PPC64)
if (ctx->sf_mode)
gen_op_b_T1_64();
@@ -2832,7 +2812,7 @@ static always_inline void gen_goto_tb
(DisasContext *ctx, int n,
gen_op_b_T1();
tcg_gen_exit_tb((long)tb + n);
} else {
- gen_set_T1(dest);
+ tcg_gen_movi_tl(cpu_T[1], dest);
#if defined(TARGET_PPC64)
if (ctx->sf_mode)
gen_op_b_T1_64();
@@ -3185,7 +3165,7 @@ GEN_HANDLER(tw, 0x1F, 0x04, 0x00, 0x00000001,
PPC_FLOW)
GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW)
{
gen_op_load_gpr_T0(rA(ctx->opcode));
- gen_set_T1(SIMM(ctx->opcode));
+ tcg_gen_movi_tl(cpu_T[1], SIMM(ctx->opcode));
/* Update the nip since this might generate a trap exception */
gen_update_nip(ctx, ctx->nip);
gen_op_tw(TO(ctx->opcode));
@@ -3206,7 +3186,7 @@ GEN_HANDLER(td, 0x1F, 0x04, 0x02, 0x00000001,
PPC_64B)
GEN_HANDLER(tdi, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B)
{
gen_op_load_gpr_T0(rA(ctx->opcode));
- gen_set_T1(SIMM(ctx->opcode));
+ tcg_gen_movi_tl(cpu_T[1], SIMM(ctx->opcode));
/* Update the nip since this might generate a trap exception */
gen_update_nip(ctx, ctx->nip);
gen_op_td(TO(ctx->opcode));
@@ -5335,7 +5315,7 @@ static always_inline void gen_addr_spe_imm_index
(DisasContext *ctx, int sh)
target_long simm = rB(ctx->opcode);
if (rA(ctx->opcode) == 0) {
- gen_set_T0(simm << sh);
+ tcg_gen_movi_tl(cpu_T[0], simm << sh);
} else {
gen_op_load_gpr_T0(rA(ctx->opcode));
if (likely(simm != 0))
[-- Attachment #2: 0001-Convert-gen_set_-T0-T1-to-TCG.patch --]
[-- Type: application/octet-stream, Size: 4439 bytes --]
From 8a879429f02673de0c72be2b62a23aa847a77a47 Mon Sep 17 00:00:00 2001
From: =?utf-8?q?Andreas=20F=C3=A4rber?= <andreas.faerber@web.de>
Date: Tue, 2 Sep 2008 15:02:07 +0200
Subject: [PATCH] Convert gen_set_{T0,T1} to TCG
---
target-ppc/translate.c | 38 +++++++++-----------------------------
1 files changed, 9 insertions(+), 29 deletions(-)
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index bde538a..205993a 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -80,26 +80,6 @@ static uint16_t *gen_fprf_buf[OPC_BUF_SIZE];
static uint16_t **gen_fprf_ptr;
#endif
-static always_inline void gen_set_T0 (target_ulong val)
-{
-#if defined(TARGET_PPC64)
- if (val >> 32)
- gen_op_set_T0_64(val >> 32, val);
- else
-#endif
- gen_op_set_T0(val);
-}
-
-static always_inline void gen_set_T1 (target_ulong val)
-{
-#if defined(TARGET_PPC64)
- if (val >> 32)
- gen_op_set_T1_64(val >> 32, val);
- else
-#endif
- gen_op_set_T1(val);
-}
-
#define GEN8(func, NAME) \
static GenOpFunc *NAME ## _table [8] = { \
NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3, \
@@ -1004,7 +984,7 @@ GEN_HANDLER(addi, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
if (rA(ctx->opcode) == 0) {
/* li case */
- gen_set_T0(simm);
+ tcg_gen_movi_tl(cpu_T[0], simm);
} else {
gen_op_load_gpr_T0(rA(ctx->opcode));
if (likely(simm != 0))
@@ -1060,7 +1040,7 @@ GEN_HANDLER(addis, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
if (rA(ctx->opcode) == 0) {
/* lis case */
- gen_set_T0(simm << 16);
+ tcg_gen_movi_tl(cpu_T[0], simm << 16);
} else {
gen_op_load_gpr_T0(rA(ctx->opcode));
if (likely(simm != 0))
@@ -1161,7 +1141,7 @@ GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL)
uint32_t mask;
if (rA(ctx->opcode) == 0) {
- gen_set_T0(0);
+ tcg_gen_movi_tl(cpu_T[0], 0);
} else {
gen_op_load_gpr_T1(rA(ctx->opcode));
}
@@ -2100,7 +2080,7 @@ static always_inline void gen_addr_imm_index (DisasContext *ctx,
simm &= ~maskl;
if (rA(ctx->opcode) == 0) {
- gen_set_T0(simm);
+ tcg_gen_movi_tl(cpu_T[0], simm);
} else {
gen_op_load_gpr_T0(rA(ctx->opcode));
if (likely(simm != 0))
@@ -2823,7 +2803,7 @@ static always_inline void gen_goto_tb (DisasContext *ctx, int n,
if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK) &&
likely(!ctx->singlestep_enabled)) {
tcg_gen_goto_tb(n);
- gen_set_T1(dest);
+ tcg_gen_movi_tl(cpu_T[1], dest);
#if defined(TARGET_PPC64)
if (ctx->sf_mode)
gen_op_b_T1_64();
@@ -2832,7 +2812,7 @@ static always_inline void gen_goto_tb (DisasContext *ctx, int n,
gen_op_b_T1();
tcg_gen_exit_tb((long)tb + n);
} else {
- gen_set_T1(dest);
+ tcg_gen_movi_tl(cpu_T[1], dest);
#if defined(TARGET_PPC64)
if (ctx->sf_mode)
gen_op_b_T1_64();
@@ -3185,7 +3165,7 @@ GEN_HANDLER(tw, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW)
GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW)
{
gen_op_load_gpr_T0(rA(ctx->opcode));
- gen_set_T1(SIMM(ctx->opcode));
+ tcg_gen_movi_tl(cpu_T[1], SIMM(ctx->opcode));
/* Update the nip since this might generate a trap exception */
gen_update_nip(ctx, ctx->nip);
gen_op_tw(TO(ctx->opcode));
@@ -3206,7 +3186,7 @@ GEN_HANDLER(td, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B)
GEN_HANDLER(tdi, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B)
{
gen_op_load_gpr_T0(rA(ctx->opcode));
- gen_set_T1(SIMM(ctx->opcode));
+ tcg_gen_movi_tl(cpu_T[1], SIMM(ctx->opcode));
/* Update the nip since this might generate a trap exception */
gen_update_nip(ctx, ctx->nip);
gen_op_td(TO(ctx->opcode));
@@ -5335,7 +5315,7 @@ static always_inline void gen_addr_spe_imm_index (DisasContext *ctx, int sh)
target_long simm = rB(ctx->opcode);
if (rA(ctx->opcode) == 0) {
- gen_set_T0(simm << sh);
+ tcg_gen_movi_tl(cpu_T[0], simm << sh);
} else {
gen_op_load_gpr_T0(rA(ctx->opcode));
if (likely(simm != 0))
--
1.5.5.1
[-- Attachment #3: Type: text/plain, Size: 1 bytes --]
^ permalink raw reply related [flat|nested] 42+ messages in thread* [Qemu-devel] [PATCH] [ppc] Convert op_reset_T0, op_set_{T0, T1} to TCG 2008-09-02 13:36 [Qemu-devel] [PATCH] [ppc] Convert gen_set_{T0,T1} to TCG Andreas Färber @ 2008-09-02 14:32 ` Andreas Färber 2008-09-02 15:39 ` [Qemu-devel] [PATCH] [ppc] Convert op_move_{T1,T2}_T0 " Andreas Färber 2008-09-02 15:58 ` [Qemu-devel] [PATCH] [ppc] Convert op_reset_T0, op_set_{T0, T1} " Aurelien Jarno 2008-09-02 16:18 ` [Qemu-devel] [PATCH] [ppc] Convert gen_set_{T0,T1} " Aurelien Jarno 1 sibling, 2 replies; 42+ messages in thread From: Andreas Färber @ 2008-09-02 14:32 UTC (permalink / raw) To: qemu-devel [-- Attachment #1: Type: text/plain, Size: 7097 bytes --] Hello, The attached patch replaces op_reset_T0, op_set_T0 and op_set_T1 with tcg_gen_movi_{tl,i32}. op_set_T0_64 and op_set_T1_64 were apparently unused, and op_set_T2 was already marked as unused. The patch removes them together with the converted ops. Signed-off-by: Andreas Faerber <andreas.faerber@web.de> Andreas diff --git a/target-ppc/op.c b/target-ppc/op.c index 972b8bc..022d424 100644 --- a/target-ppc/op.c +++ b/target-ppc/op.c @@ -137,48 +137,6 @@ void OPPROTO op_set_Rc0 (void) } /* Constants load */ -void OPPROTO op_reset_T0 (void) -{ - T0 = 0; - RETURN(); -} - -void OPPROTO op_set_T0 (void) -{ - T0 = (uint32_t)PARAM1; - RETURN(); -} - -#if defined(TARGET_PPC64) -void OPPROTO op_set_T0_64 (void) -{ - T0 = ((uint64_t)PARAM1 << 32) | (uint64_t)PARAM2; - RETURN(); -} -#endif - -void OPPROTO op_set_T1 (void) -{ - T1 = (uint32_t)PARAM1; - RETURN(); -} - -#if defined(TARGET_PPC64) -void OPPROTO op_set_T1_64 (void) -{ - T1 = ((uint64_t)PARAM1 << 32) | (uint64_t)PARAM2; - RETURN(); -} -#endif - -#if 0 // unused -void OPPROTO op_set_T2 (void) -{ - T2 = (uint32_t)PARAM1; - RETURN(); -} -#endif - void OPPROTO op_move_T1_T0 (void) { T1 = T0; diff --git a/target-ppc/translate.c b/target-ppc/translate.c index 205993a..2c83056 100644 --- a/target-ppc/translate.c +++ b/target-ppc/translate.c @@ -1292,7 +1292,7 @@ GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER) gen_op_load_gpr_T1(rB(ctx->opcode)); gen_op_xor(); } else { - gen_op_reset_T0(); + tcg_gen_movi_tl(cpu_T[0], 0); } gen_op_store_T0_gpr(rA(ctx->opcode)); if (unlikely(Rc(ctx->opcode) != 0)) @@ -2108,7 +2108,7 @@ static always_inline void gen_addr_reg_index (DisasContext *ctx) static always_inline void gen_addr_register (DisasContext *ctx) { if (rA(ctx->opcode) == 0) { - gen_op_reset_T0(); + tcg_gen_movi_tl(cpu_T[0], 0); } else { gen_op_load_gpr_T0(rA(ctx->opcode)); } @@ -2518,7 +2518,7 @@ GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING) /* NIP cannot be restored if the memory exception comes from an helper */ gen_update_nip(ctx, ctx->nip - 4); gen_addr_register(ctx); - gen_op_set_T1(nb); + tcg_gen_movi_i32(cpu_T[1], nb); op_ldsts(lswi, start); } @@ -2548,7 +2548,7 @@ GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING) gen_addr_register(ctx); if (nb == 0) nb = 32; - gen_op_set_T1(nb); + tcg_gen_movi_i32(cpu_T[1], nb); op_ldsts(stsw, rS(ctx->opcode)); } @@ -3612,7 +3612,7 @@ GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT) GEN_EXCP_PRIVREG(ctx); return; } - gen_op_set_T1(SR(ctx->opcode)); + tcg_gen_movi_i32(cpu_T[1], SR(ctx->opcode)); gen_op_load_sr(); gen_op_store_T0_gpr(rD(ctx->opcode)); #endif @@ -3646,7 +3646,7 @@ GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT) return; } gen_op_load_gpr_T0(rS(ctx->opcode)); - gen_op_set_T1(SR(ctx->opcode)); + tcg_gen_movi_i32(cpu_T[1], SR(ctx->opcode)); gen_op_store_sr(); #endif } @@ -3680,7 +3680,7 @@ GEN_HANDLER2(mfsr_64b, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B) GEN_EXCP_PRIVREG(ctx); return; } - gen_op_set_T1(SR(ctx->opcode)); + tcg_gen_movi_i32(cpu_T[1], SR(ctx->opcode)); gen_op_load_slb(); gen_op_store_T0_gpr(rD(ctx->opcode)); #endif @@ -3715,7 +3715,7 @@ GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B) return; } gen_op_load_gpr_T0(rS(ctx->opcode)); - gen_op_set_T1(SR(ctx->opcode)); + tcg_gen_movi_i32(cpu_T[1], SR(ctx->opcode)); gen_op_store_slb(); #endif } @@ -3952,7 +3952,7 @@ GEN_HANDLER(dozo, 0x1F, 0x08, 0x18, 0x00000000, PPC_POWER_BR) GEN_HANDLER(dozi, 0x09, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR) { gen_op_load_gpr_T0(rA(ctx->opcode)); - gen_op_set_T1(SIMM(ctx->opcode)); + tcg_gen_movi_i32(cpu_T[1], SIMM(ctx->opcode)); gen_op_POWER_doz(); gen_op_store_T0_gpr(rD(ctx->opcode)); } @@ -4117,7 +4117,7 @@ GEN_HANDLER(sleq, 0x1F, 0x19, 0x06, 0x00000000, PPC_POWER_BR) GEN_HANDLER(sliq, 0x1F, 0x18, 0x05, 0x00000000, PPC_POWER_BR) { gen_op_load_gpr_T0(rS(ctx->opcode)); - gen_op_set_T1(SH(ctx->opcode)); + tcg_gen_movi_i32(cpu_T[1], SH(ctx->opcode)); gen_op_POWER_sle(); gen_op_store_T0_gpr(rA(ctx->opcode)); if (unlikely(Rc(ctx->opcode) != 0)) @@ -4128,7 +4128,7 @@ GEN_HANDLER(sliq, 0x1F, 0x18, 0x05, 0x00000000, PPC_POWER_BR) GEN_HANDLER(slliq, 0x1F, 0x18, 0x07, 0x00000000, PPC_POWER_BR) { gen_op_load_gpr_T0(rS(ctx->opcode)); - gen_op_set_T1(SH(ctx->opcode)); + tcg_gen_movi_i32(cpu_T[1], SH(ctx->opcode)); gen_op_POWER_sleq(); gen_op_store_T0_gpr(rA(ctx->opcode)); if (unlikely(Rc(ctx->opcode) != 0)) @@ -4161,7 +4161,7 @@ GEN_HANDLER(slq, 0x1F, 0x18, 0x04, 0x00000000, PPC_POWER_BR) GEN_HANDLER(sraiq, 0x1F, 0x18, 0x1D, 0x00000000, PPC_POWER_BR) { gen_op_load_gpr_T0(rS(ctx->opcode)); - gen_op_set_T1(SH(ctx->opcode)); + tcg_gen_movi_i32(cpu_T[1], SH(ctx->opcode)); gen_op_POWER_sraq(); gen_op_store_T0_gpr(rA(ctx->opcode)); if (unlikely(Rc(ctx->opcode) != 0)) @@ -4216,7 +4216,7 @@ GEN_HANDLER(sreq, 0x1F, 0x19, 0x16, 0x00000000, PPC_POWER_BR) GEN_HANDLER(sriq, 0x1F, 0x18, 0x15, 0x00000000, PPC_POWER_BR) { gen_op_load_gpr_T0(rS(ctx->opcode)); - gen_op_set_T1(SH(ctx->opcode)); + tcg_gen_movi_i32(cpu_T[1], SH(ctx->opcode)); gen_op_POWER_srq(); gen_op_store_T0_gpr(rA(ctx->opcode)); if (unlikely(Rc(ctx->opcode) != 0)) @@ -4228,7 +4228,7 @@ GEN_HANDLER(srliq, 0x1F, 0x18, 0x17, 0x00000000, PPC_POWER_BR) { gen_op_load_gpr_T0(rS(ctx->opcode)); gen_op_load_gpr_T1(rB(ctx->opcode)); - gen_op_set_T1(SH(ctx->opcode)); + tcg_gen_movi_i32(cpu_T[1], SH(ctx->opcode)); gen_op_POWER_srlq(); gen_op_store_T0_gpr(rA(ctx->opcode)); if (unlikely(Rc(ctx->opcode) != 0)) @@ -4776,7 +4776,7 @@ GEN_HANDLER(mfdcr, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR) GEN_EXCP_PRIVREG(ctx); return; } - gen_op_set_T0(dcrn); + tcg_gen_movi_i32(cpu_T[0], dcrn); gen_op_load_dcr(); gen_op_store_T0_gpr(rD(ctx->opcode)); #endif @@ -4794,7 +4794,7 @@ GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR) GEN_EXCP_PRIVREG(ctx); return; } - gen_op_set_T0(dcrn); + tcg_gen_movi_i32(cpu_T[0], dcrn); gen_op_load_gpr_T1(rS(ctx->opcode)); gen_op_store_dcr(); #endif @@ -5158,7 +5158,7 @@ GEN_HANDLER(wrteei, 0x1F, 0x03, 0x05, 0x000EFC01, PPC_WRTEE) GEN_EXCP_PRIVOPC(ctx); return; } - gen_op_set_T0(ctx->opcode & 0x00010000); + tcg_gen_movi_i32(cpu_T[0], ctx->opcode & 0x00010000); gen_op_wrte(); /* Stop translation to have a chance to raise an exception * if we just set msr_ee to 1 [-- Attachment #2: op_reset-set.diff --] [-- Type: application/octet-stream, Size: 6627 bytes --] diff --git a/target-ppc/op.c b/target-ppc/op.c index 972b8bc..022d424 100644 --- a/target-ppc/op.c +++ b/target-ppc/op.c @@ -137,48 +137,6 @@ void OPPROTO op_set_Rc0 (void) } /* Constants load */ -void OPPROTO op_reset_T0 (void) -{ - T0 = 0; - RETURN(); -} - -void OPPROTO op_set_T0 (void) -{ - T0 = (uint32_t)PARAM1; - RETURN(); -} - -#if defined(TARGET_PPC64) -void OPPROTO op_set_T0_64 (void) -{ - T0 = ((uint64_t)PARAM1 << 32) | (uint64_t)PARAM2; - RETURN(); -} -#endif - -void OPPROTO op_set_T1 (void) -{ - T1 = (uint32_t)PARAM1; - RETURN(); -} - -#if defined(TARGET_PPC64) -void OPPROTO op_set_T1_64 (void) -{ - T1 = ((uint64_t)PARAM1 << 32) | (uint64_t)PARAM2; - RETURN(); -} -#endif - -#if 0 // unused -void OPPROTO op_set_T2 (void) -{ - T2 = (uint32_t)PARAM1; - RETURN(); -} -#endif - void OPPROTO op_move_T1_T0 (void) { T1 = T0; diff --git a/target-ppc/translate.c b/target-ppc/translate.c index 205993a..2c83056 100644 --- a/target-ppc/translate.c +++ b/target-ppc/translate.c @@ -1292,7 +1292,7 @@ GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER) gen_op_load_gpr_T1(rB(ctx->opcode)); gen_op_xor(); } else { - gen_op_reset_T0(); + tcg_gen_movi_tl(cpu_T[0], 0); } gen_op_store_T0_gpr(rA(ctx->opcode)); if (unlikely(Rc(ctx->opcode) != 0)) @@ -2108,7 +2108,7 @@ static always_inline void gen_addr_reg_index (DisasContext *ctx) static always_inline void gen_addr_register (DisasContext *ctx) { if (rA(ctx->opcode) == 0) { - gen_op_reset_T0(); + tcg_gen_movi_tl(cpu_T[0], 0); } else { gen_op_load_gpr_T0(rA(ctx->opcode)); } @@ -2518,7 +2518,7 @@ GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING) /* NIP cannot be restored if the memory exception comes from an helper */ gen_update_nip(ctx, ctx->nip - 4); gen_addr_register(ctx); - gen_op_set_T1(nb); + tcg_gen_movi_i32(cpu_T[1], nb); op_ldsts(lswi, start); } @@ -2548,7 +2548,7 @@ GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING) gen_addr_register(ctx); if (nb == 0) nb = 32; - gen_op_set_T1(nb); + tcg_gen_movi_i32(cpu_T[1], nb); op_ldsts(stsw, rS(ctx->opcode)); } @@ -3612,7 +3612,7 @@ GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT) GEN_EXCP_PRIVREG(ctx); return; } - gen_op_set_T1(SR(ctx->opcode)); + tcg_gen_movi_i32(cpu_T[1], SR(ctx->opcode)); gen_op_load_sr(); gen_op_store_T0_gpr(rD(ctx->opcode)); #endif @@ -3646,7 +3646,7 @@ GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT) return; } gen_op_load_gpr_T0(rS(ctx->opcode)); - gen_op_set_T1(SR(ctx->opcode)); + tcg_gen_movi_i32(cpu_T[1], SR(ctx->opcode)); gen_op_store_sr(); #endif } @@ -3680,7 +3680,7 @@ GEN_HANDLER2(mfsr_64b, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B) GEN_EXCP_PRIVREG(ctx); return; } - gen_op_set_T1(SR(ctx->opcode)); + tcg_gen_movi_i32(cpu_T[1], SR(ctx->opcode)); gen_op_load_slb(); gen_op_store_T0_gpr(rD(ctx->opcode)); #endif @@ -3715,7 +3715,7 @@ GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B) return; } gen_op_load_gpr_T0(rS(ctx->opcode)); - gen_op_set_T1(SR(ctx->opcode)); + tcg_gen_movi_i32(cpu_T[1], SR(ctx->opcode)); gen_op_store_slb(); #endif } @@ -3952,7 +3952,7 @@ GEN_HANDLER(dozo, 0x1F, 0x08, 0x18, 0x00000000, PPC_POWER_BR) GEN_HANDLER(dozi, 0x09, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR) { gen_op_load_gpr_T0(rA(ctx->opcode)); - gen_op_set_T1(SIMM(ctx->opcode)); + tcg_gen_movi_i32(cpu_T[1], SIMM(ctx->opcode)); gen_op_POWER_doz(); gen_op_store_T0_gpr(rD(ctx->opcode)); } @@ -4117,7 +4117,7 @@ GEN_HANDLER(sleq, 0x1F, 0x19, 0x06, 0x00000000, PPC_POWER_BR) GEN_HANDLER(sliq, 0x1F, 0x18, 0x05, 0x00000000, PPC_POWER_BR) { gen_op_load_gpr_T0(rS(ctx->opcode)); - gen_op_set_T1(SH(ctx->opcode)); + tcg_gen_movi_i32(cpu_T[1], SH(ctx->opcode)); gen_op_POWER_sle(); gen_op_store_T0_gpr(rA(ctx->opcode)); if (unlikely(Rc(ctx->opcode) != 0)) @@ -4128,7 +4128,7 @@ GEN_HANDLER(sliq, 0x1F, 0x18, 0x05, 0x00000000, PPC_POWER_BR) GEN_HANDLER(slliq, 0x1F, 0x18, 0x07, 0x00000000, PPC_POWER_BR) { gen_op_load_gpr_T0(rS(ctx->opcode)); - gen_op_set_T1(SH(ctx->opcode)); + tcg_gen_movi_i32(cpu_T[1], SH(ctx->opcode)); gen_op_POWER_sleq(); gen_op_store_T0_gpr(rA(ctx->opcode)); if (unlikely(Rc(ctx->opcode) != 0)) @@ -4161,7 +4161,7 @@ GEN_HANDLER(slq, 0x1F, 0x18, 0x04, 0x00000000, PPC_POWER_BR) GEN_HANDLER(sraiq, 0x1F, 0x18, 0x1D, 0x00000000, PPC_POWER_BR) { gen_op_load_gpr_T0(rS(ctx->opcode)); - gen_op_set_T1(SH(ctx->opcode)); + tcg_gen_movi_i32(cpu_T[1], SH(ctx->opcode)); gen_op_POWER_sraq(); gen_op_store_T0_gpr(rA(ctx->opcode)); if (unlikely(Rc(ctx->opcode) != 0)) @@ -4216,7 +4216,7 @@ GEN_HANDLER(sreq, 0x1F, 0x19, 0x16, 0x00000000, PPC_POWER_BR) GEN_HANDLER(sriq, 0x1F, 0x18, 0x15, 0x00000000, PPC_POWER_BR) { gen_op_load_gpr_T0(rS(ctx->opcode)); - gen_op_set_T1(SH(ctx->opcode)); + tcg_gen_movi_i32(cpu_T[1], SH(ctx->opcode)); gen_op_POWER_srq(); gen_op_store_T0_gpr(rA(ctx->opcode)); if (unlikely(Rc(ctx->opcode) != 0)) @@ -4228,7 +4228,7 @@ GEN_HANDLER(srliq, 0x1F, 0x18, 0x17, 0x00000000, PPC_POWER_BR) { gen_op_load_gpr_T0(rS(ctx->opcode)); gen_op_load_gpr_T1(rB(ctx->opcode)); - gen_op_set_T1(SH(ctx->opcode)); + tcg_gen_movi_i32(cpu_T[1], SH(ctx->opcode)); gen_op_POWER_srlq(); gen_op_store_T0_gpr(rA(ctx->opcode)); if (unlikely(Rc(ctx->opcode) != 0)) @@ -4776,7 +4776,7 @@ GEN_HANDLER(mfdcr, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR) GEN_EXCP_PRIVREG(ctx); return; } - gen_op_set_T0(dcrn); + tcg_gen_movi_i32(cpu_T[0], dcrn); gen_op_load_dcr(); gen_op_store_T0_gpr(rD(ctx->opcode)); #endif @@ -4794,7 +4794,7 @@ GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR) GEN_EXCP_PRIVREG(ctx); return; } - gen_op_set_T0(dcrn); + tcg_gen_movi_i32(cpu_T[0], dcrn); gen_op_load_gpr_T1(rS(ctx->opcode)); gen_op_store_dcr(); #endif @@ -5158,7 +5158,7 @@ GEN_HANDLER(wrteei, 0x1F, 0x03, 0x05, 0x000EFC01, PPC_WRTEE) GEN_EXCP_PRIVOPC(ctx); return; } - gen_op_set_T0(ctx->opcode & 0x00010000); + tcg_gen_movi_i32(cpu_T[0], ctx->opcode & 0x00010000); gen_op_wrte(); /* Stop translation to have a chance to raise an exception * if we just set msr_ee to 1 [-- Attachment #3: Type: text/plain, Size: 1 bytes --] ^ permalink raw reply related [flat|nested] 42+ messages in thread
* [Qemu-devel] [PATCH] [ppc] Convert op_move_{T1,T2}_T0 to TCG 2008-09-02 14:32 ` [Qemu-devel] [PATCH] [ppc] Convert op_reset_T0, op_set_{T0, T1} " Andreas Färber @ 2008-09-02 15:39 ` Andreas Färber 2008-09-02 16:19 ` Aurelien Jarno 2008-09-02 16:57 ` [Qemu-devel] [PATCH 4/x] [ppc] Convert op_moven_T2_T0 " Andreas Färber 2008-09-02 15:58 ` [Qemu-devel] [PATCH] [ppc] Convert op_reset_T0, op_set_{T0, T1} " Aurelien Jarno 1 sibling, 2 replies; 42+ messages in thread From: Andreas Färber @ 2008-09-02 15:39 UTC (permalink / raw) To: qemu-devel [-- Attachment #1: Type: text/plain, Size: 5861 bytes --] Hello, Attached patch replaces op_move_T1_T0 and op_move_T2_T0 with tcg_gen_mov_tl. Signed-off-by: Andreas Faerber <andreas.faerber@web.de> Andreas diff --git a/target-ppc/op.c b/target-ppc/op.c index 022d424..3ee326d 100644 --- a/target-ppc/op.c +++ b/target-ppc/op.c @@ -137,18 +137,6 @@ void OPPROTO op_set_Rc0 (void) } /* Constants load */ -void OPPROTO op_move_T1_T0 (void) -{ - T1 = T0; - RETURN(); -} - -void OPPROTO op_move_T2_T0 (void) -{ - T2 = T0; - RETURN(); -} - void OPPROTO op_moven_T2_T0 (void) { T2 = ~T0; diff --git a/target-ppc/translate.c b/target-ppc/translate.c index 2c83056..cf6d486 100644 --- a/target-ppc/translate.c +++ b/target-ppc/translate.c @@ -795,7 +795,7 @@ __GEN_INT_ARITH1_O_64(name##o, opc1, opc2, opc3 | 0x10, type) /* add add. addo addo. */ static always_inline void gen_op_addo (void) { - gen_op_move_T2_T0(); + tcg_gen_mov_tl(cpu_T[2], cpu_T[0]); gen_op_add(); gen_op_check_addo(); } @@ -803,7 +803,7 @@ static always_inline void gen_op_addo (void) #define gen_op_add_64 gen_op_add static always_inline void gen_op_addo_64 (void) { - gen_op_move_T2_T0(); + tcg_gen_mov_tl(cpu_T[2], cpu_T[0]); gen_op_add(); gen_op_check_addo_64(); } @@ -812,13 +812,13 @@ GEN_INT_ARITH2_64 (add, 0x1F, 0x0A, 0x08, PPC_INTEGER); /* addc addc. addco addco. */ static always_inline void gen_op_addc (void) { - gen_op_move_T2_T0(); + tcg_gen_mov_tl(cpu_T[2], cpu_T[0]); gen_op_add(); gen_op_check_addc(); } static always_inline void gen_op_addco (void) { - gen_op_move_T2_T0(); + tcg_gen_mov_tl(cpu_T[2], cpu_T[0]); gen_op_add(); gen_op_check_addc(); gen_op_check_addo(); @@ -826,13 +826,13 @@ static always_inline void gen_op_addco (void) #if defined(TARGET_PPC64) static always_inline void gen_op_addc_64 (void) { - gen_op_move_T2_T0(); + tcg_gen_mov_tl(cpu_T[2], cpu_T[0]); gen_op_add(); gen_op_check_addc_64(); } static always_inline void gen_op_addco_64 (void) { - gen_op_move_T2_T0(); + tcg_gen_mov_tl(cpu_T[2], cpu_T[0]); gen_op_add(); gen_op_check_addc_64(); gen_op_check_addo_64(); @@ -842,14 +842,14 @@ GEN_INT_ARITH2_64 (addc, 0x1F, 0x0A, 0x00, PPC_INTEGER); /* adde adde. addeo addeo. */ static always_inline void gen_op_addeo (void) { - gen_op_move_T2_T0(); + tcg_gen_mov_tl(cpu_T[2], cpu_T[0]); gen_op_adde(); gen_op_check_addo(); } #if defined(TARGET_PPC64) static always_inline void gen_op_addeo_64 (void) { - gen_op_move_T2_T0(); + tcg_gen_mov_tl(cpu_T[2], cpu_T[0]); gen_op_adde_64(); gen_op_check_addo_64(); } @@ -858,13 +858,13 @@ GEN_INT_ARITH2_64 (adde, 0x1F, 0x0A, 0x04, PPC_INTEGER); /* addme addme. addmeo addmeo. */ static always_inline void gen_op_addme (void) { - gen_op_move_T1_T0(); + tcg_gen_mov_tl(cpu_T[1], cpu_T[0]); gen_op_add_me(); } #if defined(TARGET_PPC64) static always_inline void gen_op_addme_64 (void) { - gen_op_move_T1_T0(); + tcg_gen_mov_tl(cpu_T[1], cpu_T[0]); gen_op_add_me_64(); } #endif @@ -872,13 +872,13 @@ GEN_INT_ARITH1_64 (addme, 0x1F, 0x0A, 0x07, PPC_INTEGER); /* addze addze. addzeo addzeo. */ static always_inline void gen_op_addze (void) { - gen_op_move_T2_T0(); + tcg_gen_mov_tl(cpu_T[2], cpu_T[0]); gen_op_add_ze(); gen_op_check_addc(); } static always_inline void gen_op_addzeo (void) { - gen_op_move_T2_T0(); + tcg_gen_mov_tl(cpu_T[2], cpu_T[0]); gen_op_add_ze(); gen_op_check_addc(); gen_op_check_addo(); @@ -886,13 +886,13 @@ static always_inline void gen_op_addzeo (void) #if defined(TARGET_PPC64) static always_inline void gen_op_addze_64 (void) { - gen_op_move_T2_T0(); + tcg_gen_mov_tl(cpu_T[2], cpu_T[0]); gen_op_add_ze(); gen_op_check_addc_64(); } static always_inline void gen_op_addzeo_64 (void) { - gen_op_move_T2_T0(); + tcg_gen_mov_tl(cpu_T[2], cpu_T[0]); gen_op_add_ze(); gen_op_check_addc_64(); gen_op_check_addo_64(); @@ -999,7 +999,7 @@ GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) gen_op_load_gpr_T0(rA(ctx->opcode)); if (likely(simm != 0)) { - gen_op_move_T2_T0(); + tcg_gen_mov_tl(cpu_T[2], cpu_T[0]); gen_op_addi(simm); #if defined(TARGET_PPC64) if (ctx->sf_mode) @@ -1019,7 +1019,7 @@ GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) gen_op_load_gpr_T0(rA(ctx->opcode)); if (likely(simm != 0)) { - gen_op_move_T2_T0(); + tcg_gen_mov_tl(cpu_T[2], cpu_T[0]); gen_op_addi(simm); #if defined(TARGET_PPC64) if (ctx->sf_mode) @@ -1661,7 +1661,7 @@ GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER) int mb, me; gen_op_load_gpr_T0(rS(ctx->opcode)); if (SH(ctx->opcode) != 0) { - gen_op_move_T1_T0(); + tcg_gen_mov_tl(cpu_T[1], cpu_T[0]); mb = 32 - SH(ctx->opcode); me = 31; #if defined(TARGET_PPC64) @@ -1691,7 +1691,7 @@ static always_inline void gen_sradi (DisasContext *ctx, int n) gen_op_load_gpr_T0(rS(ctx->opcode)); sh = SH(ctx->opcode) + (n << 5); if (sh != 0) { - gen_op_move_T1_T0(); + tcg_gen_mov_tl(cpu_T[1], cpu_T[0]); mb = 64 - SH(ctx->opcode); me = 63; mask = MASK(mb, me); @@ -4647,7 +4647,7 @@ static always_inline void gen_405_mulladd_insn (DisasContext *ctx, if (opc2 & 0x04) { /* (n)multiply-and-accumulate (0x0C - 0x0E) */ gen_op_load_gpr_T2(rt); - gen_op_move_T1_T0(); + tcg_gen_mov_tl(cpu_T[1], cpu_T[0]); gen_op_405_add_T0_T2(); } if (opc3 & 0x10) { [-- Attachment #2: op_move.diff --] [-- Type: application/octet-stream, Size: 5576 bytes --] diff --git a/target-ppc/op.c b/target-ppc/op.c index 022d424..3ee326d 100644 --- a/target-ppc/op.c +++ b/target-ppc/op.c @@ -137,18 +137,6 @@ void OPPROTO op_set_Rc0 (void) } /* Constants load */ -void OPPROTO op_move_T1_T0 (void) -{ - T1 = T0; - RETURN(); -} - -void OPPROTO op_move_T2_T0 (void) -{ - T2 = T0; - RETURN(); -} - void OPPROTO op_moven_T2_T0 (void) { T2 = ~T0; diff --git a/target-ppc/translate.c b/target-ppc/translate.c index 2c83056..cf6d486 100644 --- a/target-ppc/translate.c +++ b/target-ppc/translate.c @@ -795,7 +795,7 @@ __GEN_INT_ARITH1_O_64(name##o, opc1, opc2, opc3 | 0x10, type) /* add add. addo addo. */ static always_inline void gen_op_addo (void) { - gen_op_move_T2_T0(); + tcg_gen_mov_tl(cpu_T[2], cpu_T[0]); gen_op_add(); gen_op_check_addo(); } @@ -803,7 +803,7 @@ static always_inline void gen_op_addo (void) #define gen_op_add_64 gen_op_add static always_inline void gen_op_addo_64 (void) { - gen_op_move_T2_T0(); + tcg_gen_mov_tl(cpu_T[2], cpu_T[0]); gen_op_add(); gen_op_check_addo_64(); } @@ -812,13 +812,13 @@ GEN_INT_ARITH2_64 (add, 0x1F, 0x0A, 0x08, PPC_INTEGER); /* addc addc. addco addco. */ static always_inline void gen_op_addc (void) { - gen_op_move_T2_T0(); + tcg_gen_mov_tl(cpu_T[2], cpu_T[0]); gen_op_add(); gen_op_check_addc(); } static always_inline void gen_op_addco (void) { - gen_op_move_T2_T0(); + tcg_gen_mov_tl(cpu_T[2], cpu_T[0]); gen_op_add(); gen_op_check_addc(); gen_op_check_addo(); @@ -826,13 +826,13 @@ static always_inline void gen_op_addco (void) #if defined(TARGET_PPC64) static always_inline void gen_op_addc_64 (void) { - gen_op_move_T2_T0(); + tcg_gen_mov_tl(cpu_T[2], cpu_T[0]); gen_op_add(); gen_op_check_addc_64(); } static always_inline void gen_op_addco_64 (void) { - gen_op_move_T2_T0(); + tcg_gen_mov_tl(cpu_T[2], cpu_T[0]); gen_op_add(); gen_op_check_addc_64(); gen_op_check_addo_64(); @@ -842,14 +842,14 @@ GEN_INT_ARITH2_64 (addc, 0x1F, 0x0A, 0x00, PPC_INTEGER); /* adde adde. addeo addeo. */ static always_inline void gen_op_addeo (void) { - gen_op_move_T2_T0(); + tcg_gen_mov_tl(cpu_T[2], cpu_T[0]); gen_op_adde(); gen_op_check_addo(); } #if defined(TARGET_PPC64) static always_inline void gen_op_addeo_64 (void) { - gen_op_move_T2_T0(); + tcg_gen_mov_tl(cpu_T[2], cpu_T[0]); gen_op_adde_64(); gen_op_check_addo_64(); } @@ -858,13 +858,13 @@ GEN_INT_ARITH2_64 (adde, 0x1F, 0x0A, 0x04, PPC_INTEGER); /* addme addme. addmeo addmeo. */ static always_inline void gen_op_addme (void) { - gen_op_move_T1_T0(); + tcg_gen_mov_tl(cpu_T[1], cpu_T[0]); gen_op_add_me(); } #if defined(TARGET_PPC64) static always_inline void gen_op_addme_64 (void) { - gen_op_move_T1_T0(); + tcg_gen_mov_tl(cpu_T[1], cpu_T[0]); gen_op_add_me_64(); } #endif @@ -872,13 +872,13 @@ GEN_INT_ARITH1_64 (addme, 0x1F, 0x0A, 0x07, PPC_INTEGER); /* addze addze. addzeo addzeo. */ static always_inline void gen_op_addze (void) { - gen_op_move_T2_T0(); + tcg_gen_mov_tl(cpu_T[2], cpu_T[0]); gen_op_add_ze(); gen_op_check_addc(); } static always_inline void gen_op_addzeo (void) { - gen_op_move_T2_T0(); + tcg_gen_mov_tl(cpu_T[2], cpu_T[0]); gen_op_add_ze(); gen_op_check_addc(); gen_op_check_addo(); @@ -886,13 +886,13 @@ static always_inline void gen_op_addzeo (void) #if defined(TARGET_PPC64) static always_inline void gen_op_addze_64 (void) { - gen_op_move_T2_T0(); + tcg_gen_mov_tl(cpu_T[2], cpu_T[0]); gen_op_add_ze(); gen_op_check_addc_64(); } static always_inline void gen_op_addzeo_64 (void) { - gen_op_move_T2_T0(); + tcg_gen_mov_tl(cpu_T[2], cpu_T[0]); gen_op_add_ze(); gen_op_check_addc_64(); gen_op_check_addo_64(); @@ -999,7 +999,7 @@ GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) gen_op_load_gpr_T0(rA(ctx->opcode)); if (likely(simm != 0)) { - gen_op_move_T2_T0(); + tcg_gen_mov_tl(cpu_T[2], cpu_T[0]); gen_op_addi(simm); #if defined(TARGET_PPC64) if (ctx->sf_mode) @@ -1019,7 +1019,7 @@ GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) gen_op_load_gpr_T0(rA(ctx->opcode)); if (likely(simm != 0)) { - gen_op_move_T2_T0(); + tcg_gen_mov_tl(cpu_T[2], cpu_T[0]); gen_op_addi(simm); #if defined(TARGET_PPC64) if (ctx->sf_mode) @@ -1661,7 +1661,7 @@ GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER) int mb, me; gen_op_load_gpr_T0(rS(ctx->opcode)); if (SH(ctx->opcode) != 0) { - gen_op_move_T1_T0(); + tcg_gen_mov_tl(cpu_T[1], cpu_T[0]); mb = 32 - SH(ctx->opcode); me = 31; #if defined(TARGET_PPC64) @@ -1691,7 +1691,7 @@ static always_inline void gen_sradi (DisasContext *ctx, int n) gen_op_load_gpr_T0(rS(ctx->opcode)); sh = SH(ctx->opcode) + (n << 5); if (sh != 0) { - gen_op_move_T1_T0(); + tcg_gen_mov_tl(cpu_T[1], cpu_T[0]); mb = 64 - SH(ctx->opcode); me = 63; mask = MASK(mb, me); @@ -4647,7 +4647,7 @@ static always_inline void gen_405_mulladd_insn (DisasContext *ctx, if (opc2 & 0x04) { /* (n)multiply-and-accumulate (0x0C - 0x0E) */ gen_op_load_gpr_T2(rt); - gen_op_move_T1_T0(); + tcg_gen_mov_tl(cpu_T[1], cpu_T[0]); gen_op_405_add_T0_T2(); } if (opc3 & 0x10) { [-- Attachment #3: Type: text/plain, Size: 1 bytes --] ^ permalink raw reply related [flat|nested] 42+ messages in thread
* Re: [Qemu-devel] [PATCH] [ppc] Convert op_move_{T1,T2}_T0 to TCG 2008-09-02 15:39 ` [Qemu-devel] [PATCH] [ppc] Convert op_move_{T1,T2}_T0 " Andreas Färber @ 2008-09-02 16:19 ` Aurelien Jarno 2008-09-02 16:57 ` [Qemu-devel] [PATCH 4/x] [ppc] Convert op_moven_T2_T0 " Andreas Färber 1 sibling, 0 replies; 42+ messages in thread From: Aurelien Jarno @ 2008-09-02 16:19 UTC (permalink / raw) To: qemu-devel On Tue, Sep 02, 2008 at 05:39:17PM +0200, Andreas Färber wrote: > Hello, > > Attached patch replaces op_move_T1_T0 and op_move_T2_T0 with > tcg_gen_mov_tl. > > Signed-off-by: Andreas Faerber <andreas.faerber@web.de> > > Andreas Applied, thanks. > > > diff --git a/target-ppc/op.c b/target-ppc/op.c > index 022d424..3ee326d 100644 > --- a/target-ppc/op.c > +++ b/target-ppc/op.c > @@ -137,18 +137,6 @@ void OPPROTO op_set_Rc0 (void) > } > > /* Constants load */ > -void OPPROTO op_move_T1_T0 (void) > -{ > - T1 = T0; > - RETURN(); > -} > - > -void OPPROTO op_move_T2_T0 (void) > -{ > - T2 = T0; > - RETURN(); > -} > - > void OPPROTO op_moven_T2_T0 (void) > { > T2 = ~T0; > diff --git a/target-ppc/translate.c b/target-ppc/translate.c > index 2c83056..cf6d486 100644 > --- a/target-ppc/translate.c > +++ b/target-ppc/translate.c > @@ -795,7 +795,7 @@ __GEN_INT_ARITH1_O_64(name##o, opc1, opc2, opc3 | > 0x10, type) > /* add add. addo addo. */ > static always_inline void gen_op_addo (void) > { > - gen_op_move_T2_T0(); > + tcg_gen_mov_tl(cpu_T[2], cpu_T[0]); > gen_op_add(); > gen_op_check_addo(); > } > @@ -803,7 +803,7 @@ static always_inline void gen_op_addo (void) > #define gen_op_add_64 gen_op_add > static always_inline void gen_op_addo_64 (void) > { > - gen_op_move_T2_T0(); > + tcg_gen_mov_tl(cpu_T[2], cpu_T[0]); > gen_op_add(); > gen_op_check_addo_64(); > } > @@ -812,13 +812,13 @@ GEN_INT_ARITH2_64 (add, 0x1F, 0x0A, 0x08, > PPC_INTEGER); > /* addc addc. addco addco. */ > static always_inline void gen_op_addc (void) > { > - gen_op_move_T2_T0(); > + tcg_gen_mov_tl(cpu_T[2], cpu_T[0]); > gen_op_add(); > gen_op_check_addc(); > } > static always_inline void gen_op_addco (void) > { > - gen_op_move_T2_T0(); > + tcg_gen_mov_tl(cpu_T[2], cpu_T[0]); > gen_op_add(); > gen_op_check_addc(); > gen_op_check_addo(); > @@ -826,13 +826,13 @@ static always_inline void gen_op_addco (void) > #if defined(TARGET_PPC64) > static always_inline void gen_op_addc_64 (void) > { > - gen_op_move_T2_T0(); > + tcg_gen_mov_tl(cpu_T[2], cpu_T[0]); > gen_op_add(); > gen_op_check_addc_64(); > } > static always_inline void gen_op_addco_64 (void) > { > - gen_op_move_T2_T0(); > + tcg_gen_mov_tl(cpu_T[2], cpu_T[0]); > gen_op_add(); > gen_op_check_addc_64(); > gen_op_check_addo_64(); > @@ -842,14 +842,14 @@ GEN_INT_ARITH2_64 (addc, 0x1F, 0x0A, 0x00, > PPC_INTEGER); > /* adde adde. addeo addeo. */ > static always_inline void gen_op_addeo (void) > { > - gen_op_move_T2_T0(); > + tcg_gen_mov_tl(cpu_T[2], cpu_T[0]); > gen_op_adde(); > gen_op_check_addo(); > } > #if defined(TARGET_PPC64) > static always_inline void gen_op_addeo_64 (void) > { > - gen_op_move_T2_T0(); > + tcg_gen_mov_tl(cpu_T[2], cpu_T[0]); > gen_op_adde_64(); > gen_op_check_addo_64(); > } > @@ -858,13 +858,13 @@ GEN_INT_ARITH2_64 (adde, 0x1F, 0x0A, 0x04, > PPC_INTEGER); > /* addme addme. addmeo addmeo. */ > static always_inline void gen_op_addme (void) > { > - gen_op_move_T1_T0(); > + tcg_gen_mov_tl(cpu_T[1], cpu_T[0]); > gen_op_add_me(); > } > #if defined(TARGET_PPC64) > static always_inline void gen_op_addme_64 (void) > { > - gen_op_move_T1_T0(); > + tcg_gen_mov_tl(cpu_T[1], cpu_T[0]); > gen_op_add_me_64(); > } > #endif > @@ -872,13 +872,13 @@ GEN_INT_ARITH1_64 (addme, 0x1F, 0x0A, 0x07, > PPC_INTEGER); > /* addze addze. addzeo addzeo. */ > static always_inline void gen_op_addze (void) > { > - gen_op_move_T2_T0(); > + tcg_gen_mov_tl(cpu_T[2], cpu_T[0]); > gen_op_add_ze(); > gen_op_check_addc(); > } > static always_inline void gen_op_addzeo (void) > { > - gen_op_move_T2_T0(); > + tcg_gen_mov_tl(cpu_T[2], cpu_T[0]); > gen_op_add_ze(); > gen_op_check_addc(); > gen_op_check_addo(); > @@ -886,13 +886,13 @@ static always_inline void gen_op_addzeo (void) > #if defined(TARGET_PPC64) > static always_inline void gen_op_addze_64 (void) > { > - gen_op_move_T2_T0(); > + tcg_gen_mov_tl(cpu_T[2], cpu_T[0]); > gen_op_add_ze(); > gen_op_check_addc_64(); > } > static always_inline void gen_op_addzeo_64 (void) > { > - gen_op_move_T2_T0(); > + tcg_gen_mov_tl(cpu_T[2], cpu_T[0]); > gen_op_add_ze(); > gen_op_check_addc_64(); > gen_op_check_addo_64(); > @@ -999,7 +999,7 @@ GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, > PPC_INTEGER) > > gen_op_load_gpr_T0(rA(ctx->opcode)); > if (likely(simm != 0)) { > - gen_op_move_T2_T0(); > + tcg_gen_mov_tl(cpu_T[2], cpu_T[0]); > gen_op_addi(simm); > #if defined(TARGET_PPC64) > if (ctx->sf_mode) > @@ -1019,7 +1019,7 @@ GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, > 0x00000000, PPC_INTEGER) > > gen_op_load_gpr_T0(rA(ctx->opcode)); > if (likely(simm != 0)) { > - gen_op_move_T2_T0(); > + tcg_gen_mov_tl(cpu_T[2], cpu_T[0]); > gen_op_addi(simm); > #if defined(TARGET_PPC64) > if (ctx->sf_mode) > @@ -1661,7 +1661,7 @@ GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, > PPC_INTEGER) > int mb, me; > gen_op_load_gpr_T0(rS(ctx->opcode)); > if (SH(ctx->opcode) != 0) { > - gen_op_move_T1_T0(); > + tcg_gen_mov_tl(cpu_T[1], cpu_T[0]); > mb = 32 - SH(ctx->opcode); > me = 31; > #if defined(TARGET_PPC64) > @@ -1691,7 +1691,7 @@ static always_inline void gen_sradi (DisasContext > *ctx, int n) > gen_op_load_gpr_T0(rS(ctx->opcode)); > sh = SH(ctx->opcode) + (n << 5); > if (sh != 0) { > - gen_op_move_T1_T0(); > + tcg_gen_mov_tl(cpu_T[1], cpu_T[0]); > mb = 64 - SH(ctx->opcode); > me = 63; > mask = MASK(mb, me); > @@ -4647,7 +4647,7 @@ static always_inline void gen_405_mulladd_insn > (DisasContext *ctx, > if (opc2 & 0x04) { > /* (n)multiply-and-accumulate (0x0C - 0x0E) */ > gen_op_load_gpr_T2(rt); > - gen_op_move_T1_T0(); > + tcg_gen_mov_tl(cpu_T[1], cpu_T[0]); > gen_op_405_add_T0_T2(); > } > if (opc3 & 0x10) { > > -- .''`. Aurelien Jarno | GPG: 1024D/F1BCDB73 : :' : Debian developer | Electrical Engineer `. `' aurel32@debian.org | aurelien@aurel32.net `- people.debian.org/~aurel32 | www.aurel32.net ^ permalink raw reply [flat|nested] 42+ messages in thread
* [Qemu-devel] [PATCH 4/x] [ppc] Convert op_moven_T2_T0 to TCG 2008-09-02 15:39 ` [Qemu-devel] [PATCH] [ppc] Convert op_move_{T1,T2}_T0 " Andreas Färber 2008-09-02 16:19 ` Aurelien Jarno @ 2008-09-02 16:57 ` Andreas Färber 2008-09-02 22:22 ` [Qemu-devel] [PATCH 5/x] ppc: Convert op_load_gpr_{T0,T1,T2} " Andreas Färber 2008-09-02 23:27 ` [Qemu-devel] [PATCH 4/x] [ppc] Convert op_moven_T2_T0 " Aurélien Jarno 1 sibling, 2 replies; 42+ messages in thread From: Andreas Färber @ 2008-09-02 16:57 UTC (permalink / raw) To: qemu-devel; +Cc: Aurélien Jarno [-- Attachment #1: Type: text/plain, Size: 2459 bytes --] Hello, Attached patch replaces op_moven_T2_T0 with tcg_gen_not_{tl,i64}. Signed-off-by: Andreas Faerber <andreas.faerber@web.de> i64 was used for ppc64, so that I assume it is equivalent to tl. No test setup to check. Andreas diff --git a/target-ppc/op.c b/target-ppc/op.c index 3ee326d..e663e60 100644 --- a/target-ppc/op.c +++ b/target-ppc/op.c @@ -136,13 +136,6 @@ void OPPROTO op_set_Rc0 (void) RETURN(); } -/* Constants load */ -void OPPROTO op_moven_T2_T0 (void) -{ - T2 = ~T0; - RETURN(); -} - /* Generate exceptions */ void OPPROTO op_raise_exception_err (void) { diff --git a/target-ppc/translate.c b/target-ppc/translate.c index fe1de7e..9068936 100644 --- a/target-ppc/translate.c +++ b/target-ppc/translate.c @@ -914,7 +914,7 @@ GEN_INT_ARITH1_64 (neg, 0x1F, 0x08, 0x03, PPC_INTEGER); /* subf subf. subfo subfo. */ static always_inline void gen_op_subfo (void) { - gen_op_moven_T2_T0(); + tcg_gen_not_tl(cpu_T[2], cpu_T[0]); gen_op_subf(); gen_op_check_addo(); } @@ -922,7 +922,7 @@ static always_inline void gen_op_subfo (void) #define gen_op_subf_64 gen_op_subf static always_inline void gen_op_subfo_64 (void) { - gen_op_moven_T2_T0(); + tcg_gen_not_i64(cpu_T[2], cpu_T[0]); gen_op_subf(); gen_op_check_addo_64(); } @@ -936,7 +936,7 @@ static always_inline void gen_op_subfc (void) } static always_inline void gen_op_subfco (void) { - gen_op_moven_T2_T0(); + tcg_gen_not_tl(cpu_T[2], cpu_T[0]); gen_op_subf(); gen_op_check_subfc(); gen_op_check_addo(); @@ -949,7 +949,7 @@ static always_inline void gen_op_subfc_64 (void) } static always_inline void gen_op_subfco_64 (void) { - gen_op_moven_T2_T0(); + tcg_gen_not_i64(cpu_T[2], cpu_T[0]); gen_op_subf(); gen_op_check_subfc_64(); gen_op_check_addo_64(); @@ -959,7 +959,7 @@ GEN_INT_ARITH2_64 (subfc, 0x1F, 0x08, 0x00, PPC_INTEGER); /* subfe subfe. subfeo subfeo. */ static always_inline void gen_op_subfeo (void) { - gen_op_moven_T2_T0(); + tcg_gen_not_tl(cpu_T[2], cpu_T[0]); gen_op_subfe(); gen_op_check_addo(); } @@ -967,7 +967,7 @@ static always_inline void gen_op_subfeo (void) #define gen_op_subfe_64 gen_op_subfe static always_inline void gen_op_subfeo_64 (void) { - gen_op_moven_T2_T0(); + tcg_gen_not_i64(cpu_T[2], cpu_T[0]); gen_op_subfe_64(); gen_op_check_addo_64(); } [-- Attachment #2: op_moven.diff --] [-- Type: application/octet-stream, Size: 2179 bytes --] diff --git a/target-ppc/op.c b/target-ppc/op.c index 3ee326d..e663e60 100644 --- a/target-ppc/op.c +++ b/target-ppc/op.c @@ -136,13 +136,6 @@ void OPPROTO op_set_Rc0 (void) RETURN(); } -/* Constants load */ -void OPPROTO op_moven_T2_T0 (void) -{ - T2 = ~T0; - RETURN(); -} - /* Generate exceptions */ void OPPROTO op_raise_exception_err (void) { diff --git a/target-ppc/translate.c b/target-ppc/translate.c index fe1de7e..9068936 100644 --- a/target-ppc/translate.c +++ b/target-ppc/translate.c @@ -914,7 +914,7 @@ GEN_INT_ARITH1_64 (neg, 0x1F, 0x08, 0x03, PPC_INTEGER); /* subf subf. subfo subfo. */ static always_inline void gen_op_subfo (void) { - gen_op_moven_T2_T0(); + tcg_gen_not_tl(cpu_T[2], cpu_T[0]); gen_op_subf(); gen_op_check_addo(); } @@ -922,7 +922,7 @@ static always_inline void gen_op_subfo (void) #define gen_op_subf_64 gen_op_subf static always_inline void gen_op_subfo_64 (void) { - gen_op_moven_T2_T0(); + tcg_gen_not_i64(cpu_T[2], cpu_T[0]); gen_op_subf(); gen_op_check_addo_64(); } @@ -936,7 +936,7 @@ static always_inline void gen_op_subfc (void) } static always_inline void gen_op_subfco (void) { - gen_op_moven_T2_T0(); + tcg_gen_not_tl(cpu_T[2], cpu_T[0]); gen_op_subf(); gen_op_check_subfc(); gen_op_check_addo(); @@ -949,7 +949,7 @@ static always_inline void gen_op_subfc_64 (void) } static always_inline void gen_op_subfco_64 (void) { - gen_op_moven_T2_T0(); + tcg_gen_not_i64(cpu_T[2], cpu_T[0]); gen_op_subf(); gen_op_check_subfc_64(); gen_op_check_addo_64(); @@ -959,7 +959,7 @@ GEN_INT_ARITH2_64 (subfc, 0x1F, 0x08, 0x00, PPC_INTEGER); /* subfe subfe. subfeo subfeo. */ static always_inline void gen_op_subfeo (void) { - gen_op_moven_T2_T0(); + tcg_gen_not_tl(cpu_T[2], cpu_T[0]); gen_op_subfe(); gen_op_check_addo(); } @@ -967,7 +967,7 @@ static always_inline void gen_op_subfeo (void) #define gen_op_subfe_64 gen_op_subfe static always_inline void gen_op_subfeo_64 (void) { - gen_op_moven_T2_T0(); + tcg_gen_not_i64(cpu_T[2], cpu_T[0]); gen_op_subfe_64(); gen_op_check_addo_64(); } [-- Attachment #3: Type: text/plain, Size: 1 bytes --] ^ permalink raw reply related [flat|nested] 42+ messages in thread
* [Qemu-devel] [PATCH 5/x] ppc: Convert op_load_gpr_{T0,T1,T2} to TCG 2008-09-02 16:57 ` [Qemu-devel] [PATCH 4/x] [ppc] Convert op_moven_T2_T0 " Andreas Färber @ 2008-09-02 22:22 ` Andreas Färber 2008-09-02 23:20 ` Aurelien Jarno 2008-09-02 23:27 ` [Qemu-devel] [PATCH 4/x] [ppc] Convert op_moven_T2_T0 " Aurélien Jarno 1 sibling, 1 reply; 42+ messages in thread From: Andreas Färber @ 2008-09-02 22:22 UTC (permalink / raw) To: qemu-devel [-- Attachment #1: Type: text/plain, Size: 59175 bytes --] Replace op_load_gpr_T0, op_load_gpr_T1 and op_load_gpr_T2 with tcg_gen_mov_tl. To do so, introduce TCG variables cpu_gpr[0..31]. Signed-off-by: Andreas Faerber <andreas.faerber@web.de> --- target-ppc/translate.c | 418 ++++++++++++++++++++++++++ +--------------------- 1 files changed, 233 insertions(+), 185 deletions(-) diff --git a/target-ppc/translate.c b/target-ppc/translate.c index 9068936..0fe119a 100644 --- a/target-ppc/translate.c +++ b/target-ppc/translate.c @@ -44,15 +44,57 @@ / *****************************************************************************/ /* Code translation helpers */ -static TCGv cpu_env, cpu_T[3]; +/* global register indexes */ +static TCGv cpu_env; +static TCGv cpu_gpr[32]; + +/* dyngen register indexes */ +static TCGv cpu_T[3]; #include "gen-icount.h" void ppc_translate_init(void) { + int i; static int done_init = 0; + static const char* const gprnames[32] = { + "r0", + "r1", + "r2", + "r3", + "r4", + "r5", + "r6", + "r7", + "r8", + "r9", + "r10", + "r11", + "r12", + "r13", + "r14", + "r15", + "r16", + "r17", + "r18", + "r19", + "r20", + "r21", + "r22", + "r23", + "r24", + "r25", + "r26", + "r27", + "r28", + "r29", + "r30", + "r31" + }; + if (done_init) return; + cpu_env = tcg_global_reg_new(TCG_TYPE_PTR, TCG_AREG0, "env"); #if TARGET_LONG_BITS > HOST_LONG_BITS cpu_T[0] = tcg_global_mem_new(TCG_TYPE_TL, @@ -67,6 +109,12 @@ void ppc_translate_init(void) cpu_T[2] = tcg_global_reg_new(TCG_TYPE_TL, TCG_AREG3, "T2"); #endif + for (i = 0; i < 32; i++) { + cpu_gpr[i] = tcg_global_mem_new(TCG_TYPE_TL, TCG_AREG0, + offsetof(CPUState, gpr[i]), + gprnames[i]); + } + /* register helpers */ #undef DEF_HELPER #define DEF_HELPER(ret, name, params) tcg_register_helper(name, #name); @@ -667,8 +715,8 @@ static opc_handler_t invalid_handler = { #define __GEN_INT_ARITH2(name, opc1, opc2, opc3, inval, type) \ GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \ { \ - gen_op_load_gpr_T0(rA(ctx- >opcode)); \ - gen_op_load_gpr_T1(rB(ctx- >opcode)); \ + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx- >opcode)]); \ + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx- >opcode)]); \ gen_op_ ##name(); \ gen_op_store_T0_gpr(rD(ctx- >opcode)); \ if (unlikely(Rc(ctx->opcode) != 0)) \ @@ -678,8 +726,8 @@ GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \ #define __GEN_INT_ARITH2_O(name, opc1, opc2, opc3, inval, type) \ GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \ { \ - gen_op_load_gpr_T0(rA(ctx- >opcode)); \ - gen_op_load_gpr_T1(rB(ctx- >opcode)); \ + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx- >opcode)]); \ + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx- >opcode)]); \ gen_op_ ##name(); \ gen_op_store_T0_gpr(rD(ctx- >opcode)); \ if (unlikely(Rc(ctx->opcode) != 0)) \ @@ -689,7 +737,7 @@ GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \ #define __GEN_INT_ARITH1(name, opc1, opc2, opc3, type) \ GEN_HANDLER(name, opc1, opc2, opc3, 0x0000F800, type) \ { \ - gen_op_load_gpr_T0(rA(ctx- >opcode)); \ + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx- >opcode)]); \ gen_op_ ##name(); \ gen_op_store_T0_gpr(rD(ctx- >opcode)); \ if (unlikely(Rc(ctx->opcode) != 0)) \ @@ -698,7 +746,7 @@ GEN_HANDLER(name, opc1, opc2, opc3, 0x0000F800, type) \ #define __GEN_INT_ARITH1_O(name, opc1, opc2, opc3, type) \ GEN_HANDLER(name, opc1, opc2, opc3, 0x0000F800, type) \ { \ - gen_op_load_gpr_T0(rA(ctx- >opcode)); \ + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx- >opcode)]); \ gen_op_ ##name(); \ gen_op_store_T0_gpr(rD(ctx- >opcode)); \ if (unlikely(Rc(ctx->opcode) != 0)) \ @@ -723,8 +771,8 @@ __GEN_INT_ARITH1_O(name##o, opc1, opc2, opc3 | 0x10, type) #define __GEN_INT_ARITH2_64(name, opc1, opc2, opc3, inval, type) \ GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \ { \ - gen_op_load_gpr_T0(rA(ctx- >opcode)); \ - gen_op_load_gpr_T1(rB(ctx- >opcode)); \ + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx- >opcode)]); \ + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx- >opcode)]); \ if (ctx- >sf_mode) \ gen_op_##name##_64(); \ else \ @@ -737,8 +785,8 @@ GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \ #define __GEN_INT_ARITH2_O_64(name, opc1, opc2, opc3, inval, type) \ GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \ { \ - gen_op_load_gpr_T0(rA(ctx- >opcode)); \ - gen_op_load_gpr_T1(rB(ctx- >opcode)); \ + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx- >opcode)]); \ + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx- >opcode)]); \ if (ctx- >sf_mode) \ gen_op_##name##_64(); \ else \ @@ -751,7 +799,7 @@ GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \ #define __GEN_INT_ARITH1_64(name, opc1, opc2, opc3, type) \ GEN_HANDLER(name, opc1, opc2, opc3, 0x0000F800, type) \ { \ - gen_op_load_gpr_T0(rA(ctx- >opcode)); \ + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx- >opcode)]); \ if (ctx- >sf_mode) \ gen_op_##name##_64(); \ else \ @@ -763,7 +811,7 @@ GEN_HANDLER(name, opc1, opc2, opc3, 0x0000F800, type) \ #define __GEN_INT_ARITH1_O_64(name, opc1, opc2, opc3, type) \ GEN_HANDLER(name, opc1, opc2, opc3, 0x0000F800, type) \ { \ - gen_op_load_gpr_T0(rA(ctx- >opcode)); \ + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx- >opcode)]); \ if (ctx- >sf_mode) \ gen_op_##name##_64(); \ else \ @@ -986,7 +1034,7 @@ GEN_HANDLER(addi, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) /* li case */ tcg_gen_movi_tl(cpu_T[0], simm); } else { - gen_op_load_gpr_T0(rA(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); if (likely(simm != 0)) gen_op_addi(simm); } @@ -997,7 +1045,7 @@ GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) { target_long simm = SIMM(ctx->opcode); - gen_op_load_gpr_T0(rA(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); if (likely(simm != 0)) { tcg_gen_mov_tl(cpu_T[2], cpu_T[0]); gen_op_addi(simm); @@ -1017,7 +1065,7 @@ GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) { target_long simm = SIMM(ctx->opcode); - gen_op_load_gpr_T0(rA(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); if (likely(simm != 0)) { tcg_gen_mov_tl(cpu_T[2], cpu_T[0]); gen_op_addi(simm); @@ -1042,7 +1090,7 @@ GEN_HANDLER(addis, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) /* lis case */ tcg_gen_movi_tl(cpu_T[0], simm << 16); } else { - gen_op_load_gpr_T0(rA(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); if (likely(simm != 0)) gen_op_addi(simm << 16); } @@ -1051,14 +1099,14 @@ GEN_HANDLER(addis, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) /* mulli */ GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) { - gen_op_load_gpr_T0(rA(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); gen_op_mulli(SIMM(ctx->opcode)); gen_op_store_T0_gpr(rD(ctx->opcode)); } /* subfic */ GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) { - gen_op_load_gpr_T0(rA(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); #if defined(TARGET_PPC64) if (ctx->sf_mode) gen_op_subfic_64(SIMM(ctx->opcode)); @@ -1086,8 +1134,8 @@ GEN_INT_ARITH2 (divdu, 0x1F, 0x09, 0x0E, PPC_64B); #define GEN_CMP(name, opc, type) \ GEN_HANDLER(name, 0x1F, 0x00, opc, 0x00400000, type) \ { \ - gen_op_load_gpr_T0(rA(ctx- >opcode)); \ - gen_op_load_gpr_T1(rB(ctx- >opcode)); \ + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx- >opcode)]); \ + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx- >opcode)]); \ if (ctx->sf_mode && (ctx->opcode & 0x00200000)) \ gen_op_##name##_64(); \ else \ @@ -1098,8 +1146,8 @@ GEN_HANDLER(name, 0x1F, 0x00, opc, 0x00400000, type) \ #define GEN_CMP(name, opc, type) \ GEN_HANDLER(name, 0x1F, 0x00, opc, 0x00400000, type) \ { \ - gen_op_load_gpr_T0(rA(ctx- >opcode)); \ - gen_op_load_gpr_T1(rB(ctx- >opcode)); \ + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx- >opcode)]); \ + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx- >opcode)]); \ gen_op_ ##name(); \ gen_op_store_T0_crf(crfD(ctx- >opcode)); \ } @@ -1110,7 +1158,7 @@ GEN_CMP(cmp, 0x00, PPC_INTEGER); /* cmpi */ GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER) { - gen_op_load_gpr_T0(rA(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); #if defined(TARGET_PPC64) if (ctx->sf_mode && (ctx->opcode & 0x00200000)) gen_op_cmpi_64(SIMM(ctx->opcode)); @@ -1124,7 +1172,7 @@ GEN_CMP(cmpl, 0x01, PPC_INTEGER); /* cmpli */ GEN_HANDLER(cmpli, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER) { - gen_op_load_gpr_T0(rA(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); #if defined(TARGET_PPC64) if (ctx->sf_mode && (ctx->opcode & 0x00200000)) gen_op_cmpli_64(UIMM(ctx->opcode)); @@ -1143,9 +1191,9 @@ GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL) if (rA(ctx->opcode) == 0) { tcg_gen_movi_tl(cpu_T[0], 0); } else { - gen_op_load_gpr_T1(rA(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rA(ctx->opcode)]); } - gen_op_load_gpr_T2(rB(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[2], cpu_gpr[rB(ctx->opcode)]); mask = 1 << (3 - (bi & 0x03)); gen_op_load_crf_T0(bi >> 2); gen_op_test_true(mask); @@ -1157,8 +1205,8 @@ GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL) #define __GEN_LOGICAL2(name, opc2, opc3, type) \ GEN_HANDLER(name, 0x1F, opc2, opc3, 0x00000000, type) \ { \ - gen_op_load_gpr_T0(rS(ctx- >opcode)); \ - gen_op_load_gpr_T1(rB(ctx- >opcode)); \ + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx- >opcode)]); \ + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx- >opcode)]); \ gen_op_ ##name(); \ gen_op_store_T0_gpr(rA(ctx- >opcode)); \ if (unlikely(Rc(ctx->opcode) != 0)) \ @@ -1170,7 +1218,7 @@ __GEN_LOGICAL2(name, 0x1C, opc, type) #define GEN_LOGICAL1(name, opc, type) \ GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type) \ { \ - gen_op_load_gpr_T0(rS(ctx- >opcode)); \ + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx- >opcode)]); \ gen_op_ ##name(); \ gen_op_store_T0_gpr(rA(ctx- >opcode)); \ if (unlikely(Rc(ctx->opcode) != 0)) \ @@ -1184,7 +1232,7 @@ GEN_LOGICAL2(andc, 0x01, PPC_INTEGER); /* andi. */ GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) { - gen_op_load_gpr_T0(rS(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); gen_op_andi_T0(UIMM(ctx->opcode)); gen_op_store_T0_gpr(rA(ctx->opcode)); gen_set_Rc0(ctx); @@ -1192,7 +1240,7 @@ GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) /* andis. */ GEN_HANDLER2(andis_, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) { - gen_op_load_gpr_T0(rS(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); gen_op_andi_T0(UIMM(ctx->opcode) << 16); gen_op_store_T0_gpr(rA(ctx->opcode)); gen_set_Rc0(ctx); @@ -1221,16 +1269,16 @@ GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER) rb = rB(ctx->opcode); /* Optimisation for mr. ri case */ if (rs != ra || rs != rb) { - gen_op_load_gpr_T0(rs); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rs]); if (rs != rb) { - gen_op_load_gpr_T1(rb); + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rb]); gen_op_or(); } gen_op_store_T0_gpr(ra); if (unlikely(Rc(ctx->opcode) != 0)) gen_set_Rc0(ctx); } else if (unlikely(Rc(ctx->opcode) != 0)) { - gen_op_load_gpr_T0(rs); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rs]); gen_set_Rc0(ctx); #if defined(TARGET_PPC64) } else { @@ -1286,10 +1334,10 @@ GEN_LOGICAL2(orc, 0x0C, PPC_INTEGER); /* xor & xor. */ GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER) { - gen_op_load_gpr_T0(rS(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); /* Optimisation for "set to zero" case */ if (rS(ctx->opcode) != rB(ctx->opcode)) { - gen_op_load_gpr_T1(rB(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); gen_op_xor(); } else { tcg_gen_movi_tl(cpu_T[0], 0); @@ -1308,7 +1356,7 @@ GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) /* XXX: should handle special NOPs for POWER series */ return; } - gen_op_load_gpr_T0(rS(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); if (likely(uimm != 0)) gen_op_ori(uimm); gen_op_store_T0_gpr(rA(ctx->opcode)); @@ -1322,7 +1370,7 @@ GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) /* NOP */ return; } - gen_op_load_gpr_T0(rS(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); if (likely(uimm != 0)) gen_op_ori(uimm << 16); gen_op_store_T0_gpr(rA(ctx->opcode)); @@ -1336,7 +1384,7 @@ GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) /* NOP */ return; } - gen_op_load_gpr_T0(rS(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); if (likely(uimm != 0)) gen_op_xori(uimm); gen_op_store_T0_gpr(rA(ctx->opcode)); @@ -1351,7 +1399,7 @@ GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) /* NOP */ return; } - gen_op_load_gpr_T0(rS(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); if (likely(uimm != 0)) gen_op_xori(uimm << 16); gen_op_store_T0_gpr(rA(ctx->opcode)); @@ -1360,7 +1408,7 @@ GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) /* popcntb : PowerPC 2.03 specification */ GEN_HANDLER(popcntb, 0x1F, 0x03, 0x03, 0x0000F801, PPC_POPCNTB) { - gen_op_load_gpr_T0(rS(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); #if defined(TARGET_PPC64) if (ctx->sf_mode) gen_op_popcntb_64(); @@ -1389,18 +1437,18 @@ GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) sh = SH(ctx->opcode); if (likely(sh == 0)) { if (likely(mb == 0 && me == 31)) { - gen_op_load_gpr_T0(rS(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); goto do_store; } else if (likely(mb == 31 && me == 0)) { - gen_op_load_gpr_T0(rA(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); goto do_store; } - gen_op_load_gpr_T0(rS(ctx->opcode)); - gen_op_load_gpr_T1(rA(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rA(ctx->opcode)]); goto do_mask; } - gen_op_load_gpr_T0(rS(ctx->opcode)); - gen_op_load_gpr_T1(rA(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rA(ctx->opcode)]); gen_op_rotli32_T0(SH(ctx->opcode)); do_mask: #if defined(TARGET_PPC64) @@ -1424,7 +1472,7 @@ GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) sh = SH(ctx->opcode); mb = MB(ctx->opcode); me = ME(ctx->opcode); - gen_op_load_gpr_T0(rS(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); if (likely(sh == 0)) { goto do_mask; } @@ -1461,8 +1509,8 @@ GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) mb = MB(ctx->opcode); me = ME(ctx->opcode); - gen_op_load_gpr_T0(rS(ctx->opcode)); - gen_op_load_gpr_T1(rB(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); gen_op_rotl32_T0_T1(); if (unlikely(mb != 0 || me != 31)) { #if defined(TARGET_PPC64) @@ -1527,7 +1575,7 @@ static always_inline void gen_andi_T1_64 (DisasContext *ctx, uint64_t mask) static always_inline void gen_rldinm (DisasContext *ctx, uint32_t mb, uint32_t me, uint32_t sh) { - gen_op_load_gpr_T0(rS(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); if (likely(sh == 0)) { goto do_mask; } @@ -1587,8 +1635,8 @@ GEN_PPC64_R4(rldic, 0x1E, 0x04); static always_inline void gen_rldnm (DisasContext *ctx, uint32_t mb, uint32_t me) { - gen_op_load_gpr_T0(rS(ctx->opcode)); - gen_op_load_gpr_T1(rB(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); gen_op_rotl64_T0_T1(); if (unlikely(mb != 0 || me != 63)) { gen_andi_T0_64(ctx, MASK(mb, me)); @@ -1627,15 +1675,15 @@ static always_inline void gen_rldimi (DisasContext *ctx, int mbn, int shn) me = 63 - sh; if (likely(sh == 0)) { if (likely(mb == 0)) { - gen_op_load_gpr_T0(rS(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); goto do_store; } - gen_op_load_gpr_T0(rS(ctx->opcode)); - gen_op_load_gpr_T1(rA(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rA(ctx->opcode)]); goto do_mask; } - gen_op_load_gpr_T0(rS(ctx->opcode)); - gen_op_load_gpr_T1(rA(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rA(ctx->opcode)]); gen_op_rotli64_T0(sh); do_mask: mask = MASK(mb, me); @@ -1659,7 +1707,7 @@ __GEN_LOGICAL2(sraw, 0x18, 0x18, PPC_INTEGER); GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER) { int mb, me; - gen_op_load_gpr_T0(rS(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); if (SH(ctx->opcode) != 0) { tcg_gen_mov_tl(cpu_T[1], cpu_T[0]); mb = 32 - SH(ctx->opcode); @@ -1688,7 +1736,7 @@ static always_inline void gen_sradi (DisasContext *ctx, int n) uint64_t mask; int sh, mb, me; - gen_op_load_gpr_T0(rS(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); sh = SH(ctx->opcode) + (n << 5); if (sh != 0) { tcg_gen_mov_tl(cpu_T[1], cpu_T[0]); @@ -2082,7 +2130,7 @@ static always_inline void gen_addr_imm_index (DisasContext *ctx, if (rA(ctx->opcode) == 0) { tcg_gen_movi_tl(cpu_T[0], simm); } else { - gen_op_load_gpr_T0(rA(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); if (likely(simm != 0)) gen_op_addi(simm); } @@ -2094,10 +2142,10 @@ static always_inline void gen_addr_imm_index (DisasContext *ctx, static always_inline void gen_addr_reg_index (DisasContext *ctx) { if (rA(ctx->opcode) == 0) { - gen_op_load_gpr_T0(rB(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rB(ctx->opcode)]); } else { - gen_op_load_gpr_T0(rA(ctx->opcode)); - gen_op_load_gpr_T1(rB(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); gen_op_add(); } #ifdef DEBUG_MEMORY_ACCESSES @@ -2110,7 +2158,7 @@ static always_inline void gen_addr_register (DisasContext *ctx) if (rA(ctx->opcode) == 0) { tcg_gen_movi_tl(cpu_T[0], 0); } else { - gen_op_load_gpr_T0(rA(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); } #ifdef DEBUG_MEMORY_ACCESSES gen_op_print_mem_EA(); @@ -2309,7 +2357,7 @@ GEN_HANDLER(lq, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX) GEN_HANDLER(st##width, opc, 0xFF, 0xFF, 0x00000000, type) \ { \ gen_addr_imm_index(ctx, 0); \ - gen_op_load_gpr_T1(rS(ctx- >opcode)); \ + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx- >opcode)]); \ op_ldst (st##width); \ } @@ -2324,7 +2372,7 @@ GEN_HANDLER(st##width##u, opc, 0xFF, 0xFF, 0x00000000, type) \ gen_addr_imm_index(ctx, 0x03); \ else \ gen_addr_imm_index(ctx, 0); \ - gen_op_load_gpr_T1(rS(ctx- >opcode)); \ + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx- >opcode)]); \ op_ldst (st##width); \ gen_op_store_T0_gpr(rA(ctx- >opcode)); \ } @@ -2337,7 +2385,7 @@ GEN_HANDLER(st##width##ux, 0x1F, opc2, opc3, 0x00000001, type) \ return; \ } \ gen_addr_reg_index (ctx); \ - gen_op_load_gpr_T1(rS(ctx- >opcode)); \ + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx- >opcode)]); \ op_ldst (st##width); \ gen_op_store_T0_gpr(rA(ctx- >opcode)); \ } @@ -2346,7 +2394,7 @@ GEN_HANDLER(st##width##ux, 0x1F, opc2, opc3, 0x00000001, type) \ GEN_HANDLER(st##width##x, 0x1F, opc2, opc3, 0x00000001, type) \ { \ gen_addr_reg_index (ctx); \ - gen_op_load_gpr_T1(rS(ctx- >opcode)); \ + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx- >opcode)]); \ op_ldst (st##width); \ } @@ -2391,10 +2439,10 @@ GEN_HANDLER(std, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B) return; } gen_addr_imm_index(ctx, 0x03); - gen_op_load_gpr_T1(rs); + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rs]); op_ldst(std); gen_op_addi(8); - gen_op_load_gpr_T1(rs + 1); + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rs + 1]); op_ldst(std); #endif } else { @@ -2406,7 +2454,7 @@ GEN_HANDLER(std, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B) } } gen_addr_imm_index(ctx, 0x03); - gen_op_load_gpr_T1(rs); + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rs]); op_ldst(std); if (Rc(ctx->opcode)) gen_op_store_T0_gpr(rA(ctx->opcode)); @@ -2599,7 +2647,7 @@ GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES) /* NIP cannot be restored if the memory exception comes from an helper */ gen_update_nip(ctx, ctx->nip - 4); gen_addr_reg_index(ctx); - gen_op_load_gpr_T1(rS(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]); op_stwcx(); } @@ -2629,7 +2677,7 @@ GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B) /* NIP cannot be restored if the memory exception comes from an helper */ gen_update_nip(ctx, ctx->nip - 4); gen_addr_reg_index(ctx); - gen_op_load_gpr_T1(rS(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]); op_stdcx(); } #endif /* defined(TARGET_PPC64) */ @@ -3154,8 +3202,8 @@ GEN_HANDLER(sc, 0x11, 0xFF, 0xFF, 0x03FFF01D, PPC_FLOW) /* tw */ GEN_HANDLER(tw, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW) { - gen_op_load_gpr_T0(rA(ctx->opcode)); - gen_op_load_gpr_T1(rB(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); /* Update the nip since this might generate a trap exception */ gen_update_nip(ctx, ctx->nip); gen_op_tw(TO(ctx->opcode)); @@ -3164,7 +3212,7 @@ GEN_HANDLER(tw, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW) /* twi */ GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW) { - gen_op_load_gpr_T0(rA(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); tcg_gen_movi_tl(cpu_T[1], SIMM(ctx->opcode)); /* Update the nip since this might generate a trap exception */ gen_update_nip(ctx, ctx->nip); @@ -3175,8 +3223,8 @@ GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW) /* td */ GEN_HANDLER(td, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B) { - gen_op_load_gpr_T0(rA(ctx->opcode)); - gen_op_load_gpr_T1(rB(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); /* Update the nip since this might generate a trap exception */ gen_update_nip(ctx, ctx->nip); gen_op_td(TO(ctx->opcode)); @@ -3185,7 +3233,7 @@ GEN_HANDLER(td, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B) /* tdi */ GEN_HANDLER(tdi, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B) { - gen_op_load_gpr_T0(rA(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); tcg_gen_movi_tl(cpu_T[1], SIMM(ctx->opcode)); /* Update the nip since this might generate a trap exception */ gen_update_nip(ctx, ctx->nip); @@ -3309,7 +3357,7 @@ GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC) { uint32_t crm, crn; - gen_op_load_gpr_T0(rS(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); crm = CRM(ctx->opcode); if (likely((ctx->opcode & 0x00100000) || (crm ^ (crm - 1)) == 0)) { crn = ffs(crm); @@ -3332,7 +3380,7 @@ GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B) GEN_EXCP_PRIVREG(ctx); return; } - gen_op_load_gpr_T0(rS(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); if (ctx->opcode & 0x00010000) { /* Special form that does not need any synchronisation */ gen_op_update_riee(); @@ -3360,7 +3408,7 @@ GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001FF801, PPC_MISC) GEN_EXCP_PRIVREG(ctx); return; } - gen_op_load_gpr_T0(rS(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); if (ctx->opcode & 0x00010000) { /* Special form that does not need any synchronisation */ gen_op_update_riee(); @@ -3399,7 +3447,7 @@ GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000001, PPC_MISC) write_cb = ctx->spr_cb[sprn].uea_write; if (likely(write_cb != NULL)) { if (likely(write_cb != SPR_NOACCESS)) { - gen_op_load_gpr_T0(rS(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); (*write_cb)(ctx, sprn); } else { /* Privilege exception */ @@ -3628,7 +3676,7 @@ GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT) GEN_EXCP_PRIVREG(ctx); return; } - gen_op_load_gpr_T1(rB(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); gen_op_srli_T1(28); gen_op_load_sr(); gen_op_store_T0_gpr(rD(ctx->opcode)); @@ -3645,7 +3693,7 @@ GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT) GEN_EXCP_PRIVREG(ctx); return; } - gen_op_load_gpr_T0(rS(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); tcg_gen_movi_tl(cpu_T[1], SR(ctx->opcode)); gen_op_store_sr(); #endif @@ -3661,8 +3709,8 @@ GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT) GEN_EXCP_PRIVREG(ctx); return; } - gen_op_load_gpr_T0(rS(ctx->opcode)); - gen_op_load_gpr_T1(rB(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); gen_op_srli_T1(28); gen_op_store_sr(); #endif @@ -3697,7 +3745,7 @@ GEN_HANDLER2(mfsrin_64b, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001, GEN_EXCP_PRIVREG(ctx); return; } - gen_op_load_gpr_T1(rB(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); gen_op_srli_T1(28); gen_op_load_slb(); gen_op_store_T0_gpr(rD(ctx->opcode)); @@ -3714,7 +3762,7 @@ GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B) GEN_EXCP_PRIVREG(ctx); return; } - gen_op_load_gpr_T0(rS(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); tcg_gen_movi_tl(cpu_T[1], SR(ctx->opcode)); gen_op_store_slb(); #endif @@ -3731,8 +3779,8 @@ GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001, GEN_EXCP_PRIVREG(ctx); return; } - gen_op_load_gpr_T0(rS(ctx->opcode)); - gen_op_load_gpr_T1(rB(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); gen_op_srli_T1(28); gen_op_store_slb(); #endif @@ -3765,7 +3813,7 @@ GEN_HANDLER(tlbie, 0x1F, 0x12, 0x09, 0x03FF0001, PPC_MEM_TLBIE) GEN_EXCP_PRIVOPC(ctx); return; } - gen_op_load_gpr_T0(rB(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rB(ctx->opcode)]); #if defined(TARGET_PPC64) if (ctx->sf_mode) gen_op_tlbie_64(); @@ -3817,7 +3865,7 @@ GEN_HANDLER(slbie, 0x1F, 0x12, 0x0D, 0x03FF0001, PPC_SLBI) GEN_EXCP_PRIVOPC(ctx); return; } - gen_op_load_gpr_T0(rB(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rB(ctx->opcode)]); gen_op_slbie(); #endif } @@ -3848,7 +3896,7 @@ GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN) { /* Should check EAR[E] & alignment ! */ gen_addr_reg_index(ctx); - gen_op_load_gpr_T1(rS(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]); op_ecowx(); } @@ -3856,7 +3904,7 @@ GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN) /* abs - abs. */ GEN_HANDLER(abs, 0x1F, 0x08, 0x0B, 0x0000F800, PPC_POWER_BR) { - gen_op_load_gpr_T0(rA(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); gen_op_POWER_abs(); gen_op_store_T0_gpr(rD(ctx->opcode)); if (unlikely(Rc(ctx->opcode) != 0)) @@ -3866,7 +3914,7 @@ GEN_HANDLER(abs, 0x1F, 0x08, 0x0B, 0x0000F800, PPC_POWER_BR) /* abso - abso. */ GEN_HANDLER(abso, 0x1F, 0x08, 0x1B, 0x0000F800, PPC_POWER_BR) { - gen_op_load_gpr_T0(rA(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); gen_op_POWER_abso(); gen_op_store_T0_gpr(rD(ctx->opcode)); if (unlikely(Rc(ctx->opcode) != 0)) @@ -3876,7 +3924,7 @@ GEN_HANDLER(abso, 0x1F, 0x08, 0x1B, 0x0000F800, PPC_POWER_BR) /* clcs */ GEN_HANDLER(clcs, 0x1F, 0x10, 0x13, 0x0000F800, PPC_POWER_BR) { - gen_op_load_gpr_T0(rA(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); gen_op_POWER_clcs(); /* Rc=1 sets CR0 to an undefined state */ gen_op_store_T0_gpr(rD(ctx->opcode)); @@ -3885,8 +3933,8 @@ GEN_HANDLER(clcs, 0x1F, 0x10, 0x13, 0x0000F800, PPC_POWER_BR) /* div - div. */ GEN_HANDLER(div, 0x1F, 0x0B, 0x0A, 0x00000000, PPC_POWER_BR) { - gen_op_load_gpr_T0(rA(ctx->opcode)); - gen_op_load_gpr_T1(rB(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); gen_op_POWER_div(); gen_op_store_T0_gpr(rD(ctx->opcode)); if (unlikely(Rc(ctx->opcode) != 0)) @@ -3896,8 +3944,8 @@ GEN_HANDLER(div, 0x1F, 0x0B, 0x0A, 0x00000000, PPC_POWER_BR) /* divo - divo. */ GEN_HANDLER(divo, 0x1F, 0x0B, 0x1A, 0x00000000, PPC_POWER_BR) { - gen_op_load_gpr_T0(rA(ctx->opcode)); - gen_op_load_gpr_T1(rB(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); gen_op_POWER_divo(); gen_op_store_T0_gpr(rD(ctx->opcode)); if (unlikely(Rc(ctx->opcode) != 0)) @@ -3907,8 +3955,8 @@ GEN_HANDLER(divo, 0x1F, 0x0B, 0x1A, 0x00000000, PPC_POWER_BR) /* divs - divs. */ GEN_HANDLER(divs, 0x1F, 0x0B, 0x0B, 0x00000000, PPC_POWER_BR) { - gen_op_load_gpr_T0(rA(ctx->opcode)); - gen_op_load_gpr_T1(rB(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); gen_op_POWER_divs(); gen_op_store_T0_gpr(rD(ctx->opcode)); if (unlikely(Rc(ctx->opcode) != 0)) @@ -3918,8 +3966,8 @@ GEN_HANDLER(divs, 0x1F, 0x0B, 0x0B, 0x00000000, PPC_POWER_BR) /* divso - divso. */ GEN_HANDLER(divso, 0x1F, 0x0B, 0x1B, 0x00000000, PPC_POWER_BR) { - gen_op_load_gpr_T0(rA(ctx->opcode)); - gen_op_load_gpr_T1(rB(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); gen_op_POWER_divso(); gen_op_store_T0_gpr(rD(ctx->opcode)); if (unlikely(Rc(ctx->opcode) != 0)) @@ -3929,8 +3977,8 @@ GEN_HANDLER(divso, 0x1F, 0x0B, 0x1B, 0x00000000, PPC_POWER_BR) /* doz - doz. */ GEN_HANDLER(doz, 0x1F, 0x08, 0x08, 0x00000000, PPC_POWER_BR) { - gen_op_load_gpr_T0(rA(ctx->opcode)); - gen_op_load_gpr_T1(rB(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); gen_op_POWER_doz(); gen_op_store_T0_gpr(rD(ctx->opcode)); if (unlikely(Rc(ctx->opcode) != 0)) @@ -3940,8 +3988,8 @@ GEN_HANDLER(doz, 0x1F, 0x08, 0x08, 0x00000000, PPC_POWER_BR) /* dozo - dozo. */ GEN_HANDLER(dozo, 0x1F, 0x08, 0x18, 0x00000000, PPC_POWER_BR) { - gen_op_load_gpr_T0(rA(ctx->opcode)); - gen_op_load_gpr_T1(rB(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); gen_op_POWER_dozo(); gen_op_store_T0_gpr(rD(ctx->opcode)); if (unlikely(Rc(ctx->opcode) != 0)) @@ -3951,7 +3999,7 @@ GEN_HANDLER(dozo, 0x1F, 0x08, 0x18, 0x00000000, PPC_POWER_BR) /* dozi */ GEN_HANDLER(dozi, 0x09, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR) { - gen_op_load_gpr_T0(rA(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); tcg_gen_movi_tl(cpu_T[1], SIMM(ctx->opcode)); gen_op_POWER_doz(); gen_op_store_T0_gpr(rD(ctx->opcode)); @@ -4001,8 +4049,8 @@ GEN_HANDLER(lscbx, 0x1F, 0x15, 0x08, 0x00000000, PPC_POWER_BR) /* maskg - maskg. */ GEN_HANDLER(maskg, 0x1F, 0x1D, 0x00, 0x00000000, PPC_POWER_BR) { - gen_op_load_gpr_T0(rS(ctx->opcode)); - gen_op_load_gpr_T1(rB(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); gen_op_POWER_maskg(); gen_op_store_T0_gpr(rA(ctx->opcode)); if (unlikely(Rc(ctx->opcode) != 0)) @@ -4012,9 +4060,9 @@ GEN_HANDLER(maskg, 0x1F, 0x1D, 0x00, 0x00000000, PPC_POWER_BR) /* maskir - maskir. */ GEN_HANDLER(maskir, 0x1F, 0x1D, 0x10, 0x00000000, PPC_POWER_BR) { - gen_op_load_gpr_T0(rA(ctx->opcode)); - gen_op_load_gpr_T1(rS(ctx->opcode)); - gen_op_load_gpr_T2(rB(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]); + tcg_gen_mov_tl(cpu_T[2], cpu_gpr[rB(ctx->opcode)]); gen_op_POWER_maskir(); gen_op_store_T0_gpr(rA(ctx->opcode)); if (unlikely(Rc(ctx->opcode) != 0)) @@ -4024,8 +4072,8 @@ GEN_HANDLER(maskir, 0x1F, 0x1D, 0x10, 0x00000000, PPC_POWER_BR) /* mul - mul. */ GEN_HANDLER(mul, 0x1F, 0x0B, 0x03, 0x00000000, PPC_POWER_BR) { - gen_op_load_gpr_T0(rA(ctx->opcode)); - gen_op_load_gpr_T1(rB(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); gen_op_POWER_mul(); gen_op_store_T0_gpr(rD(ctx->opcode)); if (unlikely(Rc(ctx->opcode) != 0)) @@ -4035,8 +4083,8 @@ GEN_HANDLER(mul, 0x1F, 0x0B, 0x03, 0x00000000, PPC_POWER_BR) /* mulo - mulo. */ GEN_HANDLER(mulo, 0x1F, 0x0B, 0x13, 0x00000000, PPC_POWER_BR) { - gen_op_load_gpr_T0(rA(ctx->opcode)); - gen_op_load_gpr_T1(rB(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); gen_op_POWER_mulo(); gen_op_store_T0_gpr(rD(ctx->opcode)); if (unlikely(Rc(ctx->opcode) != 0)) @@ -4046,7 +4094,7 @@ GEN_HANDLER(mulo, 0x1F, 0x0B, 0x13, 0x00000000, PPC_POWER_BR) /* nabs - nabs. */ GEN_HANDLER(nabs, 0x1F, 0x08, 0x0F, 0x00000000, PPC_POWER_BR) { - gen_op_load_gpr_T0(rA(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); gen_op_POWER_nabs(); gen_op_store_T0_gpr(rD(ctx->opcode)); if (unlikely(Rc(ctx->opcode) != 0)) @@ -4056,7 +4104,7 @@ GEN_HANDLER(nabs, 0x1F, 0x08, 0x0F, 0x00000000, PPC_POWER_BR) /* nabso - nabso. */ GEN_HANDLER(nabso, 0x1F, 0x08, 0x1F, 0x00000000, PPC_POWER_BR) { - gen_op_load_gpr_T0(rA(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); gen_op_POWER_nabso(); gen_op_store_T0_gpr(rD(ctx->opcode)); if (unlikely(Rc(ctx->opcode) != 0)) @@ -4070,9 +4118,9 @@ GEN_HANDLER(rlmi, 0x16, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR) mb = MB(ctx->opcode); me = ME(ctx->opcode); - gen_op_load_gpr_T0(rS(ctx->opcode)); - gen_op_load_gpr_T1(rA(ctx->opcode)); - gen_op_load_gpr_T2(rB(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rA(ctx->opcode)]); + tcg_gen_mov_tl(cpu_T[2], cpu_gpr[rB(ctx->opcode)]); gen_op_POWER_rlmi(MASK(mb, me), ~MASK(mb, me)); gen_op_store_T0_gpr(rA(ctx->opcode)); if (unlikely(Rc(ctx->opcode) != 0)) @@ -4082,9 +4130,9 @@ GEN_HANDLER(rlmi, 0x16, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR) /* rrib - rrib. */ GEN_HANDLER(rrib, 0x1F, 0x19, 0x10, 0x00000000, PPC_POWER_BR) { - gen_op_load_gpr_T0(rS(ctx->opcode)); - gen_op_load_gpr_T1(rA(ctx->opcode)); - gen_op_load_gpr_T2(rB(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rA(ctx->opcode)]); + tcg_gen_mov_tl(cpu_T[2], cpu_gpr[rB(ctx->opcode)]); gen_op_POWER_rrib(); gen_op_store_T0_gpr(rA(ctx->opcode)); if (unlikely(Rc(ctx->opcode) != 0)) @@ -4094,8 +4142,8 @@ GEN_HANDLER(rrib, 0x1F, 0x19, 0x10, 0x00000000, PPC_POWER_BR) /* sle - sle. */ GEN_HANDLER(sle, 0x1F, 0x19, 0x04, 0x00000000, PPC_POWER_BR) { - gen_op_load_gpr_T0(rS(ctx->opcode)); - gen_op_load_gpr_T1(rB(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); gen_op_POWER_sle(); gen_op_store_T0_gpr(rA(ctx->opcode)); if (unlikely(Rc(ctx->opcode) != 0)) @@ -4105,8 +4153,8 @@ GEN_HANDLER(sle, 0x1F, 0x19, 0x04, 0x00000000, PPC_POWER_BR) /* sleq - sleq. */ GEN_HANDLER(sleq, 0x1F, 0x19, 0x06, 0x00000000, PPC_POWER_BR) { - gen_op_load_gpr_T0(rS(ctx->opcode)); - gen_op_load_gpr_T1(rB(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); gen_op_POWER_sleq(); gen_op_store_T0_gpr(rA(ctx->opcode)); if (unlikely(Rc(ctx->opcode) != 0)) @@ -4116,7 +4164,7 @@ GEN_HANDLER(sleq, 0x1F, 0x19, 0x06, 0x00000000, PPC_POWER_BR) /* sliq - sliq. */ GEN_HANDLER(sliq, 0x1F, 0x18, 0x05, 0x00000000, PPC_POWER_BR) { - gen_op_load_gpr_T0(rS(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); tcg_gen_movi_tl(cpu_T[1], SH(ctx->opcode)); gen_op_POWER_sle(); gen_op_store_T0_gpr(rA(ctx->opcode)); @@ -4127,7 +4175,7 @@ GEN_HANDLER(sliq, 0x1F, 0x18, 0x05, 0x00000000, PPC_POWER_BR) /* slliq - slliq. */ GEN_HANDLER(slliq, 0x1F, 0x18, 0x07, 0x00000000, PPC_POWER_BR) { - gen_op_load_gpr_T0(rS(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); tcg_gen_movi_tl(cpu_T[1], SH(ctx->opcode)); gen_op_POWER_sleq(); gen_op_store_T0_gpr(rA(ctx->opcode)); @@ -4138,8 +4186,8 @@ GEN_HANDLER(slliq, 0x1F, 0x18, 0x07, 0x00000000, PPC_POWER_BR) /* sllq - sllq. */ GEN_HANDLER(sllq, 0x1F, 0x18, 0x06, 0x00000000, PPC_POWER_BR) { - gen_op_load_gpr_T0(rS(ctx->opcode)); - gen_op_load_gpr_T1(rB(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); gen_op_POWER_sllq(); gen_op_store_T0_gpr(rA(ctx->opcode)); if (unlikely(Rc(ctx->opcode) != 0)) @@ -4149,8 +4197,8 @@ GEN_HANDLER(sllq, 0x1F, 0x18, 0x06, 0x00000000, PPC_POWER_BR) /* slq - slq. */ GEN_HANDLER(slq, 0x1F, 0x18, 0x04, 0x00000000, PPC_POWER_BR) { - gen_op_load_gpr_T0(rS(ctx->opcode)); - gen_op_load_gpr_T1(rB(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); gen_op_POWER_slq(); gen_op_store_T0_gpr(rA(ctx->opcode)); if (unlikely(Rc(ctx->opcode) != 0)) @@ -4160,7 +4208,7 @@ GEN_HANDLER(slq, 0x1F, 0x18, 0x04, 0x00000000, PPC_POWER_BR) /* sraiq - sraiq. */ GEN_HANDLER(sraiq, 0x1F, 0x18, 0x1D, 0x00000000, PPC_POWER_BR) { - gen_op_load_gpr_T0(rS(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); tcg_gen_movi_tl(cpu_T[1], SH(ctx->opcode)); gen_op_POWER_sraq(); gen_op_store_T0_gpr(rA(ctx->opcode)); @@ -4171,8 +4219,8 @@ GEN_HANDLER(sraiq, 0x1F, 0x18, 0x1D, 0x00000000, PPC_POWER_BR) /* sraq - sraq. */ GEN_HANDLER(sraq, 0x1F, 0x18, 0x1C, 0x00000000, PPC_POWER_BR) { - gen_op_load_gpr_T0(rS(ctx->opcode)); - gen_op_load_gpr_T1(rB(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); gen_op_POWER_sraq(); gen_op_store_T0_gpr(rA(ctx->opcode)); if (unlikely(Rc(ctx->opcode) != 0)) @@ -4182,8 +4230,8 @@ GEN_HANDLER(sraq, 0x1F, 0x18, 0x1C, 0x00000000, PPC_POWER_BR) /* sre - sre. */ GEN_HANDLER(sre, 0x1F, 0x19, 0x14, 0x00000000, PPC_POWER_BR) { - gen_op_load_gpr_T0(rS(ctx->opcode)); - gen_op_load_gpr_T1(rB(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); gen_op_POWER_sre(); gen_op_store_T0_gpr(rA(ctx->opcode)); if (unlikely(Rc(ctx->opcode) != 0)) @@ -4193,8 +4241,8 @@ GEN_HANDLER(sre, 0x1F, 0x19, 0x14, 0x00000000, PPC_POWER_BR) /* srea - srea. */ GEN_HANDLER(srea, 0x1F, 0x19, 0x1C, 0x00000000, PPC_POWER_BR) { - gen_op_load_gpr_T0(rS(ctx->opcode)); - gen_op_load_gpr_T1(rB(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); gen_op_POWER_srea(); gen_op_store_T0_gpr(rA(ctx->opcode)); if (unlikely(Rc(ctx->opcode) != 0)) @@ -4204,8 +4252,8 @@ GEN_HANDLER(srea, 0x1F, 0x19, 0x1C, 0x00000000, PPC_POWER_BR) /* sreq */ GEN_HANDLER(sreq, 0x1F, 0x19, 0x16, 0x00000000, PPC_POWER_BR) { - gen_op_load_gpr_T0(rS(ctx->opcode)); - gen_op_load_gpr_T1(rB(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); gen_op_POWER_sreq(); gen_op_store_T0_gpr(rA(ctx->opcode)); if (unlikely(Rc(ctx->opcode) != 0)) @@ -4215,7 +4263,7 @@ GEN_HANDLER(sreq, 0x1F, 0x19, 0x16, 0x00000000, PPC_POWER_BR) /* sriq */ GEN_HANDLER(sriq, 0x1F, 0x18, 0x15, 0x00000000, PPC_POWER_BR) { - gen_op_load_gpr_T0(rS(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); tcg_gen_movi_tl(cpu_T[1], SH(ctx->opcode)); gen_op_POWER_srq(); gen_op_store_T0_gpr(rA(ctx->opcode)); @@ -4226,8 +4274,8 @@ GEN_HANDLER(sriq, 0x1F, 0x18, 0x15, 0x00000000, PPC_POWER_BR) /* srliq */ GEN_HANDLER(srliq, 0x1F, 0x18, 0x17, 0x00000000, PPC_POWER_BR) { - gen_op_load_gpr_T0(rS(ctx->opcode)); - gen_op_load_gpr_T1(rB(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); tcg_gen_movi_tl(cpu_T[1], SH(ctx->opcode)); gen_op_POWER_srlq(); gen_op_store_T0_gpr(rA(ctx->opcode)); @@ -4238,8 +4286,8 @@ GEN_HANDLER(srliq, 0x1F, 0x18, 0x17, 0x00000000, PPC_POWER_BR) /* srlq */ GEN_HANDLER(srlq, 0x1F, 0x18, 0x16, 0x00000000, PPC_POWER_BR) { - gen_op_load_gpr_T0(rS(ctx->opcode)); - gen_op_load_gpr_T1(rB(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); gen_op_POWER_srlq(); gen_op_store_T0_gpr(rA(ctx->opcode)); if (unlikely(Rc(ctx->opcode) != 0)) @@ -4249,8 +4297,8 @@ GEN_HANDLER(srlq, 0x1F, 0x18, 0x16, 0x00000000, PPC_POWER_BR) /* srq */ GEN_HANDLER(srq, 0x1F, 0x18, 0x14, 0x00000000, PPC_POWER_BR) { - gen_op_load_gpr_T0(rS(ctx->opcode)); - gen_op_load_gpr_T1(rB(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); gen_op_POWER_srq(); gen_op_store_T0_gpr(rA(ctx->opcode)); if (unlikely(Rc(ctx->opcode) != 0)) @@ -4282,7 +4330,7 @@ GEN_HANDLER(mfrom, 0x1F, 0x09, 0x08, 0x03E0F801, PPC_602_SPEC) GEN_EXCP_PRIVOPC(ctx); return; } - gen_op_load_gpr_T0(rA(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); gen_op_602_mfrom(); gen_op_store_T0_gpr(rD(ctx->opcode)); #endif @@ -4299,7 +4347,7 @@ GEN_HANDLER2(tlbld_6xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB) GEN_EXCP_PRIVOPC(ctx); return; } - gen_op_load_gpr_T0(rB(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rB(ctx->opcode)]); gen_op_6xx_tlbld(); #endif } @@ -4314,7 +4362,7 @@ GEN_HANDLER2(tlbli_6xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB) GEN_EXCP_PRIVOPC(ctx); return; } - gen_op_load_gpr_T0(rB(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rB(ctx->opcode)]); gen_op_6xx_tlbli(); #endif } @@ -4330,7 +4378,7 @@ GEN_HANDLER2(tlbld_74xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_74xx_TLB) GEN_EXCP_PRIVOPC(ctx); return; } - gen_op_load_gpr_T0(rB(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rB(ctx->opcode)]); gen_op_74xx_tlbld(); #endif } @@ -4345,7 +4393,7 @@ GEN_HANDLER2(tlbli_74xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_74xx_TLB) GEN_EXCP_PRIVOPC(ctx); return; } - gen_op_load_gpr_T0(rB(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rB(ctx->opcode)]); gen_op_74xx_tlbli(); #endif } @@ -4594,8 +4642,8 @@ static always_inline void gen_405_mulladd_insn (DisasContext *ctx, int opc2, int opc3, int ra, int rb, int rt, int Rc) { - gen_op_load_gpr_T0(ra); - gen_op_load_gpr_T1(rb); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[ra]); + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rb]); switch (opc3 & 0x0D) { case 0x05: /* macchw - macchw. - macchwo - macchwo. */ @@ -4646,7 +4694,7 @@ static always_inline void gen_405_mulladd_insn (DisasContext *ctx, } if (opc2 & 0x04) { /* (n)multiply-and-accumulate (0x0C - 0x0E) */ - gen_op_load_gpr_T2(rt); + tcg_gen_mov_tl(cpu_T[2], cpu_gpr[rt]); tcg_gen_mov_tl(cpu_T[1], cpu_T[0]); gen_op_405_add_T0_T2(); } @@ -4795,7 +4843,7 @@ GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR) return; } tcg_gen_movi_tl(cpu_T[0], dcrn); - gen_op_load_gpr_T1(rS(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]); gen_op_store_dcr(); #endif } @@ -4811,7 +4859,7 @@ GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX) GEN_EXCP_PRIVREG(ctx); return; } - gen_op_load_gpr_T0(rA(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); gen_op_load_dcr(); gen_op_store_T0_gpr(rD(ctx->opcode)); /* Note: Rc update flag set leads to undefined state of Rc0 */ @@ -4829,8 +4877,8 @@ GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX) GEN_EXCP_PRIVREG(ctx); return; } - gen_op_load_gpr_T0(rA(ctx->opcode)); - gen_op_load_gpr_T1(rS(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]); gen_op_store_dcr(); /* Note: Rc update flag set leads to undefined state of Rc0 */ #endif @@ -4839,7 +4887,7 @@ GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX) /* mfdcrux (PPC 460) : user-mode access to DCR */ GEN_HANDLER(mfdcrux, 0x1F, 0x03, 0x09, 0x00000000, PPC_DCRUX) { - gen_op_load_gpr_T0(rA(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); gen_op_load_dcr(); gen_op_store_T0_gpr(rD(ctx->opcode)); /* Note: Rc update flag set leads to undefined state of Rc0 */ @@ -4848,8 +4896,8 @@ GEN_HANDLER(mfdcrux, 0x1F, 0x03, 0x09, 0x00000000, PPC_DCRUX) /* mtdcrux (PPC 460) : user-mode access to DCR */ GEN_HANDLER(mtdcrux, 0x1F, 0x03, 0x0D, 0x00000000, PPC_DCRUX) { - gen_op_load_gpr_T0(rA(ctx->opcode)); - gen_op_load_gpr_T1(rS(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]); gen_op_store_dcr(); /* Note: Rc update flag set leads to undefined state of Rc0 */ } @@ -4998,12 +5046,12 @@ GEN_HANDLER2(tlbre_40x, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB) } switch (rB(ctx->opcode)) { case 0: - gen_op_load_gpr_T0(rA(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); gen_op_4xx_tlbre_hi(); gen_op_store_T0_gpr(rD(ctx->opcode)); break; case 1: - gen_op_load_gpr_T0(rA(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); gen_op_4xx_tlbre_lo(); gen_op_store_T0_gpr(rD(ctx->opcode)); break; @@ -5044,13 +5092,13 @@ GEN_HANDLER2(tlbwe_40x, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB) } switch (rB(ctx->opcode)) { case 0: - gen_op_load_gpr_T0(rA(ctx->opcode)); - gen_op_load_gpr_T1(rS(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]); gen_op_4xx_tlbwe_hi(); break; case 1: - gen_op_load_gpr_T0(rA(ctx->opcode)); - gen_op_load_gpr_T1(rS(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]); gen_op_4xx_tlbwe_lo(); break; default: @@ -5075,7 +5123,7 @@ GEN_HANDLER2(tlbre_440, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE) case 0: case 1: case 2: - gen_op_load_gpr_T0(rA(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); gen_op_440_tlbre(rB(ctx->opcode)); gen_op_store_T0_gpr(rD(ctx->opcode)); break; @@ -5118,8 +5166,8 @@ GEN_HANDLER2(tlbwe_440, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE) case 0: case 1: case 2: - gen_op_load_gpr_T0(rA(ctx->opcode)); - gen_op_load_gpr_T1(rS(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]); gen_op_440_tlbwe(rB(ctx->opcode)); break; default: @@ -5139,7 +5187,7 @@ GEN_HANDLER(wrtee, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE) GEN_EXCP_PRIVOPC(ctx); return; } - gen_op_load_gpr_T0(rD(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rD(ctx->opcode)]); gen_op_wrte(); /* Stop translation to have a chance to raise an exception * if we just set msr_ee to 1 @@ -5171,8 +5219,8 @@ GEN_HANDLER(wrteei, 0x1F, 0x03, 0x05, 0x000EFC01, PPC_WRTEE) /* dlmzb */ GEN_HANDLER(dlmzb, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC) { - gen_op_load_gpr_T0(rS(ctx->opcode)); - gen_op_load_gpr_T1(rB(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); gen_op_440_dlmzb(); gen_op_store_T0_gpr(rA(ctx->opcode)); gen_op_store_xer_bc(); @@ -5317,7 +5365,7 @@ static always_inline void gen_addr_spe_imm_index (DisasContext *ctx, int sh) if (rA(ctx->opcode) == 0) { tcg_gen_movi_tl(cpu_T[0], simm << sh); } else { - gen_op_load_gpr_T0(rA(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); if (likely(simm != 0)) gen_op_addi(simm << sh); } @@ -5465,8 +5513,8 @@ GEN_SPEOP_ARITH1(evcntlsw); static always_inline void gen_brinc (DisasContext *ctx) { /* Note: brinc is usable even if SPE is disabled */ - gen_op_load_gpr_T0(rA(ctx->opcode)); - gen_op_load_gpr_T1(rB(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); gen_op_brinc(); gen_op_store_T0_gpr(rD(ctx->opcode)); } -- 1.5.5.1 [-- Attachment #2: 0001-Convert-op_load_gpr_-T0-T1-T2-to-TCG.patch --] [-- Type: application/octet-stream, Size: 59394 bytes --] From d562e4f7f2e3916984b99bbc0369d81894e3165c Mon Sep 17 00:00:00 2001 From: =?utf-8?q?Andreas=20F=C3=A4rber?= <andreas.faerber@web.de> Date: Wed, 3 Sep 2008 00:06:41 +0200 Subject: [PATCH] ppc: Convert op_load_gpr_{T0,T1,T2} to TCG Replace op_load_gpr_T0, op_load_gpr_T1 and op_load_gpr_T2 with tcg_gen_mov_tl. To do so, TCG variables cpu_gpr[0..31] are introduced. Signed-off-by: Andreas Faerber <andreas.faerber@web.de> --- target-ppc/translate.c | 418 +++++++++++++++++++++++++++--------------------- 1 files changed, 233 insertions(+), 185 deletions(-) diff --git a/target-ppc/translate.c b/target-ppc/translate.c index 9068936..0fe119a 100644 --- a/target-ppc/translate.c +++ b/target-ppc/translate.c @@ -44,15 +44,57 @@ /*****************************************************************************/ /* Code translation helpers */ -static TCGv cpu_env, cpu_T[3]; +/* global register indexes */ +static TCGv cpu_env; +static TCGv cpu_gpr[32]; + +/* dyngen register indexes */ +static TCGv cpu_T[3]; #include "gen-icount.h" void ppc_translate_init(void) { + int i; static int done_init = 0; + static const char* const gprnames[32] = { + "r0", + "r1", + "r2", + "r3", + "r4", + "r5", + "r6", + "r7", + "r8", + "r9", + "r10", + "r11", + "r12", + "r13", + "r14", + "r15", + "r16", + "r17", + "r18", + "r19", + "r20", + "r21", + "r22", + "r23", + "r24", + "r25", + "r26", + "r27", + "r28", + "r29", + "r30", + "r31" + }; + if (done_init) return; + cpu_env = tcg_global_reg_new(TCG_TYPE_PTR, TCG_AREG0, "env"); #if TARGET_LONG_BITS > HOST_LONG_BITS cpu_T[0] = tcg_global_mem_new(TCG_TYPE_TL, @@ -67,6 +109,12 @@ void ppc_translate_init(void) cpu_T[2] = tcg_global_reg_new(TCG_TYPE_TL, TCG_AREG3, "T2"); #endif + for (i = 0; i < 32; i++) { + cpu_gpr[i] = tcg_global_mem_new(TCG_TYPE_TL, TCG_AREG0, + offsetof(CPUState, gpr[i]), + gprnames[i]); + } + /* register helpers */ #undef DEF_HELPER #define DEF_HELPER(ret, name, params) tcg_register_helper(name, #name); @@ -667,8 +715,8 @@ static opc_handler_t invalid_handler = { #define __GEN_INT_ARITH2(name, opc1, opc2, opc3, inval, type) \ GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \ { \ - gen_op_load_gpr_T0(rA(ctx->opcode)); \ - gen_op_load_gpr_T1(rB(ctx->opcode)); \ + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); \ + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); \ gen_op_##name(); \ gen_op_store_T0_gpr(rD(ctx->opcode)); \ if (unlikely(Rc(ctx->opcode) != 0)) \ @@ -678,8 +726,8 @@ GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \ #define __GEN_INT_ARITH2_O(name, opc1, opc2, opc3, inval, type) \ GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \ { \ - gen_op_load_gpr_T0(rA(ctx->opcode)); \ - gen_op_load_gpr_T1(rB(ctx->opcode)); \ + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); \ + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); \ gen_op_##name(); \ gen_op_store_T0_gpr(rD(ctx->opcode)); \ if (unlikely(Rc(ctx->opcode) != 0)) \ @@ -689,7 +737,7 @@ GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \ #define __GEN_INT_ARITH1(name, opc1, opc2, opc3, type) \ GEN_HANDLER(name, opc1, opc2, opc3, 0x0000F800, type) \ { \ - gen_op_load_gpr_T0(rA(ctx->opcode)); \ + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); \ gen_op_##name(); \ gen_op_store_T0_gpr(rD(ctx->opcode)); \ if (unlikely(Rc(ctx->opcode) != 0)) \ @@ -698,7 +746,7 @@ GEN_HANDLER(name, opc1, opc2, opc3, 0x0000F800, type) \ #define __GEN_INT_ARITH1_O(name, opc1, opc2, opc3, type) \ GEN_HANDLER(name, opc1, opc2, opc3, 0x0000F800, type) \ { \ - gen_op_load_gpr_T0(rA(ctx->opcode)); \ + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); \ gen_op_##name(); \ gen_op_store_T0_gpr(rD(ctx->opcode)); \ if (unlikely(Rc(ctx->opcode) != 0)) \ @@ -723,8 +771,8 @@ __GEN_INT_ARITH1_O(name##o, opc1, opc2, opc3 | 0x10, type) #define __GEN_INT_ARITH2_64(name, opc1, opc2, opc3, inval, type) \ GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \ { \ - gen_op_load_gpr_T0(rA(ctx->opcode)); \ - gen_op_load_gpr_T1(rB(ctx->opcode)); \ + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); \ + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); \ if (ctx->sf_mode) \ gen_op_##name##_64(); \ else \ @@ -737,8 +785,8 @@ GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \ #define __GEN_INT_ARITH2_O_64(name, opc1, opc2, opc3, inval, type) \ GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \ { \ - gen_op_load_gpr_T0(rA(ctx->opcode)); \ - gen_op_load_gpr_T1(rB(ctx->opcode)); \ + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); \ + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); \ if (ctx->sf_mode) \ gen_op_##name##_64(); \ else \ @@ -751,7 +799,7 @@ GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \ #define __GEN_INT_ARITH1_64(name, opc1, opc2, opc3, type) \ GEN_HANDLER(name, opc1, opc2, opc3, 0x0000F800, type) \ { \ - gen_op_load_gpr_T0(rA(ctx->opcode)); \ + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); \ if (ctx->sf_mode) \ gen_op_##name##_64(); \ else \ @@ -763,7 +811,7 @@ GEN_HANDLER(name, opc1, opc2, opc3, 0x0000F800, type) \ #define __GEN_INT_ARITH1_O_64(name, opc1, opc2, opc3, type) \ GEN_HANDLER(name, opc1, opc2, opc3, 0x0000F800, type) \ { \ - gen_op_load_gpr_T0(rA(ctx->opcode)); \ + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); \ if (ctx->sf_mode) \ gen_op_##name##_64(); \ else \ @@ -986,7 +1034,7 @@ GEN_HANDLER(addi, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) /* li case */ tcg_gen_movi_tl(cpu_T[0], simm); } else { - gen_op_load_gpr_T0(rA(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); if (likely(simm != 0)) gen_op_addi(simm); } @@ -997,7 +1045,7 @@ GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) { target_long simm = SIMM(ctx->opcode); - gen_op_load_gpr_T0(rA(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); if (likely(simm != 0)) { tcg_gen_mov_tl(cpu_T[2], cpu_T[0]); gen_op_addi(simm); @@ -1017,7 +1065,7 @@ GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) { target_long simm = SIMM(ctx->opcode); - gen_op_load_gpr_T0(rA(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); if (likely(simm != 0)) { tcg_gen_mov_tl(cpu_T[2], cpu_T[0]); gen_op_addi(simm); @@ -1042,7 +1090,7 @@ GEN_HANDLER(addis, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) /* lis case */ tcg_gen_movi_tl(cpu_T[0], simm << 16); } else { - gen_op_load_gpr_T0(rA(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); if (likely(simm != 0)) gen_op_addi(simm << 16); } @@ -1051,14 +1099,14 @@ GEN_HANDLER(addis, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) /* mulli */ GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) { - gen_op_load_gpr_T0(rA(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); gen_op_mulli(SIMM(ctx->opcode)); gen_op_store_T0_gpr(rD(ctx->opcode)); } /* subfic */ GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) { - gen_op_load_gpr_T0(rA(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); #if defined(TARGET_PPC64) if (ctx->sf_mode) gen_op_subfic_64(SIMM(ctx->opcode)); @@ -1086,8 +1134,8 @@ GEN_INT_ARITH2 (divdu, 0x1F, 0x09, 0x0E, PPC_64B); #define GEN_CMP(name, opc, type) \ GEN_HANDLER(name, 0x1F, 0x00, opc, 0x00400000, type) \ { \ - gen_op_load_gpr_T0(rA(ctx->opcode)); \ - gen_op_load_gpr_T1(rB(ctx->opcode)); \ + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); \ + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); \ if (ctx->sf_mode && (ctx->opcode & 0x00200000)) \ gen_op_##name##_64(); \ else \ @@ -1098,8 +1146,8 @@ GEN_HANDLER(name, 0x1F, 0x00, opc, 0x00400000, type) \ #define GEN_CMP(name, opc, type) \ GEN_HANDLER(name, 0x1F, 0x00, opc, 0x00400000, type) \ { \ - gen_op_load_gpr_T0(rA(ctx->opcode)); \ - gen_op_load_gpr_T1(rB(ctx->opcode)); \ + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); \ + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); \ gen_op_##name(); \ gen_op_store_T0_crf(crfD(ctx->opcode)); \ } @@ -1110,7 +1158,7 @@ GEN_CMP(cmp, 0x00, PPC_INTEGER); /* cmpi */ GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER) { - gen_op_load_gpr_T0(rA(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); #if defined(TARGET_PPC64) if (ctx->sf_mode && (ctx->opcode & 0x00200000)) gen_op_cmpi_64(SIMM(ctx->opcode)); @@ -1124,7 +1172,7 @@ GEN_CMP(cmpl, 0x01, PPC_INTEGER); /* cmpli */ GEN_HANDLER(cmpli, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER) { - gen_op_load_gpr_T0(rA(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); #if defined(TARGET_PPC64) if (ctx->sf_mode && (ctx->opcode & 0x00200000)) gen_op_cmpli_64(UIMM(ctx->opcode)); @@ -1143,9 +1191,9 @@ GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL) if (rA(ctx->opcode) == 0) { tcg_gen_movi_tl(cpu_T[0], 0); } else { - gen_op_load_gpr_T1(rA(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rA(ctx->opcode)]); } - gen_op_load_gpr_T2(rB(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[2], cpu_gpr[rB(ctx->opcode)]); mask = 1 << (3 - (bi & 0x03)); gen_op_load_crf_T0(bi >> 2); gen_op_test_true(mask); @@ -1157,8 +1205,8 @@ GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL) #define __GEN_LOGICAL2(name, opc2, opc3, type) \ GEN_HANDLER(name, 0x1F, opc2, opc3, 0x00000000, type) \ { \ - gen_op_load_gpr_T0(rS(ctx->opcode)); \ - gen_op_load_gpr_T1(rB(ctx->opcode)); \ + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); \ + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); \ gen_op_##name(); \ gen_op_store_T0_gpr(rA(ctx->opcode)); \ if (unlikely(Rc(ctx->opcode) != 0)) \ @@ -1170,7 +1218,7 @@ __GEN_LOGICAL2(name, 0x1C, opc, type) #define GEN_LOGICAL1(name, opc, type) \ GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type) \ { \ - gen_op_load_gpr_T0(rS(ctx->opcode)); \ + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); \ gen_op_##name(); \ gen_op_store_T0_gpr(rA(ctx->opcode)); \ if (unlikely(Rc(ctx->opcode) != 0)) \ @@ -1184,7 +1232,7 @@ GEN_LOGICAL2(andc, 0x01, PPC_INTEGER); /* andi. */ GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) { - gen_op_load_gpr_T0(rS(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); gen_op_andi_T0(UIMM(ctx->opcode)); gen_op_store_T0_gpr(rA(ctx->opcode)); gen_set_Rc0(ctx); @@ -1192,7 +1240,7 @@ GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) /* andis. */ GEN_HANDLER2(andis_, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) { - gen_op_load_gpr_T0(rS(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); gen_op_andi_T0(UIMM(ctx->opcode) << 16); gen_op_store_T0_gpr(rA(ctx->opcode)); gen_set_Rc0(ctx); @@ -1221,16 +1269,16 @@ GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER) rb = rB(ctx->opcode); /* Optimisation for mr. ri case */ if (rs != ra || rs != rb) { - gen_op_load_gpr_T0(rs); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rs]); if (rs != rb) { - gen_op_load_gpr_T1(rb); + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rb]); gen_op_or(); } gen_op_store_T0_gpr(ra); if (unlikely(Rc(ctx->opcode) != 0)) gen_set_Rc0(ctx); } else if (unlikely(Rc(ctx->opcode) != 0)) { - gen_op_load_gpr_T0(rs); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rs]); gen_set_Rc0(ctx); #if defined(TARGET_PPC64) } else { @@ -1286,10 +1334,10 @@ GEN_LOGICAL2(orc, 0x0C, PPC_INTEGER); /* xor & xor. */ GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER) { - gen_op_load_gpr_T0(rS(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); /* Optimisation for "set to zero" case */ if (rS(ctx->opcode) != rB(ctx->opcode)) { - gen_op_load_gpr_T1(rB(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); gen_op_xor(); } else { tcg_gen_movi_tl(cpu_T[0], 0); @@ -1308,7 +1356,7 @@ GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) /* XXX: should handle special NOPs for POWER series */ return; } - gen_op_load_gpr_T0(rS(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); if (likely(uimm != 0)) gen_op_ori(uimm); gen_op_store_T0_gpr(rA(ctx->opcode)); @@ -1322,7 +1370,7 @@ GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) /* NOP */ return; } - gen_op_load_gpr_T0(rS(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); if (likely(uimm != 0)) gen_op_ori(uimm << 16); gen_op_store_T0_gpr(rA(ctx->opcode)); @@ -1336,7 +1384,7 @@ GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) /* NOP */ return; } - gen_op_load_gpr_T0(rS(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); if (likely(uimm != 0)) gen_op_xori(uimm); gen_op_store_T0_gpr(rA(ctx->opcode)); @@ -1351,7 +1399,7 @@ GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) /* NOP */ return; } - gen_op_load_gpr_T0(rS(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); if (likely(uimm != 0)) gen_op_xori(uimm << 16); gen_op_store_T0_gpr(rA(ctx->opcode)); @@ -1360,7 +1408,7 @@ GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) /* popcntb : PowerPC 2.03 specification */ GEN_HANDLER(popcntb, 0x1F, 0x03, 0x03, 0x0000F801, PPC_POPCNTB) { - gen_op_load_gpr_T0(rS(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); #if defined(TARGET_PPC64) if (ctx->sf_mode) gen_op_popcntb_64(); @@ -1389,18 +1437,18 @@ GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) sh = SH(ctx->opcode); if (likely(sh == 0)) { if (likely(mb == 0 && me == 31)) { - gen_op_load_gpr_T0(rS(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); goto do_store; } else if (likely(mb == 31 && me == 0)) { - gen_op_load_gpr_T0(rA(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); goto do_store; } - gen_op_load_gpr_T0(rS(ctx->opcode)); - gen_op_load_gpr_T1(rA(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rA(ctx->opcode)]); goto do_mask; } - gen_op_load_gpr_T0(rS(ctx->opcode)); - gen_op_load_gpr_T1(rA(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rA(ctx->opcode)]); gen_op_rotli32_T0(SH(ctx->opcode)); do_mask: #if defined(TARGET_PPC64) @@ -1424,7 +1472,7 @@ GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) sh = SH(ctx->opcode); mb = MB(ctx->opcode); me = ME(ctx->opcode); - gen_op_load_gpr_T0(rS(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); if (likely(sh == 0)) { goto do_mask; } @@ -1461,8 +1509,8 @@ GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) mb = MB(ctx->opcode); me = ME(ctx->opcode); - gen_op_load_gpr_T0(rS(ctx->opcode)); - gen_op_load_gpr_T1(rB(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); gen_op_rotl32_T0_T1(); if (unlikely(mb != 0 || me != 31)) { #if defined(TARGET_PPC64) @@ -1527,7 +1575,7 @@ static always_inline void gen_andi_T1_64 (DisasContext *ctx, uint64_t mask) static always_inline void gen_rldinm (DisasContext *ctx, uint32_t mb, uint32_t me, uint32_t sh) { - gen_op_load_gpr_T0(rS(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); if (likely(sh == 0)) { goto do_mask; } @@ -1587,8 +1635,8 @@ GEN_PPC64_R4(rldic, 0x1E, 0x04); static always_inline void gen_rldnm (DisasContext *ctx, uint32_t mb, uint32_t me) { - gen_op_load_gpr_T0(rS(ctx->opcode)); - gen_op_load_gpr_T1(rB(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); gen_op_rotl64_T0_T1(); if (unlikely(mb != 0 || me != 63)) { gen_andi_T0_64(ctx, MASK(mb, me)); @@ -1627,15 +1675,15 @@ static always_inline void gen_rldimi (DisasContext *ctx, int mbn, int shn) me = 63 - sh; if (likely(sh == 0)) { if (likely(mb == 0)) { - gen_op_load_gpr_T0(rS(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); goto do_store; } - gen_op_load_gpr_T0(rS(ctx->opcode)); - gen_op_load_gpr_T1(rA(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rA(ctx->opcode)]); goto do_mask; } - gen_op_load_gpr_T0(rS(ctx->opcode)); - gen_op_load_gpr_T1(rA(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rA(ctx->opcode)]); gen_op_rotli64_T0(sh); do_mask: mask = MASK(mb, me); @@ -1659,7 +1707,7 @@ __GEN_LOGICAL2(sraw, 0x18, 0x18, PPC_INTEGER); GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER) { int mb, me; - gen_op_load_gpr_T0(rS(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); if (SH(ctx->opcode) != 0) { tcg_gen_mov_tl(cpu_T[1], cpu_T[0]); mb = 32 - SH(ctx->opcode); @@ -1688,7 +1736,7 @@ static always_inline void gen_sradi (DisasContext *ctx, int n) uint64_t mask; int sh, mb, me; - gen_op_load_gpr_T0(rS(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); sh = SH(ctx->opcode) + (n << 5); if (sh != 0) { tcg_gen_mov_tl(cpu_T[1], cpu_T[0]); @@ -2082,7 +2130,7 @@ static always_inline void gen_addr_imm_index (DisasContext *ctx, if (rA(ctx->opcode) == 0) { tcg_gen_movi_tl(cpu_T[0], simm); } else { - gen_op_load_gpr_T0(rA(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); if (likely(simm != 0)) gen_op_addi(simm); } @@ -2094,10 +2142,10 @@ static always_inline void gen_addr_imm_index (DisasContext *ctx, static always_inline void gen_addr_reg_index (DisasContext *ctx) { if (rA(ctx->opcode) == 0) { - gen_op_load_gpr_T0(rB(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rB(ctx->opcode)]); } else { - gen_op_load_gpr_T0(rA(ctx->opcode)); - gen_op_load_gpr_T1(rB(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); gen_op_add(); } #ifdef DEBUG_MEMORY_ACCESSES @@ -2110,7 +2158,7 @@ static always_inline void gen_addr_register (DisasContext *ctx) if (rA(ctx->opcode) == 0) { tcg_gen_movi_tl(cpu_T[0], 0); } else { - gen_op_load_gpr_T0(rA(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); } #ifdef DEBUG_MEMORY_ACCESSES gen_op_print_mem_EA(); @@ -2309,7 +2357,7 @@ GEN_HANDLER(lq, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX) GEN_HANDLER(st##width, opc, 0xFF, 0xFF, 0x00000000, type) \ { \ gen_addr_imm_index(ctx, 0); \ - gen_op_load_gpr_T1(rS(ctx->opcode)); \ + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]); \ op_ldst(st##width); \ } @@ -2324,7 +2372,7 @@ GEN_HANDLER(st##width##u, opc, 0xFF, 0xFF, 0x00000000, type) \ gen_addr_imm_index(ctx, 0x03); \ else \ gen_addr_imm_index(ctx, 0); \ - gen_op_load_gpr_T1(rS(ctx->opcode)); \ + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]); \ op_ldst(st##width); \ gen_op_store_T0_gpr(rA(ctx->opcode)); \ } @@ -2337,7 +2385,7 @@ GEN_HANDLER(st##width##ux, 0x1F, opc2, opc3, 0x00000001, type) \ return; \ } \ gen_addr_reg_index(ctx); \ - gen_op_load_gpr_T1(rS(ctx->opcode)); \ + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]); \ op_ldst(st##width); \ gen_op_store_T0_gpr(rA(ctx->opcode)); \ } @@ -2346,7 +2394,7 @@ GEN_HANDLER(st##width##ux, 0x1F, opc2, opc3, 0x00000001, type) \ GEN_HANDLER(st##width##x, 0x1F, opc2, opc3, 0x00000001, type) \ { \ gen_addr_reg_index(ctx); \ - gen_op_load_gpr_T1(rS(ctx->opcode)); \ + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]); \ op_ldst(st##width); \ } @@ -2391,10 +2439,10 @@ GEN_HANDLER(std, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B) return; } gen_addr_imm_index(ctx, 0x03); - gen_op_load_gpr_T1(rs); + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rs]); op_ldst(std); gen_op_addi(8); - gen_op_load_gpr_T1(rs + 1); + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rs + 1]); op_ldst(std); #endif } else { @@ -2406,7 +2454,7 @@ GEN_HANDLER(std, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B) } } gen_addr_imm_index(ctx, 0x03); - gen_op_load_gpr_T1(rs); + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rs]); op_ldst(std); if (Rc(ctx->opcode)) gen_op_store_T0_gpr(rA(ctx->opcode)); @@ -2599,7 +2647,7 @@ GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES) /* NIP cannot be restored if the memory exception comes from an helper */ gen_update_nip(ctx, ctx->nip - 4); gen_addr_reg_index(ctx); - gen_op_load_gpr_T1(rS(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]); op_stwcx(); } @@ -2629,7 +2677,7 @@ GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B) /* NIP cannot be restored if the memory exception comes from an helper */ gen_update_nip(ctx, ctx->nip - 4); gen_addr_reg_index(ctx); - gen_op_load_gpr_T1(rS(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]); op_stdcx(); } #endif /* defined(TARGET_PPC64) */ @@ -3154,8 +3202,8 @@ GEN_HANDLER(sc, 0x11, 0xFF, 0xFF, 0x03FFF01D, PPC_FLOW) /* tw */ GEN_HANDLER(tw, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW) { - gen_op_load_gpr_T0(rA(ctx->opcode)); - gen_op_load_gpr_T1(rB(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); /* Update the nip since this might generate a trap exception */ gen_update_nip(ctx, ctx->nip); gen_op_tw(TO(ctx->opcode)); @@ -3164,7 +3212,7 @@ GEN_HANDLER(tw, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW) /* twi */ GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW) { - gen_op_load_gpr_T0(rA(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); tcg_gen_movi_tl(cpu_T[1], SIMM(ctx->opcode)); /* Update the nip since this might generate a trap exception */ gen_update_nip(ctx, ctx->nip); @@ -3175,8 +3223,8 @@ GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW) /* td */ GEN_HANDLER(td, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B) { - gen_op_load_gpr_T0(rA(ctx->opcode)); - gen_op_load_gpr_T1(rB(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); /* Update the nip since this might generate a trap exception */ gen_update_nip(ctx, ctx->nip); gen_op_td(TO(ctx->opcode)); @@ -3185,7 +3233,7 @@ GEN_HANDLER(td, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B) /* tdi */ GEN_HANDLER(tdi, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B) { - gen_op_load_gpr_T0(rA(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); tcg_gen_movi_tl(cpu_T[1], SIMM(ctx->opcode)); /* Update the nip since this might generate a trap exception */ gen_update_nip(ctx, ctx->nip); @@ -3309,7 +3357,7 @@ GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC) { uint32_t crm, crn; - gen_op_load_gpr_T0(rS(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); crm = CRM(ctx->opcode); if (likely((ctx->opcode & 0x00100000) || (crm ^ (crm - 1)) == 0)) { crn = ffs(crm); @@ -3332,7 +3380,7 @@ GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B) GEN_EXCP_PRIVREG(ctx); return; } - gen_op_load_gpr_T0(rS(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); if (ctx->opcode & 0x00010000) { /* Special form that does not need any synchronisation */ gen_op_update_riee(); @@ -3360,7 +3408,7 @@ GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001FF801, PPC_MISC) GEN_EXCP_PRIVREG(ctx); return; } - gen_op_load_gpr_T0(rS(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); if (ctx->opcode & 0x00010000) { /* Special form that does not need any synchronisation */ gen_op_update_riee(); @@ -3399,7 +3447,7 @@ GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000001, PPC_MISC) write_cb = ctx->spr_cb[sprn].uea_write; if (likely(write_cb != NULL)) { if (likely(write_cb != SPR_NOACCESS)) { - gen_op_load_gpr_T0(rS(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); (*write_cb)(ctx, sprn); } else { /* Privilege exception */ @@ -3628,7 +3676,7 @@ GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT) GEN_EXCP_PRIVREG(ctx); return; } - gen_op_load_gpr_T1(rB(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); gen_op_srli_T1(28); gen_op_load_sr(); gen_op_store_T0_gpr(rD(ctx->opcode)); @@ -3645,7 +3693,7 @@ GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT) GEN_EXCP_PRIVREG(ctx); return; } - gen_op_load_gpr_T0(rS(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); tcg_gen_movi_tl(cpu_T[1], SR(ctx->opcode)); gen_op_store_sr(); #endif @@ -3661,8 +3709,8 @@ GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT) GEN_EXCP_PRIVREG(ctx); return; } - gen_op_load_gpr_T0(rS(ctx->opcode)); - gen_op_load_gpr_T1(rB(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); gen_op_srli_T1(28); gen_op_store_sr(); #endif @@ -3697,7 +3745,7 @@ GEN_HANDLER2(mfsrin_64b, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001, GEN_EXCP_PRIVREG(ctx); return; } - gen_op_load_gpr_T1(rB(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); gen_op_srli_T1(28); gen_op_load_slb(); gen_op_store_T0_gpr(rD(ctx->opcode)); @@ -3714,7 +3762,7 @@ GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B) GEN_EXCP_PRIVREG(ctx); return; } - gen_op_load_gpr_T0(rS(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); tcg_gen_movi_tl(cpu_T[1], SR(ctx->opcode)); gen_op_store_slb(); #endif @@ -3731,8 +3779,8 @@ GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001, GEN_EXCP_PRIVREG(ctx); return; } - gen_op_load_gpr_T0(rS(ctx->opcode)); - gen_op_load_gpr_T1(rB(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); gen_op_srli_T1(28); gen_op_store_slb(); #endif @@ -3765,7 +3813,7 @@ GEN_HANDLER(tlbie, 0x1F, 0x12, 0x09, 0x03FF0001, PPC_MEM_TLBIE) GEN_EXCP_PRIVOPC(ctx); return; } - gen_op_load_gpr_T0(rB(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rB(ctx->opcode)]); #if defined(TARGET_PPC64) if (ctx->sf_mode) gen_op_tlbie_64(); @@ -3817,7 +3865,7 @@ GEN_HANDLER(slbie, 0x1F, 0x12, 0x0D, 0x03FF0001, PPC_SLBI) GEN_EXCP_PRIVOPC(ctx); return; } - gen_op_load_gpr_T0(rB(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rB(ctx->opcode)]); gen_op_slbie(); #endif } @@ -3848,7 +3896,7 @@ GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN) { /* Should check EAR[E] & alignment ! */ gen_addr_reg_index(ctx); - gen_op_load_gpr_T1(rS(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]); op_ecowx(); } @@ -3856,7 +3904,7 @@ GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN) /* abs - abs. */ GEN_HANDLER(abs, 0x1F, 0x08, 0x0B, 0x0000F800, PPC_POWER_BR) { - gen_op_load_gpr_T0(rA(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); gen_op_POWER_abs(); gen_op_store_T0_gpr(rD(ctx->opcode)); if (unlikely(Rc(ctx->opcode) != 0)) @@ -3866,7 +3914,7 @@ GEN_HANDLER(abs, 0x1F, 0x08, 0x0B, 0x0000F800, PPC_POWER_BR) /* abso - abso. */ GEN_HANDLER(abso, 0x1F, 0x08, 0x1B, 0x0000F800, PPC_POWER_BR) { - gen_op_load_gpr_T0(rA(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); gen_op_POWER_abso(); gen_op_store_T0_gpr(rD(ctx->opcode)); if (unlikely(Rc(ctx->opcode) != 0)) @@ -3876,7 +3924,7 @@ GEN_HANDLER(abso, 0x1F, 0x08, 0x1B, 0x0000F800, PPC_POWER_BR) /* clcs */ GEN_HANDLER(clcs, 0x1F, 0x10, 0x13, 0x0000F800, PPC_POWER_BR) { - gen_op_load_gpr_T0(rA(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); gen_op_POWER_clcs(); /* Rc=1 sets CR0 to an undefined state */ gen_op_store_T0_gpr(rD(ctx->opcode)); @@ -3885,8 +3933,8 @@ GEN_HANDLER(clcs, 0x1F, 0x10, 0x13, 0x0000F800, PPC_POWER_BR) /* div - div. */ GEN_HANDLER(div, 0x1F, 0x0B, 0x0A, 0x00000000, PPC_POWER_BR) { - gen_op_load_gpr_T0(rA(ctx->opcode)); - gen_op_load_gpr_T1(rB(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); gen_op_POWER_div(); gen_op_store_T0_gpr(rD(ctx->opcode)); if (unlikely(Rc(ctx->opcode) != 0)) @@ -3896,8 +3944,8 @@ GEN_HANDLER(div, 0x1F, 0x0B, 0x0A, 0x00000000, PPC_POWER_BR) /* divo - divo. */ GEN_HANDLER(divo, 0x1F, 0x0B, 0x1A, 0x00000000, PPC_POWER_BR) { - gen_op_load_gpr_T0(rA(ctx->opcode)); - gen_op_load_gpr_T1(rB(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); gen_op_POWER_divo(); gen_op_store_T0_gpr(rD(ctx->opcode)); if (unlikely(Rc(ctx->opcode) != 0)) @@ -3907,8 +3955,8 @@ GEN_HANDLER(divo, 0x1F, 0x0B, 0x1A, 0x00000000, PPC_POWER_BR) /* divs - divs. */ GEN_HANDLER(divs, 0x1F, 0x0B, 0x0B, 0x00000000, PPC_POWER_BR) { - gen_op_load_gpr_T0(rA(ctx->opcode)); - gen_op_load_gpr_T1(rB(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); gen_op_POWER_divs(); gen_op_store_T0_gpr(rD(ctx->opcode)); if (unlikely(Rc(ctx->opcode) != 0)) @@ -3918,8 +3966,8 @@ GEN_HANDLER(divs, 0x1F, 0x0B, 0x0B, 0x00000000, PPC_POWER_BR) /* divso - divso. */ GEN_HANDLER(divso, 0x1F, 0x0B, 0x1B, 0x00000000, PPC_POWER_BR) { - gen_op_load_gpr_T0(rA(ctx->opcode)); - gen_op_load_gpr_T1(rB(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); gen_op_POWER_divso(); gen_op_store_T0_gpr(rD(ctx->opcode)); if (unlikely(Rc(ctx->opcode) != 0)) @@ -3929,8 +3977,8 @@ GEN_HANDLER(divso, 0x1F, 0x0B, 0x1B, 0x00000000, PPC_POWER_BR) /* doz - doz. */ GEN_HANDLER(doz, 0x1F, 0x08, 0x08, 0x00000000, PPC_POWER_BR) { - gen_op_load_gpr_T0(rA(ctx->opcode)); - gen_op_load_gpr_T1(rB(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); gen_op_POWER_doz(); gen_op_store_T0_gpr(rD(ctx->opcode)); if (unlikely(Rc(ctx->opcode) != 0)) @@ -3940,8 +3988,8 @@ GEN_HANDLER(doz, 0x1F, 0x08, 0x08, 0x00000000, PPC_POWER_BR) /* dozo - dozo. */ GEN_HANDLER(dozo, 0x1F, 0x08, 0x18, 0x00000000, PPC_POWER_BR) { - gen_op_load_gpr_T0(rA(ctx->opcode)); - gen_op_load_gpr_T1(rB(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); gen_op_POWER_dozo(); gen_op_store_T0_gpr(rD(ctx->opcode)); if (unlikely(Rc(ctx->opcode) != 0)) @@ -3951,7 +3999,7 @@ GEN_HANDLER(dozo, 0x1F, 0x08, 0x18, 0x00000000, PPC_POWER_BR) /* dozi */ GEN_HANDLER(dozi, 0x09, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR) { - gen_op_load_gpr_T0(rA(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); tcg_gen_movi_tl(cpu_T[1], SIMM(ctx->opcode)); gen_op_POWER_doz(); gen_op_store_T0_gpr(rD(ctx->opcode)); @@ -4001,8 +4049,8 @@ GEN_HANDLER(lscbx, 0x1F, 0x15, 0x08, 0x00000000, PPC_POWER_BR) /* maskg - maskg. */ GEN_HANDLER(maskg, 0x1F, 0x1D, 0x00, 0x00000000, PPC_POWER_BR) { - gen_op_load_gpr_T0(rS(ctx->opcode)); - gen_op_load_gpr_T1(rB(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); gen_op_POWER_maskg(); gen_op_store_T0_gpr(rA(ctx->opcode)); if (unlikely(Rc(ctx->opcode) != 0)) @@ -4012,9 +4060,9 @@ GEN_HANDLER(maskg, 0x1F, 0x1D, 0x00, 0x00000000, PPC_POWER_BR) /* maskir - maskir. */ GEN_HANDLER(maskir, 0x1F, 0x1D, 0x10, 0x00000000, PPC_POWER_BR) { - gen_op_load_gpr_T0(rA(ctx->opcode)); - gen_op_load_gpr_T1(rS(ctx->opcode)); - gen_op_load_gpr_T2(rB(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]); + tcg_gen_mov_tl(cpu_T[2], cpu_gpr[rB(ctx->opcode)]); gen_op_POWER_maskir(); gen_op_store_T0_gpr(rA(ctx->opcode)); if (unlikely(Rc(ctx->opcode) != 0)) @@ -4024,8 +4072,8 @@ GEN_HANDLER(maskir, 0x1F, 0x1D, 0x10, 0x00000000, PPC_POWER_BR) /* mul - mul. */ GEN_HANDLER(mul, 0x1F, 0x0B, 0x03, 0x00000000, PPC_POWER_BR) { - gen_op_load_gpr_T0(rA(ctx->opcode)); - gen_op_load_gpr_T1(rB(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); gen_op_POWER_mul(); gen_op_store_T0_gpr(rD(ctx->opcode)); if (unlikely(Rc(ctx->opcode) != 0)) @@ -4035,8 +4083,8 @@ GEN_HANDLER(mul, 0x1F, 0x0B, 0x03, 0x00000000, PPC_POWER_BR) /* mulo - mulo. */ GEN_HANDLER(mulo, 0x1F, 0x0B, 0x13, 0x00000000, PPC_POWER_BR) { - gen_op_load_gpr_T0(rA(ctx->opcode)); - gen_op_load_gpr_T1(rB(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); gen_op_POWER_mulo(); gen_op_store_T0_gpr(rD(ctx->opcode)); if (unlikely(Rc(ctx->opcode) != 0)) @@ -4046,7 +4094,7 @@ GEN_HANDLER(mulo, 0x1F, 0x0B, 0x13, 0x00000000, PPC_POWER_BR) /* nabs - nabs. */ GEN_HANDLER(nabs, 0x1F, 0x08, 0x0F, 0x00000000, PPC_POWER_BR) { - gen_op_load_gpr_T0(rA(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); gen_op_POWER_nabs(); gen_op_store_T0_gpr(rD(ctx->opcode)); if (unlikely(Rc(ctx->opcode) != 0)) @@ -4056,7 +4104,7 @@ GEN_HANDLER(nabs, 0x1F, 0x08, 0x0F, 0x00000000, PPC_POWER_BR) /* nabso - nabso. */ GEN_HANDLER(nabso, 0x1F, 0x08, 0x1F, 0x00000000, PPC_POWER_BR) { - gen_op_load_gpr_T0(rA(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); gen_op_POWER_nabso(); gen_op_store_T0_gpr(rD(ctx->opcode)); if (unlikely(Rc(ctx->opcode) != 0)) @@ -4070,9 +4118,9 @@ GEN_HANDLER(rlmi, 0x16, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR) mb = MB(ctx->opcode); me = ME(ctx->opcode); - gen_op_load_gpr_T0(rS(ctx->opcode)); - gen_op_load_gpr_T1(rA(ctx->opcode)); - gen_op_load_gpr_T2(rB(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rA(ctx->opcode)]); + tcg_gen_mov_tl(cpu_T[2], cpu_gpr[rB(ctx->opcode)]); gen_op_POWER_rlmi(MASK(mb, me), ~MASK(mb, me)); gen_op_store_T0_gpr(rA(ctx->opcode)); if (unlikely(Rc(ctx->opcode) != 0)) @@ -4082,9 +4130,9 @@ GEN_HANDLER(rlmi, 0x16, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR) /* rrib - rrib. */ GEN_HANDLER(rrib, 0x1F, 0x19, 0x10, 0x00000000, PPC_POWER_BR) { - gen_op_load_gpr_T0(rS(ctx->opcode)); - gen_op_load_gpr_T1(rA(ctx->opcode)); - gen_op_load_gpr_T2(rB(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rA(ctx->opcode)]); + tcg_gen_mov_tl(cpu_T[2], cpu_gpr[rB(ctx->opcode)]); gen_op_POWER_rrib(); gen_op_store_T0_gpr(rA(ctx->opcode)); if (unlikely(Rc(ctx->opcode) != 0)) @@ -4094,8 +4142,8 @@ GEN_HANDLER(rrib, 0x1F, 0x19, 0x10, 0x00000000, PPC_POWER_BR) /* sle - sle. */ GEN_HANDLER(sle, 0x1F, 0x19, 0x04, 0x00000000, PPC_POWER_BR) { - gen_op_load_gpr_T0(rS(ctx->opcode)); - gen_op_load_gpr_T1(rB(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); gen_op_POWER_sle(); gen_op_store_T0_gpr(rA(ctx->opcode)); if (unlikely(Rc(ctx->opcode) != 0)) @@ -4105,8 +4153,8 @@ GEN_HANDLER(sle, 0x1F, 0x19, 0x04, 0x00000000, PPC_POWER_BR) /* sleq - sleq. */ GEN_HANDLER(sleq, 0x1F, 0x19, 0x06, 0x00000000, PPC_POWER_BR) { - gen_op_load_gpr_T0(rS(ctx->opcode)); - gen_op_load_gpr_T1(rB(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); gen_op_POWER_sleq(); gen_op_store_T0_gpr(rA(ctx->opcode)); if (unlikely(Rc(ctx->opcode) != 0)) @@ -4116,7 +4164,7 @@ GEN_HANDLER(sleq, 0x1F, 0x19, 0x06, 0x00000000, PPC_POWER_BR) /* sliq - sliq. */ GEN_HANDLER(sliq, 0x1F, 0x18, 0x05, 0x00000000, PPC_POWER_BR) { - gen_op_load_gpr_T0(rS(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); tcg_gen_movi_tl(cpu_T[1], SH(ctx->opcode)); gen_op_POWER_sle(); gen_op_store_T0_gpr(rA(ctx->opcode)); @@ -4127,7 +4175,7 @@ GEN_HANDLER(sliq, 0x1F, 0x18, 0x05, 0x00000000, PPC_POWER_BR) /* slliq - slliq. */ GEN_HANDLER(slliq, 0x1F, 0x18, 0x07, 0x00000000, PPC_POWER_BR) { - gen_op_load_gpr_T0(rS(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); tcg_gen_movi_tl(cpu_T[1], SH(ctx->opcode)); gen_op_POWER_sleq(); gen_op_store_T0_gpr(rA(ctx->opcode)); @@ -4138,8 +4186,8 @@ GEN_HANDLER(slliq, 0x1F, 0x18, 0x07, 0x00000000, PPC_POWER_BR) /* sllq - sllq. */ GEN_HANDLER(sllq, 0x1F, 0x18, 0x06, 0x00000000, PPC_POWER_BR) { - gen_op_load_gpr_T0(rS(ctx->opcode)); - gen_op_load_gpr_T1(rB(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); gen_op_POWER_sllq(); gen_op_store_T0_gpr(rA(ctx->opcode)); if (unlikely(Rc(ctx->opcode) != 0)) @@ -4149,8 +4197,8 @@ GEN_HANDLER(sllq, 0x1F, 0x18, 0x06, 0x00000000, PPC_POWER_BR) /* slq - slq. */ GEN_HANDLER(slq, 0x1F, 0x18, 0x04, 0x00000000, PPC_POWER_BR) { - gen_op_load_gpr_T0(rS(ctx->opcode)); - gen_op_load_gpr_T1(rB(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); gen_op_POWER_slq(); gen_op_store_T0_gpr(rA(ctx->opcode)); if (unlikely(Rc(ctx->opcode) != 0)) @@ -4160,7 +4208,7 @@ GEN_HANDLER(slq, 0x1F, 0x18, 0x04, 0x00000000, PPC_POWER_BR) /* sraiq - sraiq. */ GEN_HANDLER(sraiq, 0x1F, 0x18, 0x1D, 0x00000000, PPC_POWER_BR) { - gen_op_load_gpr_T0(rS(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); tcg_gen_movi_tl(cpu_T[1], SH(ctx->opcode)); gen_op_POWER_sraq(); gen_op_store_T0_gpr(rA(ctx->opcode)); @@ -4171,8 +4219,8 @@ GEN_HANDLER(sraiq, 0x1F, 0x18, 0x1D, 0x00000000, PPC_POWER_BR) /* sraq - sraq. */ GEN_HANDLER(sraq, 0x1F, 0x18, 0x1C, 0x00000000, PPC_POWER_BR) { - gen_op_load_gpr_T0(rS(ctx->opcode)); - gen_op_load_gpr_T1(rB(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); gen_op_POWER_sraq(); gen_op_store_T0_gpr(rA(ctx->opcode)); if (unlikely(Rc(ctx->opcode) != 0)) @@ -4182,8 +4230,8 @@ GEN_HANDLER(sraq, 0x1F, 0x18, 0x1C, 0x00000000, PPC_POWER_BR) /* sre - sre. */ GEN_HANDLER(sre, 0x1F, 0x19, 0x14, 0x00000000, PPC_POWER_BR) { - gen_op_load_gpr_T0(rS(ctx->opcode)); - gen_op_load_gpr_T1(rB(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); gen_op_POWER_sre(); gen_op_store_T0_gpr(rA(ctx->opcode)); if (unlikely(Rc(ctx->opcode) != 0)) @@ -4193,8 +4241,8 @@ GEN_HANDLER(sre, 0x1F, 0x19, 0x14, 0x00000000, PPC_POWER_BR) /* srea - srea. */ GEN_HANDLER(srea, 0x1F, 0x19, 0x1C, 0x00000000, PPC_POWER_BR) { - gen_op_load_gpr_T0(rS(ctx->opcode)); - gen_op_load_gpr_T1(rB(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); gen_op_POWER_srea(); gen_op_store_T0_gpr(rA(ctx->opcode)); if (unlikely(Rc(ctx->opcode) != 0)) @@ -4204,8 +4252,8 @@ GEN_HANDLER(srea, 0x1F, 0x19, 0x1C, 0x00000000, PPC_POWER_BR) /* sreq */ GEN_HANDLER(sreq, 0x1F, 0x19, 0x16, 0x00000000, PPC_POWER_BR) { - gen_op_load_gpr_T0(rS(ctx->opcode)); - gen_op_load_gpr_T1(rB(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); gen_op_POWER_sreq(); gen_op_store_T0_gpr(rA(ctx->opcode)); if (unlikely(Rc(ctx->opcode) != 0)) @@ -4215,7 +4263,7 @@ GEN_HANDLER(sreq, 0x1F, 0x19, 0x16, 0x00000000, PPC_POWER_BR) /* sriq */ GEN_HANDLER(sriq, 0x1F, 0x18, 0x15, 0x00000000, PPC_POWER_BR) { - gen_op_load_gpr_T0(rS(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); tcg_gen_movi_tl(cpu_T[1], SH(ctx->opcode)); gen_op_POWER_srq(); gen_op_store_T0_gpr(rA(ctx->opcode)); @@ -4226,8 +4274,8 @@ GEN_HANDLER(sriq, 0x1F, 0x18, 0x15, 0x00000000, PPC_POWER_BR) /* srliq */ GEN_HANDLER(srliq, 0x1F, 0x18, 0x17, 0x00000000, PPC_POWER_BR) { - gen_op_load_gpr_T0(rS(ctx->opcode)); - gen_op_load_gpr_T1(rB(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); tcg_gen_movi_tl(cpu_T[1], SH(ctx->opcode)); gen_op_POWER_srlq(); gen_op_store_T0_gpr(rA(ctx->opcode)); @@ -4238,8 +4286,8 @@ GEN_HANDLER(srliq, 0x1F, 0x18, 0x17, 0x00000000, PPC_POWER_BR) /* srlq */ GEN_HANDLER(srlq, 0x1F, 0x18, 0x16, 0x00000000, PPC_POWER_BR) { - gen_op_load_gpr_T0(rS(ctx->opcode)); - gen_op_load_gpr_T1(rB(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); gen_op_POWER_srlq(); gen_op_store_T0_gpr(rA(ctx->opcode)); if (unlikely(Rc(ctx->opcode) != 0)) @@ -4249,8 +4297,8 @@ GEN_HANDLER(srlq, 0x1F, 0x18, 0x16, 0x00000000, PPC_POWER_BR) /* srq */ GEN_HANDLER(srq, 0x1F, 0x18, 0x14, 0x00000000, PPC_POWER_BR) { - gen_op_load_gpr_T0(rS(ctx->opcode)); - gen_op_load_gpr_T1(rB(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); gen_op_POWER_srq(); gen_op_store_T0_gpr(rA(ctx->opcode)); if (unlikely(Rc(ctx->opcode) != 0)) @@ -4282,7 +4330,7 @@ GEN_HANDLER(mfrom, 0x1F, 0x09, 0x08, 0x03E0F801, PPC_602_SPEC) GEN_EXCP_PRIVOPC(ctx); return; } - gen_op_load_gpr_T0(rA(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); gen_op_602_mfrom(); gen_op_store_T0_gpr(rD(ctx->opcode)); #endif @@ -4299,7 +4347,7 @@ GEN_HANDLER2(tlbld_6xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB) GEN_EXCP_PRIVOPC(ctx); return; } - gen_op_load_gpr_T0(rB(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rB(ctx->opcode)]); gen_op_6xx_tlbld(); #endif } @@ -4314,7 +4362,7 @@ GEN_HANDLER2(tlbli_6xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB) GEN_EXCP_PRIVOPC(ctx); return; } - gen_op_load_gpr_T0(rB(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rB(ctx->opcode)]); gen_op_6xx_tlbli(); #endif } @@ -4330,7 +4378,7 @@ GEN_HANDLER2(tlbld_74xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_74xx_TLB) GEN_EXCP_PRIVOPC(ctx); return; } - gen_op_load_gpr_T0(rB(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rB(ctx->opcode)]); gen_op_74xx_tlbld(); #endif } @@ -4345,7 +4393,7 @@ GEN_HANDLER2(tlbli_74xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_74xx_TLB) GEN_EXCP_PRIVOPC(ctx); return; } - gen_op_load_gpr_T0(rB(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rB(ctx->opcode)]); gen_op_74xx_tlbli(); #endif } @@ -4594,8 +4642,8 @@ static always_inline void gen_405_mulladd_insn (DisasContext *ctx, int opc2, int opc3, int ra, int rb, int rt, int Rc) { - gen_op_load_gpr_T0(ra); - gen_op_load_gpr_T1(rb); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[ra]); + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rb]); switch (opc3 & 0x0D) { case 0x05: /* macchw - macchw. - macchwo - macchwo. */ @@ -4646,7 +4694,7 @@ static always_inline void gen_405_mulladd_insn (DisasContext *ctx, } if (opc2 & 0x04) { /* (n)multiply-and-accumulate (0x0C - 0x0E) */ - gen_op_load_gpr_T2(rt); + tcg_gen_mov_tl(cpu_T[2], cpu_gpr[rt]); tcg_gen_mov_tl(cpu_T[1], cpu_T[0]); gen_op_405_add_T0_T2(); } @@ -4795,7 +4843,7 @@ GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR) return; } tcg_gen_movi_tl(cpu_T[0], dcrn); - gen_op_load_gpr_T1(rS(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]); gen_op_store_dcr(); #endif } @@ -4811,7 +4859,7 @@ GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX) GEN_EXCP_PRIVREG(ctx); return; } - gen_op_load_gpr_T0(rA(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); gen_op_load_dcr(); gen_op_store_T0_gpr(rD(ctx->opcode)); /* Note: Rc update flag set leads to undefined state of Rc0 */ @@ -4829,8 +4877,8 @@ GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX) GEN_EXCP_PRIVREG(ctx); return; } - gen_op_load_gpr_T0(rA(ctx->opcode)); - gen_op_load_gpr_T1(rS(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]); gen_op_store_dcr(); /* Note: Rc update flag set leads to undefined state of Rc0 */ #endif @@ -4839,7 +4887,7 @@ GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX) /* mfdcrux (PPC 460) : user-mode access to DCR */ GEN_HANDLER(mfdcrux, 0x1F, 0x03, 0x09, 0x00000000, PPC_DCRUX) { - gen_op_load_gpr_T0(rA(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); gen_op_load_dcr(); gen_op_store_T0_gpr(rD(ctx->opcode)); /* Note: Rc update flag set leads to undefined state of Rc0 */ @@ -4848,8 +4896,8 @@ GEN_HANDLER(mfdcrux, 0x1F, 0x03, 0x09, 0x00000000, PPC_DCRUX) /* mtdcrux (PPC 460) : user-mode access to DCR */ GEN_HANDLER(mtdcrux, 0x1F, 0x03, 0x0D, 0x00000000, PPC_DCRUX) { - gen_op_load_gpr_T0(rA(ctx->opcode)); - gen_op_load_gpr_T1(rS(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]); gen_op_store_dcr(); /* Note: Rc update flag set leads to undefined state of Rc0 */ } @@ -4998,12 +5046,12 @@ GEN_HANDLER2(tlbre_40x, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB) } switch (rB(ctx->opcode)) { case 0: - gen_op_load_gpr_T0(rA(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); gen_op_4xx_tlbre_hi(); gen_op_store_T0_gpr(rD(ctx->opcode)); break; case 1: - gen_op_load_gpr_T0(rA(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); gen_op_4xx_tlbre_lo(); gen_op_store_T0_gpr(rD(ctx->opcode)); break; @@ -5044,13 +5092,13 @@ GEN_HANDLER2(tlbwe_40x, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB) } switch (rB(ctx->opcode)) { case 0: - gen_op_load_gpr_T0(rA(ctx->opcode)); - gen_op_load_gpr_T1(rS(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]); gen_op_4xx_tlbwe_hi(); break; case 1: - gen_op_load_gpr_T0(rA(ctx->opcode)); - gen_op_load_gpr_T1(rS(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]); gen_op_4xx_tlbwe_lo(); break; default: @@ -5075,7 +5123,7 @@ GEN_HANDLER2(tlbre_440, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE) case 0: case 1: case 2: - gen_op_load_gpr_T0(rA(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); gen_op_440_tlbre(rB(ctx->opcode)); gen_op_store_T0_gpr(rD(ctx->opcode)); break; @@ -5118,8 +5166,8 @@ GEN_HANDLER2(tlbwe_440, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE) case 0: case 1: case 2: - gen_op_load_gpr_T0(rA(ctx->opcode)); - gen_op_load_gpr_T1(rS(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]); gen_op_440_tlbwe(rB(ctx->opcode)); break; default: @@ -5139,7 +5187,7 @@ GEN_HANDLER(wrtee, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE) GEN_EXCP_PRIVOPC(ctx); return; } - gen_op_load_gpr_T0(rD(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rD(ctx->opcode)]); gen_op_wrte(); /* Stop translation to have a chance to raise an exception * if we just set msr_ee to 1 @@ -5171,8 +5219,8 @@ GEN_HANDLER(wrteei, 0x1F, 0x03, 0x05, 0x000EFC01, PPC_WRTEE) /* dlmzb */ GEN_HANDLER(dlmzb, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC) { - gen_op_load_gpr_T0(rS(ctx->opcode)); - gen_op_load_gpr_T1(rB(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); gen_op_440_dlmzb(); gen_op_store_T0_gpr(rA(ctx->opcode)); gen_op_store_xer_bc(); @@ -5317,7 +5365,7 @@ static always_inline void gen_addr_spe_imm_index (DisasContext *ctx, int sh) if (rA(ctx->opcode) == 0) { tcg_gen_movi_tl(cpu_T[0], simm << sh); } else { - gen_op_load_gpr_T0(rA(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); if (likely(simm != 0)) gen_op_addi(simm << sh); } @@ -5465,8 +5513,8 @@ GEN_SPEOP_ARITH1(evcntlsw); static always_inline void gen_brinc (DisasContext *ctx) { /* Note: brinc is usable even if SPE is disabled */ - gen_op_load_gpr_T0(rA(ctx->opcode)); - gen_op_load_gpr_T1(rB(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); gen_op_brinc(); gen_op_store_T0_gpr(rD(ctx->opcode)); } -- 1.5.5.1 [-- Attachment #3: Type: text/plain, Size: 1 bytes --] ^ permalink raw reply related [flat|nested] 42+ messages in thread
* Re: [Qemu-devel] [PATCH 5/x] ppc: Convert op_load_gpr_{T0,T1,T2} to TCG 2008-09-02 22:22 ` [Qemu-devel] [PATCH 5/x] ppc: Convert op_load_gpr_{T0,T1,T2} " Andreas Färber @ 2008-09-02 23:20 ` Aurelien Jarno 2008-09-03 0:39 ` [Qemu-devel] [PATCH 5/x] ppc: Convert op_load_gpr_{T0, T1, T2} " Andreas Färber 0 siblings, 1 reply; 42+ messages in thread From: Aurelien Jarno @ 2008-09-02 23:20 UTC (permalink / raw) To: qemu-devel; +Cc: Andreas Faerber On Wed, Sep 03, 2008 at 12:22:48AM +0200, Andreas Färber wrote: > Replace op_load_gpr_T0, op_load_gpr_T1 and op_load_gpr_T2 with > tcg_gen_mov_tl. > > To do so, introduce TCG variables cpu_gpr[0..31]. > > Signed-off-by: Andreas Faerber <andreas.faerber@web.de> > --- > target-ppc/translate.c | 418 ++++++++++++++++++++++++++ > +--------------------- > 1 files changed, 233 insertions(+), 185 deletions(-) > > diff --git a/target-ppc/translate.c b/target-ppc/translate.c > index 9068936..0fe119a 100644 > --- a/target-ppc/translate.c > +++ b/target-ppc/translate.c > @@ -44,15 +44,57 @@ > / > *****************************************************************************/ > /* Code translation helpers > */ > > -static TCGv cpu_env, cpu_T[3]; > +/* global register indexes */ > +static TCGv cpu_env; > +static TCGv cpu_gpr[32]; > + > +/* dyngen register indexes */ > +static TCGv cpu_T[3]; > > #include "gen-icount.h" > > void ppc_translate_init(void) > { > + int i; > static int done_init = 0; > + static const char* const gprnames[32] = { > + "r0", > + "r1", > + "r2", > + "r3", > + "r4", > + "r5", > + "r6", > + "r7", > + "r8", > + "r9", > + "r10", > + "r11", > + "r12", > + "r13", > + "r14", > + "r15", > + "r16", > + "r17", > + "r18", > + "r19", > + "r20", > + "r21", > + "r22", > + "r23", > + "r24", > + "r25", > + "r26", > + "r27", > + "r28", > + "r29", > + "r30", > + "r31" > + }; > + You may want to use a sprintf() function instead (see other targets). > if (done_init) > return; > + > cpu_env = tcg_global_reg_new(TCG_TYPE_PTR, TCG_AREG0, "env"); > #if TARGET_LONG_BITS > HOST_LONG_BITS > cpu_T[0] = tcg_global_mem_new(TCG_TYPE_TL, > @@ -67,6 +109,12 @@ void ppc_translate_init(void) > cpu_T[2] = tcg_global_reg_new(TCG_TYPE_TL, TCG_AREG3, "T2"); > #endif > > + for (i = 0; i < 32; i++) { > + cpu_gpr[i] = tcg_global_mem_new(TCG_TYPE_TL, TCG_AREG0, > + offsetof(CPUState, gpr[i]), > + gprnames[i]); This is most probably wrong given the definition of ppc_gpr_t in cpu.h: - 64 bits on 64-bit targets - 32 bits on 32-bit targets and 32-bit hosts - *64 bits* on 32-bit targets and 64-bit hosts I think it is a bit weird, and I think the best is to modify cpu.h in order to have ppc_gpr_t matching the target bitness. Otherwise the patch looks ok. Care to also replace the ops in the same patch? It's actually a general request, would nice to have a few more instructions switched in a patch, to avoid spending to much time in handling patches. > + } > + > /* register helpers */ > #undef DEF_HELPER > #define DEF_HELPER(ret, name, params) tcg_register_helper(name, #name); > @@ -667,8 +715,8 @@ static opc_handler_t invalid_handler = { > #define __GEN_INT_ARITH2(name, opc1, opc2, opc3, inval, type) > \ > GEN_HANDLER(name, opc1, opc2, opc3, inval, type) > \ > { > \ > - gen_op_load_gpr_T0(rA(ctx->opcode)); > \ > - gen_op_load_gpr_T1(rB(ctx->opcode)); > \ > + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); > \ > + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); > \ > gen_op_##name(); > \ > gen_op_store_T0_gpr(rD(ctx->opcode)); > \ > if (unlikely(Rc(ctx->opcode) != 0)) > \ > @@ -678,8 +726,8 @@ GEN_HANDLER(name, opc1, opc2, opc3, inval, type) > \ > #define __GEN_INT_ARITH2_O(name, opc1, opc2, opc3, inval, type) > \ > GEN_HANDLER(name, opc1, opc2, opc3, inval, type) > \ > { > \ > - gen_op_load_gpr_T0(rA(ctx->opcode)); > \ > - gen_op_load_gpr_T1(rB(ctx->opcode)); > \ > + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); > \ > + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); > \ > gen_op_##name(); > \ > gen_op_store_T0_gpr(rD(ctx->opcode)); > \ > if (unlikely(Rc(ctx->opcode) != 0)) > \ > @@ -689,7 +737,7 @@ GEN_HANDLER(name, opc1, opc2, opc3, inval, type) > \ > #define __GEN_INT_ARITH1(name, opc1, opc2, opc3, type) > \ > GEN_HANDLER(name, opc1, opc2, opc3, 0x0000F800, type) > \ > { > \ > - gen_op_load_gpr_T0(rA(ctx->opcode)); > \ > + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); > \ > gen_op_##name(); > \ > gen_op_store_T0_gpr(rD(ctx->opcode)); > \ > if (unlikely(Rc(ctx->opcode) != 0)) > \ > @@ -698,7 +746,7 @@ GEN_HANDLER(name, opc1, opc2, opc3, 0x0000F800, > type) \ > #define __GEN_INT_ARITH1_O(name, opc1, opc2, opc3, type) > \ > GEN_HANDLER(name, opc1, opc2, opc3, 0x0000F800, type) > \ > { > \ > - gen_op_load_gpr_T0(rA(ctx->opcode)); > \ > + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); > \ > gen_op_##name(); > \ > gen_op_store_T0_gpr(rD(ctx->opcode)); > \ > if (unlikely(Rc(ctx->opcode) != 0)) > \ > @@ -723,8 +771,8 @@ __GEN_INT_ARITH1_O(name##o, opc1, opc2, opc3 | 0x10, > type) > #define __GEN_INT_ARITH2_64(name, opc1, opc2, opc3, inval, type) > \ > GEN_HANDLER(name, opc1, opc2, opc3, inval, type) > \ > { > \ > - gen_op_load_gpr_T0(rA(ctx->opcode)); > \ > - gen_op_load_gpr_T1(rB(ctx->opcode)); > \ > + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); > \ > + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); > \ > if (ctx->sf_mode) > \ > gen_op_##name##_64(); > \ > else > \ > @@ -737,8 +785,8 @@ GEN_HANDLER(name, opc1, opc2, opc3, inval, type) > \ > #define __GEN_INT_ARITH2_O_64(name, opc1, opc2, opc3, inval, type) > \ > GEN_HANDLER(name, opc1, opc2, opc3, inval, type) > \ > { > \ > - gen_op_load_gpr_T0(rA(ctx->opcode)); > \ > - gen_op_load_gpr_T1(rB(ctx->opcode)); > \ > + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); > \ > + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); > \ > if (ctx->sf_mode) > \ > gen_op_##name##_64(); > \ > else > \ > @@ -751,7 +799,7 @@ GEN_HANDLER(name, opc1, opc2, opc3, inval, type) > \ > #define __GEN_INT_ARITH1_64(name, opc1, opc2, opc3, type) > \ > GEN_HANDLER(name, opc1, opc2, opc3, 0x0000F800, type) > \ > { > \ > - gen_op_load_gpr_T0(rA(ctx->opcode)); > \ > + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); > \ > if (ctx->sf_mode) > \ > gen_op_##name##_64(); > \ > else > \ > @@ -763,7 +811,7 @@ GEN_HANDLER(name, opc1, opc2, opc3, 0x0000F800, > type) \ > #define __GEN_INT_ARITH1_O_64(name, opc1, opc2, opc3, type) > \ > GEN_HANDLER(name, opc1, opc2, opc3, 0x0000F800, type) > \ > { > \ > - gen_op_load_gpr_T0(rA(ctx->opcode)); > \ > + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); > \ > if (ctx->sf_mode) > \ > gen_op_##name##_64(); > \ > else > \ > @@ -986,7 +1034,7 @@ GEN_HANDLER(addi, 0x0E, 0xFF, 0xFF, 0x00000000, > PPC_INTEGER) > /* li case */ > tcg_gen_movi_tl(cpu_T[0], simm); > } else { > - gen_op_load_gpr_T0(rA(ctx->opcode)); > + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); > if (likely(simm != 0)) > gen_op_addi(simm); > } > @@ -997,7 +1045,7 @@ GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, > PPC_INTEGER) > { > target_long simm = SIMM(ctx->opcode); > > - gen_op_load_gpr_T0(rA(ctx->opcode)); > + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); > if (likely(simm != 0)) { > tcg_gen_mov_tl(cpu_T[2], cpu_T[0]); > gen_op_addi(simm); > @@ -1017,7 +1065,7 @@ GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, > 0x00000000, PPC_INTEGER) > { > target_long simm = SIMM(ctx->opcode); > > - gen_op_load_gpr_T0(rA(ctx->opcode)); > + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); > if (likely(simm != 0)) { > tcg_gen_mov_tl(cpu_T[2], cpu_T[0]); > gen_op_addi(simm); > @@ -1042,7 +1090,7 @@ GEN_HANDLER(addis, 0x0F, 0xFF, 0xFF, 0x00000000, > PPC_INTEGER) > /* lis case */ > tcg_gen_movi_tl(cpu_T[0], simm << 16); > } else { > - gen_op_load_gpr_T0(rA(ctx->opcode)); > + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); > if (likely(simm != 0)) > gen_op_addi(simm << 16); > } > @@ -1051,14 +1099,14 @@ GEN_HANDLER(addis, 0x0F, 0xFF, 0xFF, 0x00000000, > PPC_INTEGER) > /* mulli */ > GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) > { > - gen_op_load_gpr_T0(rA(ctx->opcode)); > + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); > gen_op_mulli(SIMM(ctx->opcode)); > gen_op_store_T0_gpr(rD(ctx->opcode)); > } > /* subfic */ > GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) > { > - gen_op_load_gpr_T0(rA(ctx->opcode)); > + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); > #if defined(TARGET_PPC64) > if (ctx->sf_mode) > gen_op_subfic_64(SIMM(ctx->opcode)); > @@ -1086,8 +1134,8 @@ GEN_INT_ARITH2 (divdu, 0x1F, 0x09, 0x0E, > PPC_64B); > #define GEN_CMP(name, opc, type) > \ > GEN_HANDLER(name, 0x1F, 0x00, opc, 0x00400000, type) > \ > { > \ > - gen_op_load_gpr_T0(rA(ctx->opcode)); > \ > - gen_op_load_gpr_T1(rB(ctx->opcode)); > \ > + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); > \ > + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); > \ > if (ctx->sf_mode && (ctx->opcode & 0x00200000)) > \ > gen_op_##name##_64(); > \ > else > \ > @@ -1098,8 +1146,8 @@ GEN_HANDLER(name, 0x1F, 0x00, opc, 0x00400000, > type) \ > #define GEN_CMP(name, opc, type) > \ > GEN_HANDLER(name, 0x1F, 0x00, opc, 0x00400000, type) > \ > { > \ > - gen_op_load_gpr_T0(rA(ctx->opcode)); > \ > - gen_op_load_gpr_T1(rB(ctx->opcode)); > \ > + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); > \ > + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); > \ > gen_op_##name(); > \ > gen_op_store_T0_crf(crfD(ctx->opcode)); > \ > } > @@ -1110,7 +1158,7 @@ GEN_CMP(cmp, 0x00, PPC_INTEGER); > /* cmpi */ > GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER) > { > - gen_op_load_gpr_T0(rA(ctx->opcode)); > + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); > #if defined(TARGET_PPC64) > if (ctx->sf_mode && (ctx->opcode & 0x00200000)) > gen_op_cmpi_64(SIMM(ctx->opcode)); > @@ -1124,7 +1172,7 @@ GEN_CMP(cmpl, 0x01, PPC_INTEGER); > /* cmpli */ > GEN_HANDLER(cmpli, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER) > { > - gen_op_load_gpr_T0(rA(ctx->opcode)); > + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); > #if defined(TARGET_PPC64) > if (ctx->sf_mode && (ctx->opcode & 0x00200000)) > gen_op_cmpli_64(UIMM(ctx->opcode)); > @@ -1143,9 +1191,9 @@ GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, > PPC_ISEL) > if (rA(ctx->opcode) == 0) { > tcg_gen_movi_tl(cpu_T[0], 0); > } else { > - gen_op_load_gpr_T1(rA(ctx->opcode)); > + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rA(ctx->opcode)]); > } > - gen_op_load_gpr_T2(rB(ctx->opcode)); > + tcg_gen_mov_tl(cpu_T[2], cpu_gpr[rB(ctx->opcode)]); > mask = 1 << (3 - (bi & 0x03)); > gen_op_load_crf_T0(bi >> 2); > gen_op_test_true(mask); > @@ -1157,8 +1205,8 @@ GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, > PPC_ISEL) > #define __GEN_LOGICAL2(name, opc2, opc3, type) > \ > GEN_HANDLER(name, 0x1F, opc2, opc3, 0x00000000, type) > \ > { > \ > - gen_op_load_gpr_T0(rS(ctx->opcode)); > \ > - gen_op_load_gpr_T1(rB(ctx->opcode)); > \ > + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); > \ > + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); > \ > gen_op_##name(); > \ > gen_op_store_T0_gpr(rA(ctx->opcode)); > \ > if (unlikely(Rc(ctx->opcode) != 0)) > \ > @@ -1170,7 +1218,7 @@ __GEN_LOGICAL2(name, 0x1C, opc, type) > #define GEN_LOGICAL1(name, opc, type) > \ > GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type) > \ > { > \ > - gen_op_load_gpr_T0(rS(ctx->opcode)); > \ > + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); > \ > gen_op_##name(); > \ > gen_op_store_T0_gpr(rA(ctx->opcode)); > \ > if (unlikely(Rc(ctx->opcode) != 0)) > \ > @@ -1184,7 +1232,7 @@ GEN_LOGICAL2(andc, 0x01, PPC_INTEGER); > /* andi. */ > GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) > { > - gen_op_load_gpr_T0(rS(ctx->opcode)); > + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); > gen_op_andi_T0(UIMM(ctx->opcode)); > gen_op_store_T0_gpr(rA(ctx->opcode)); > gen_set_Rc0(ctx); > @@ -1192,7 +1240,7 @@ GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, > 0x00000000, PPC_INTEGER) > /* andis. */ > GEN_HANDLER2(andis_, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, > PPC_INTEGER) > { > - gen_op_load_gpr_T0(rS(ctx->opcode)); > + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); > gen_op_andi_T0(UIMM(ctx->opcode) << 16); > gen_op_store_T0_gpr(rA(ctx->opcode)); > gen_set_Rc0(ctx); > @@ -1221,16 +1269,16 @@ GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, > PPC_INTEGER) > rb = rB(ctx->opcode); > /* Optimisation for mr. ri case */ > if (rs != ra || rs != rb) { > - gen_op_load_gpr_T0(rs); > + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rs]); > if (rs != rb) { > - gen_op_load_gpr_T1(rb); > + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rb]); > gen_op_or(); > } > gen_op_store_T0_gpr(ra); > if (unlikely(Rc(ctx->opcode) != 0)) > gen_set_Rc0(ctx); > } else if (unlikely(Rc(ctx->opcode) != 0)) { > - gen_op_load_gpr_T0(rs); > + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rs]); > gen_set_Rc0(ctx); > #if defined(TARGET_PPC64) > } else { > @@ -1286,10 +1334,10 @@ GEN_LOGICAL2(orc, 0x0C, PPC_INTEGER); > /* xor & xor. */ > GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER) > { > - gen_op_load_gpr_T0(rS(ctx->opcode)); > + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); > /* Optimisation for "set to zero" case */ > if (rS(ctx->opcode) != rB(ctx->opcode)) { > - gen_op_load_gpr_T1(rB(ctx->opcode)); > + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); > gen_op_xor(); > } else { > tcg_gen_movi_tl(cpu_T[0], 0); > @@ -1308,7 +1356,7 @@ GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, > PPC_INTEGER) > /* XXX: should handle special NOPs for POWER series */ > return; > } > - gen_op_load_gpr_T0(rS(ctx->opcode)); > + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); > if (likely(uimm != 0)) > gen_op_ori(uimm); > gen_op_store_T0_gpr(rA(ctx->opcode)); > @@ -1322,7 +1370,7 @@ GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, > PPC_INTEGER) > /* NOP */ > return; > } > - gen_op_load_gpr_T0(rS(ctx->opcode)); > + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); > if (likely(uimm != 0)) > gen_op_ori(uimm << 16); > gen_op_store_T0_gpr(rA(ctx->opcode)); > @@ -1336,7 +1384,7 @@ GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, > PPC_INTEGER) > /* NOP */ > return; > } > - gen_op_load_gpr_T0(rS(ctx->opcode)); > + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); > if (likely(uimm != 0)) > gen_op_xori(uimm); > gen_op_store_T0_gpr(rA(ctx->opcode)); > @@ -1351,7 +1399,7 @@ GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, > PPC_INTEGER) > /* NOP */ > return; > } > - gen_op_load_gpr_T0(rS(ctx->opcode)); > + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); > if (likely(uimm != 0)) > gen_op_xori(uimm << 16); > gen_op_store_T0_gpr(rA(ctx->opcode)); > @@ -1360,7 +1408,7 @@ GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, > PPC_INTEGER) > /* popcntb : PowerPC 2.03 specification */ > GEN_HANDLER(popcntb, 0x1F, 0x03, 0x03, 0x0000F801, PPC_POPCNTB) > { > - gen_op_load_gpr_T0(rS(ctx->opcode)); > + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); > #if defined(TARGET_PPC64) > if (ctx->sf_mode) > gen_op_popcntb_64(); > @@ -1389,18 +1437,18 @@ GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, > 0x00000000, PPC_INTEGER) > sh = SH(ctx->opcode); > if (likely(sh == 0)) { > if (likely(mb == 0 && me == 31)) { > - gen_op_load_gpr_T0(rS(ctx->opcode)); > + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); > goto do_store; > } else if (likely(mb == 31 && me == 0)) { > - gen_op_load_gpr_T0(rA(ctx->opcode)); > + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); > goto do_store; > } > - gen_op_load_gpr_T0(rS(ctx->opcode)); > - gen_op_load_gpr_T1(rA(ctx->opcode)); > + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); > + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rA(ctx->opcode)]); > goto do_mask; > } > - gen_op_load_gpr_T0(rS(ctx->opcode)); > - gen_op_load_gpr_T1(rA(ctx->opcode)); > + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); > + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rA(ctx->opcode)]); > gen_op_rotli32_T0(SH(ctx->opcode)); > do_mask: > #if defined(TARGET_PPC64) > @@ -1424,7 +1472,7 @@ GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, > PPC_INTEGER) > sh = SH(ctx->opcode); > mb = MB(ctx->opcode); > me = ME(ctx->opcode); > - gen_op_load_gpr_T0(rS(ctx->opcode)); > + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); > if (likely(sh == 0)) { > goto do_mask; > } > @@ -1461,8 +1509,8 @@ GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, > PPC_INTEGER) > > mb = MB(ctx->opcode); > me = ME(ctx->opcode); > - gen_op_load_gpr_T0(rS(ctx->opcode)); > - gen_op_load_gpr_T1(rB(ctx->opcode)); > + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); > + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); > gen_op_rotl32_T0_T1(); > if (unlikely(mb != 0 || me != 31)) { > #if defined(TARGET_PPC64) > @@ -1527,7 +1575,7 @@ static always_inline void gen_andi_T1_64 > (DisasContext *ctx, uint64_t mask) > static always_inline void gen_rldinm (DisasContext *ctx, uint32_t mb, > uint32_t me, uint32_t sh) > { > - gen_op_load_gpr_T0(rS(ctx->opcode)); > + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); > if (likely(sh == 0)) { > goto do_mask; > } > @@ -1587,8 +1635,8 @@ GEN_PPC64_R4(rldic, 0x1E, 0x04); > static always_inline void gen_rldnm (DisasContext *ctx, uint32_t mb, > uint32_t me) > { > - gen_op_load_gpr_T0(rS(ctx->opcode)); > - gen_op_load_gpr_T1(rB(ctx->opcode)); > + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); > + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); > gen_op_rotl64_T0_T1(); > if (unlikely(mb != 0 || me != 63)) { > gen_andi_T0_64(ctx, MASK(mb, me)); > @@ -1627,15 +1675,15 @@ static always_inline void gen_rldimi > (DisasContext *ctx, int mbn, int shn) > me = 63 - sh; > if (likely(sh == 0)) { > if (likely(mb == 0)) { > - gen_op_load_gpr_T0(rS(ctx->opcode)); > + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); > goto do_store; > } > - gen_op_load_gpr_T0(rS(ctx->opcode)); > - gen_op_load_gpr_T1(rA(ctx->opcode)); > + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); > + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rA(ctx->opcode)]); > goto do_mask; > } > - gen_op_load_gpr_T0(rS(ctx->opcode)); > - gen_op_load_gpr_T1(rA(ctx->opcode)); > + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); > + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rA(ctx->opcode)]); > gen_op_rotli64_T0(sh); > do_mask: > mask = MASK(mb, me); > @@ -1659,7 +1707,7 @@ __GEN_LOGICAL2(sraw, 0x18, 0x18, PPC_INTEGER); > GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER) > { > int mb, me; > - gen_op_load_gpr_T0(rS(ctx->opcode)); > + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); > if (SH(ctx->opcode) != 0) { > tcg_gen_mov_tl(cpu_T[1], cpu_T[0]); > mb = 32 - SH(ctx->opcode); > @@ -1688,7 +1736,7 @@ static always_inline void gen_sradi (DisasContext > *ctx, int n) > uint64_t mask; > int sh, mb, me; > > - gen_op_load_gpr_T0(rS(ctx->opcode)); > + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); > sh = SH(ctx->opcode) + (n << 5); > if (sh != 0) { > tcg_gen_mov_tl(cpu_T[1], cpu_T[0]); > @@ -2082,7 +2130,7 @@ static always_inline void gen_addr_imm_index > (DisasContext *ctx, > if (rA(ctx->opcode) == 0) { > tcg_gen_movi_tl(cpu_T[0], simm); > } else { > - gen_op_load_gpr_T0(rA(ctx->opcode)); > + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); > if (likely(simm != 0)) > gen_op_addi(simm); > } > @@ -2094,10 +2142,10 @@ static always_inline void gen_addr_imm_index > (DisasContext *ctx, > static always_inline void gen_addr_reg_index (DisasContext *ctx) > { > if (rA(ctx->opcode) == 0) { > - gen_op_load_gpr_T0(rB(ctx->opcode)); > + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rB(ctx->opcode)]); > } else { > - gen_op_load_gpr_T0(rA(ctx->opcode)); > - gen_op_load_gpr_T1(rB(ctx->opcode)); > + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); > + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); > gen_op_add(); > } > #ifdef DEBUG_MEMORY_ACCESSES > @@ -2110,7 +2158,7 @@ static always_inline void gen_addr_register > (DisasContext *ctx) > if (rA(ctx->opcode) == 0) { > tcg_gen_movi_tl(cpu_T[0], 0); > } else { > - gen_op_load_gpr_T0(rA(ctx->opcode)); > + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); > } > #ifdef DEBUG_MEMORY_ACCESSES > gen_op_print_mem_EA(); > @@ -2309,7 +2357,7 @@ GEN_HANDLER(lq, 0x38, 0xFF, 0xFF, 0x00000000, > PPC_64BX) > GEN_HANDLER(st##width, opc, 0xFF, 0xFF, 0x00000000, type) > \ > { > \ > gen_addr_imm_index(ctx, 0); > \ > - gen_op_load_gpr_T1(rS(ctx->opcode)); > \ > + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]); > \ > op_ldst(st##width); > \ > } > > @@ -2324,7 +2372,7 @@ GEN_HANDLER(st##width##u, opc, 0xFF, 0xFF, > 0x00000000, type) \ > gen_addr_imm_index(ctx, 0x03); > \ > else > \ > gen_addr_imm_index(ctx, 0); > \ > - gen_op_load_gpr_T1(rS(ctx->opcode)); > \ > + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]); > \ > op_ldst(st##width); > \ > gen_op_store_T0_gpr(rA(ctx->opcode)); > \ > } > @@ -2337,7 +2385,7 @@ GEN_HANDLER(st##width##ux, 0x1F, opc2, opc3, > 0x00000001, type) \ > return; > \ > } \ > gen_addr_reg_index(ctx); > \ > - gen_op_load_gpr_T1(rS(ctx->opcode)); > \ > + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]); > \ > op_ldst(st##width); > \ > gen_op_store_T0_gpr(rA(ctx->opcode)); > \ > } > @@ -2346,7 +2394,7 @@ GEN_HANDLER(st##width##ux, 0x1F, opc2, opc3, > 0x00000001, type) \ > GEN_HANDLER(st##width##x, 0x1F, opc2, opc3, 0x00000001, type) > \ > { > \ > gen_addr_reg_index(ctx); > \ > - gen_op_load_gpr_T1(rS(ctx->opcode)); > \ > + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]); > \ > op_ldst(st##width); > \ > } > > @@ -2391,10 +2439,10 @@ GEN_HANDLER(std, 0x3E, 0xFF, 0xFF, 0x00000000, > PPC_64B) > return; > } > gen_addr_imm_index(ctx, 0x03); > - gen_op_load_gpr_T1(rs); > + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rs]); > op_ldst(std); > gen_op_addi(8); > - gen_op_load_gpr_T1(rs + 1); > + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rs + 1]); > op_ldst(std); > #endif > } else { > @@ -2406,7 +2454,7 @@ GEN_HANDLER(std, 0x3E, 0xFF, 0xFF, 0x00000000, > PPC_64B) > } > } > gen_addr_imm_index(ctx, 0x03); > - gen_op_load_gpr_T1(rs); > + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rs]); > op_ldst(std); > if (Rc(ctx->opcode)) > gen_op_store_T0_gpr(rA(ctx->opcode)); > @@ -2599,7 +2647,7 @@ GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, > 0x00000000, PPC_RES) > /* NIP cannot be restored if the memory exception comes from an > helper */ > gen_update_nip(ctx, ctx->nip - 4); > gen_addr_reg_index(ctx); > - gen_op_load_gpr_T1(rS(ctx->opcode)); > + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]); > op_stwcx(); > } > > @@ -2629,7 +2677,7 @@ GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, > 0x00000000, PPC_64B) > /* NIP cannot be restored if the memory exception comes from an > helper */ > gen_update_nip(ctx, ctx->nip - 4); > gen_addr_reg_index(ctx); > - gen_op_load_gpr_T1(rS(ctx->opcode)); > + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]); > op_stdcx(); > } > #endif /* defined(TARGET_PPC64) */ > @@ -3154,8 +3202,8 @@ GEN_HANDLER(sc, 0x11, 0xFF, 0xFF, 0x03FFF01D, > PPC_FLOW) > /* tw */ > GEN_HANDLER(tw, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW) > { > - gen_op_load_gpr_T0(rA(ctx->opcode)); > - gen_op_load_gpr_T1(rB(ctx->opcode)); > + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); > + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); > /* Update the nip since this might generate a trap exception */ > gen_update_nip(ctx, ctx->nip); > gen_op_tw(TO(ctx->opcode)); > @@ -3164,7 +3212,7 @@ GEN_HANDLER(tw, 0x1F, 0x04, 0x00, 0x00000001, > PPC_FLOW) > /* twi */ > GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW) > { > - gen_op_load_gpr_T0(rA(ctx->opcode)); > + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); > tcg_gen_movi_tl(cpu_T[1], SIMM(ctx->opcode)); > /* Update the nip since this might generate a trap exception */ > gen_update_nip(ctx, ctx->nip); > @@ -3175,8 +3223,8 @@ GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, > PPC_FLOW) > /* td */ > GEN_HANDLER(td, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B) > { > - gen_op_load_gpr_T0(rA(ctx->opcode)); > - gen_op_load_gpr_T1(rB(ctx->opcode)); > + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); > + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); > /* Update the nip since this might generate a trap exception */ > gen_update_nip(ctx, ctx->nip); > gen_op_td(TO(ctx->opcode)); > @@ -3185,7 +3233,7 @@ GEN_HANDLER(td, 0x1F, 0x04, 0x02, 0x00000001, > PPC_64B) > /* tdi */ > GEN_HANDLER(tdi, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B) > { > - gen_op_load_gpr_T0(rA(ctx->opcode)); > + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); > tcg_gen_movi_tl(cpu_T[1], SIMM(ctx->opcode)); > /* Update the nip since this might generate a trap exception */ > gen_update_nip(ctx, ctx->nip); > @@ -3309,7 +3357,7 @@ GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, > PPC_MISC) > { > uint32_t crm, crn; > > - gen_op_load_gpr_T0(rS(ctx->opcode)); > + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); > crm = CRM(ctx->opcode); > if (likely((ctx->opcode & 0x00100000) || (crm ^ (crm - 1)) == 0)) { > crn = ffs(crm); > @@ -3332,7 +3380,7 @@ GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, > PPC_64B) > GEN_EXCP_PRIVREG(ctx); > return; > } > - gen_op_load_gpr_T0(rS(ctx->opcode)); > + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); > if (ctx->opcode & 0x00010000) { > /* Special form that does not need any synchronisation */ > gen_op_update_riee(); > @@ -3360,7 +3408,7 @@ GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001FF801, > PPC_MISC) > GEN_EXCP_PRIVREG(ctx); > return; > } > - gen_op_load_gpr_T0(rS(ctx->opcode)); > + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); > if (ctx->opcode & 0x00010000) { > /* Special form that does not need any synchronisation */ > gen_op_update_riee(); > @@ -3399,7 +3447,7 @@ GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000001, > PPC_MISC) > write_cb = ctx->spr_cb[sprn].uea_write; > if (likely(write_cb != NULL)) { > if (likely(write_cb != SPR_NOACCESS)) { > - gen_op_load_gpr_T0(rS(ctx->opcode)); > + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); > (*write_cb)(ctx, sprn); > } else { > /* Privilege exception */ > @@ -3628,7 +3676,7 @@ GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, > PPC_SEGMENT) > GEN_EXCP_PRIVREG(ctx); > return; > } > - gen_op_load_gpr_T1(rB(ctx->opcode)); > + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); > gen_op_srli_T1(28); > gen_op_load_sr(); > gen_op_store_T0_gpr(rD(ctx->opcode)); > @@ -3645,7 +3693,7 @@ GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, > PPC_SEGMENT) > GEN_EXCP_PRIVREG(ctx); > return; > } > - gen_op_load_gpr_T0(rS(ctx->opcode)); > + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); > tcg_gen_movi_tl(cpu_T[1], SR(ctx->opcode)); > gen_op_store_sr(); > #endif > @@ -3661,8 +3709,8 @@ GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, > PPC_SEGMENT) > GEN_EXCP_PRIVREG(ctx); > return; > } > - gen_op_load_gpr_T0(rS(ctx->opcode)); > - gen_op_load_gpr_T1(rB(ctx->opcode)); > + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); > + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); > gen_op_srli_T1(28); > gen_op_store_sr(); > #endif > @@ -3697,7 +3745,7 @@ GEN_HANDLER2(mfsrin_64b, "mfsrin", 0x1F, 0x13, > 0x14, 0x001F0001, > GEN_EXCP_PRIVREG(ctx); > return; > } > - gen_op_load_gpr_T1(rB(ctx->opcode)); > + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); > gen_op_srli_T1(28); > gen_op_load_slb(); > gen_op_store_T0_gpr(rD(ctx->opcode)); > @@ -3714,7 +3762,7 @@ GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, > 0x0010F801, PPC_SEGMENT_64B) > GEN_EXCP_PRIVREG(ctx); > return; > } > - gen_op_load_gpr_T0(rS(ctx->opcode)); > + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); > tcg_gen_movi_tl(cpu_T[1], SR(ctx->opcode)); > gen_op_store_slb(); > #endif > @@ -3731,8 +3779,8 @@ GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, > 0x07, 0x001F0001, > GEN_EXCP_PRIVREG(ctx); > return; > } > - gen_op_load_gpr_T0(rS(ctx->opcode)); > - gen_op_load_gpr_T1(rB(ctx->opcode)); > + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); > + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); > gen_op_srli_T1(28); > gen_op_store_slb(); > #endif > @@ -3765,7 +3813,7 @@ GEN_HANDLER(tlbie, 0x1F, 0x12, 0x09, 0x03FF0001, > PPC_MEM_TLBIE) > GEN_EXCP_PRIVOPC(ctx); > return; > } > - gen_op_load_gpr_T0(rB(ctx->opcode)); > + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rB(ctx->opcode)]); > #if defined(TARGET_PPC64) > if (ctx->sf_mode) > gen_op_tlbie_64(); > @@ -3817,7 +3865,7 @@ GEN_HANDLER(slbie, 0x1F, 0x12, 0x0D, 0x03FF0001, > PPC_SLBI) > GEN_EXCP_PRIVOPC(ctx); > return; > } > - gen_op_load_gpr_T0(rB(ctx->opcode)); > + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rB(ctx->opcode)]); > gen_op_slbie(); > #endif > } > @@ -3848,7 +3896,7 @@ GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, > PPC_EXTERN) > { > /* Should check EAR[E] & alignment ! */ > gen_addr_reg_index(ctx); > - gen_op_load_gpr_T1(rS(ctx->opcode)); > + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]); > op_ecowx(); > } > > @@ -3856,7 +3904,7 @@ GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, > PPC_EXTERN) > /* abs - abs. */ > GEN_HANDLER(abs, 0x1F, 0x08, 0x0B, 0x0000F800, PPC_POWER_BR) > { > - gen_op_load_gpr_T0(rA(ctx->opcode)); > + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); > gen_op_POWER_abs(); > gen_op_store_T0_gpr(rD(ctx->opcode)); > if (unlikely(Rc(ctx->opcode) != 0)) > @@ -3866,7 +3914,7 @@ GEN_HANDLER(abs, 0x1F, 0x08, 0x0B, 0x0000F800, > PPC_POWER_BR) > /* abso - abso. */ > GEN_HANDLER(abso, 0x1F, 0x08, 0x1B, 0x0000F800, PPC_POWER_BR) > { > - gen_op_load_gpr_T0(rA(ctx->opcode)); > + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); > gen_op_POWER_abso(); > gen_op_store_T0_gpr(rD(ctx->opcode)); > if (unlikely(Rc(ctx->opcode) != 0)) > @@ -3876,7 +3924,7 @@ GEN_HANDLER(abso, 0x1F, 0x08, 0x1B, 0x0000F800, > PPC_POWER_BR) > /* clcs */ > GEN_HANDLER(clcs, 0x1F, 0x10, 0x13, 0x0000F800, PPC_POWER_BR) > { > - gen_op_load_gpr_T0(rA(ctx->opcode)); > + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); > gen_op_POWER_clcs(); > /* Rc=1 sets CR0 to an undefined state */ > gen_op_store_T0_gpr(rD(ctx->opcode)); > @@ -3885,8 +3933,8 @@ GEN_HANDLER(clcs, 0x1F, 0x10, 0x13, 0x0000F800, > PPC_POWER_BR) > /* div - div. */ > GEN_HANDLER(div, 0x1F, 0x0B, 0x0A, 0x00000000, PPC_POWER_BR) > { > - gen_op_load_gpr_T0(rA(ctx->opcode)); > - gen_op_load_gpr_T1(rB(ctx->opcode)); > + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); > + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); > gen_op_POWER_div(); > gen_op_store_T0_gpr(rD(ctx->opcode)); > if (unlikely(Rc(ctx->opcode) != 0)) > @@ -3896,8 +3944,8 @@ GEN_HANDLER(div, 0x1F, 0x0B, 0x0A, 0x00000000, > PPC_POWER_BR) > /* divo - divo. */ > GEN_HANDLER(divo, 0x1F, 0x0B, 0x1A, 0x00000000, PPC_POWER_BR) > { > - gen_op_load_gpr_T0(rA(ctx->opcode)); > - gen_op_load_gpr_T1(rB(ctx->opcode)); > + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); > + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); > gen_op_POWER_divo(); > gen_op_store_T0_gpr(rD(ctx->opcode)); > if (unlikely(Rc(ctx->opcode) != 0)) > @@ -3907,8 +3955,8 @@ GEN_HANDLER(divo, 0x1F, 0x0B, 0x1A, 0x00000000, > PPC_POWER_BR) > /* divs - divs. */ > GEN_HANDLER(divs, 0x1F, 0x0B, 0x0B, 0x00000000, PPC_POWER_BR) > { > - gen_op_load_gpr_T0(rA(ctx->opcode)); > - gen_op_load_gpr_T1(rB(ctx->opcode)); > + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); > + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); > gen_op_POWER_divs(); > gen_op_store_T0_gpr(rD(ctx->opcode)); > if (unlikely(Rc(ctx->opcode) != 0)) > @@ -3918,8 +3966,8 @@ GEN_HANDLER(divs, 0x1F, 0x0B, 0x0B, 0x00000000, > PPC_POWER_BR) > /* divso - divso. */ > GEN_HANDLER(divso, 0x1F, 0x0B, 0x1B, 0x00000000, PPC_POWER_BR) > { > - gen_op_load_gpr_T0(rA(ctx->opcode)); > - gen_op_load_gpr_T1(rB(ctx->opcode)); > + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); > + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); > gen_op_POWER_divso(); > gen_op_store_T0_gpr(rD(ctx->opcode)); > if (unlikely(Rc(ctx->opcode) != 0)) > @@ -3929,8 +3977,8 @@ GEN_HANDLER(divso, 0x1F, 0x0B, 0x1B, 0x00000000, > PPC_POWER_BR) > /* doz - doz. */ > GEN_HANDLER(doz, 0x1F, 0x08, 0x08, 0x00000000, PPC_POWER_BR) > { > - gen_op_load_gpr_T0(rA(ctx->opcode)); > - gen_op_load_gpr_T1(rB(ctx->opcode)); > + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); > + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); > gen_op_POWER_doz(); > gen_op_store_T0_gpr(rD(ctx->opcode)); > if (unlikely(Rc(ctx->opcode) != 0)) > @@ -3940,8 +3988,8 @@ GEN_HANDLER(doz, 0x1F, 0x08, 0x08, 0x00000000, > PPC_POWER_BR) > /* dozo - dozo. */ > GEN_HANDLER(dozo, 0x1F, 0x08, 0x18, 0x00000000, PPC_POWER_BR) > { > - gen_op_load_gpr_T0(rA(ctx->opcode)); > - gen_op_load_gpr_T1(rB(ctx->opcode)); > + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); > + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); > gen_op_POWER_dozo(); > gen_op_store_T0_gpr(rD(ctx->opcode)); > if (unlikely(Rc(ctx->opcode) != 0)) > @@ -3951,7 +3999,7 @@ GEN_HANDLER(dozo, 0x1F, 0x08, 0x18, 0x00000000, > PPC_POWER_BR) > /* dozi */ > GEN_HANDLER(dozi, 0x09, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR) > { > - gen_op_load_gpr_T0(rA(ctx->opcode)); > + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); > tcg_gen_movi_tl(cpu_T[1], SIMM(ctx->opcode)); > gen_op_POWER_doz(); > gen_op_store_T0_gpr(rD(ctx->opcode)); > @@ -4001,8 +4049,8 @@ GEN_HANDLER(lscbx, 0x1F, 0x15, 0x08, 0x00000000, > PPC_POWER_BR) > /* maskg - maskg. */ > GEN_HANDLER(maskg, 0x1F, 0x1D, 0x00, 0x00000000, PPC_POWER_BR) > { > - gen_op_load_gpr_T0(rS(ctx->opcode)); > - gen_op_load_gpr_T1(rB(ctx->opcode)); > + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); > + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); > gen_op_POWER_maskg(); > gen_op_store_T0_gpr(rA(ctx->opcode)); > if (unlikely(Rc(ctx->opcode) != 0)) > @@ -4012,9 +4060,9 @@ GEN_HANDLER(maskg, 0x1F, 0x1D, 0x00, 0x00000000, > PPC_POWER_BR) > /* maskir - maskir. */ > GEN_HANDLER(maskir, 0x1F, 0x1D, 0x10, 0x00000000, PPC_POWER_BR) > { > - gen_op_load_gpr_T0(rA(ctx->opcode)); > - gen_op_load_gpr_T1(rS(ctx->opcode)); > - gen_op_load_gpr_T2(rB(ctx->opcode)); > + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); > + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]); > + tcg_gen_mov_tl(cpu_T[2], cpu_gpr[rB(ctx->opcode)]); > gen_op_POWER_maskir(); > gen_op_store_T0_gpr(rA(ctx->opcode)); > if (unlikely(Rc(ctx->opcode) != 0)) > @@ -4024,8 +4072,8 @@ GEN_HANDLER(maskir, 0x1F, 0x1D, 0x10, 0x00000000, > PPC_POWER_BR) > /* mul - mul. */ > GEN_HANDLER(mul, 0x1F, 0x0B, 0x03, 0x00000000, PPC_POWER_BR) > { > - gen_op_load_gpr_T0(rA(ctx->opcode)); > - gen_op_load_gpr_T1(rB(ctx->opcode)); > + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); > + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); > gen_op_POWER_mul(); > gen_op_store_T0_gpr(rD(ctx->opcode)); > if (unlikely(Rc(ctx->opcode) != 0)) > @@ -4035,8 +4083,8 @@ GEN_HANDLER(mul, 0x1F, 0x0B, 0x03, 0x00000000, > PPC_POWER_BR) > /* mulo - mulo. */ > GEN_HANDLER(mulo, 0x1F, 0x0B, 0x13, 0x00000000, PPC_POWER_BR) > { > - gen_op_load_gpr_T0(rA(ctx->opcode)); > - gen_op_load_gpr_T1(rB(ctx->opcode)); > + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); > + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); > gen_op_POWER_mulo(); > gen_op_store_T0_gpr(rD(ctx->opcode)); > if (unlikely(Rc(ctx->opcode) != 0)) > @@ -4046,7 +4094,7 @@ GEN_HANDLER(mulo, 0x1F, 0x0B, 0x13, 0x00000000, > PPC_POWER_BR) > /* nabs - nabs. */ > GEN_HANDLER(nabs, 0x1F, 0x08, 0x0F, 0x00000000, PPC_POWER_BR) > { > - gen_op_load_gpr_T0(rA(ctx->opcode)); > + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); > gen_op_POWER_nabs(); > gen_op_store_T0_gpr(rD(ctx->opcode)); > if (unlikely(Rc(ctx->opcode) != 0)) > @@ -4056,7 +4104,7 @@ GEN_HANDLER(nabs, 0x1F, 0x08, 0x0F, 0x00000000, > PPC_POWER_BR) > /* nabso - nabso. */ > GEN_HANDLER(nabso, 0x1F, 0x08, 0x1F, 0x00000000, PPC_POWER_BR) > { > - gen_op_load_gpr_T0(rA(ctx->opcode)); > + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); > gen_op_POWER_nabso(); > gen_op_store_T0_gpr(rD(ctx->opcode)); > if (unlikely(Rc(ctx->opcode) != 0)) > @@ -4070,9 +4118,9 @@ GEN_HANDLER(rlmi, 0x16, 0xFF, 0xFF, 0x00000000, > PPC_POWER_BR) > > mb = MB(ctx->opcode); > me = ME(ctx->opcode); > - gen_op_load_gpr_T0(rS(ctx->opcode)); > - gen_op_load_gpr_T1(rA(ctx->opcode)); > - gen_op_load_gpr_T2(rB(ctx->opcode)); > + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); > + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rA(ctx->opcode)]); > + tcg_gen_mov_tl(cpu_T[2], cpu_gpr[rB(ctx->opcode)]); > gen_op_POWER_rlmi(MASK(mb, me), ~MASK(mb, me)); > gen_op_store_T0_gpr(rA(ctx->opcode)); > if (unlikely(Rc(ctx->opcode) != 0)) > @@ -4082,9 +4130,9 @@ GEN_HANDLER(rlmi, 0x16, 0xFF, 0xFF, 0x00000000, > PPC_POWER_BR) > /* rrib - rrib. */ > GEN_HANDLER(rrib, 0x1F, 0x19, 0x10, 0x00000000, PPC_POWER_BR) > { > - gen_op_load_gpr_T0(rS(ctx->opcode)); > - gen_op_load_gpr_T1(rA(ctx->opcode)); > - gen_op_load_gpr_T2(rB(ctx->opcode)); > + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); > + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rA(ctx->opcode)]); > + tcg_gen_mov_tl(cpu_T[2], cpu_gpr[rB(ctx->opcode)]); > gen_op_POWER_rrib(); > gen_op_store_T0_gpr(rA(ctx->opcode)); > if (unlikely(Rc(ctx->opcode) != 0)) > @@ -4094,8 +4142,8 @@ GEN_HANDLER(rrib, 0x1F, 0x19, 0x10, 0x00000000, > PPC_POWER_BR) > /* sle - sle. */ > GEN_HANDLER(sle, 0x1F, 0x19, 0x04, 0x00000000, PPC_POWER_BR) > { > - gen_op_load_gpr_T0(rS(ctx->opcode)); > - gen_op_load_gpr_T1(rB(ctx->opcode)); > + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); > + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); > gen_op_POWER_sle(); > gen_op_store_T0_gpr(rA(ctx->opcode)); > if (unlikely(Rc(ctx->opcode) != 0)) > @@ -4105,8 +4153,8 @@ GEN_HANDLER(sle, 0x1F, 0x19, 0x04, 0x00000000, > PPC_POWER_BR) > /* sleq - sleq. */ > GEN_HANDLER(sleq, 0x1F, 0x19, 0x06, 0x00000000, PPC_POWER_BR) > { > - gen_op_load_gpr_T0(rS(ctx->opcode)); > - gen_op_load_gpr_T1(rB(ctx->opcode)); > + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); > + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); > gen_op_POWER_sleq(); > gen_op_store_T0_gpr(rA(ctx->opcode)); > if (unlikely(Rc(ctx->opcode) != 0)) > @@ -4116,7 +4164,7 @@ GEN_HANDLER(sleq, 0x1F, 0x19, 0x06, 0x00000000, > PPC_POWER_BR) > /* sliq - sliq. */ > GEN_HANDLER(sliq, 0x1F, 0x18, 0x05, 0x00000000, PPC_POWER_BR) > { > - gen_op_load_gpr_T0(rS(ctx->opcode)); > + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); > tcg_gen_movi_tl(cpu_T[1], SH(ctx->opcode)); > gen_op_POWER_sle(); > gen_op_store_T0_gpr(rA(ctx->opcode)); > @@ -4127,7 +4175,7 @@ GEN_HANDLER(sliq, 0x1F, 0x18, 0x05, 0x00000000, > PPC_POWER_BR) > /* slliq - slliq. */ > GEN_HANDLER(slliq, 0x1F, 0x18, 0x07, 0x00000000, PPC_POWER_BR) > { > - gen_op_load_gpr_T0(rS(ctx->opcode)); > + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); > tcg_gen_movi_tl(cpu_T[1], SH(ctx->opcode)); > gen_op_POWER_sleq(); > gen_op_store_T0_gpr(rA(ctx->opcode)); > @@ -4138,8 +4186,8 @@ GEN_HANDLER(slliq, 0x1F, 0x18, 0x07, 0x00000000, > PPC_POWER_BR) > /* sllq - sllq. */ > GEN_HANDLER(sllq, 0x1F, 0x18, 0x06, 0x00000000, PPC_POWER_BR) > { > - gen_op_load_gpr_T0(rS(ctx->opcode)); > - gen_op_load_gpr_T1(rB(ctx->opcode)); > + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); > + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); > gen_op_POWER_sllq(); > gen_op_store_T0_gpr(rA(ctx->opcode)); > if (unlikely(Rc(ctx->opcode) != 0)) > @@ -4149,8 +4197,8 @@ GEN_HANDLER(sllq, 0x1F, 0x18, 0x06, 0x00000000, > PPC_POWER_BR) > /* slq - slq. */ > GEN_HANDLER(slq, 0x1F, 0x18, 0x04, 0x00000000, PPC_POWER_BR) > { > - gen_op_load_gpr_T0(rS(ctx->opcode)); > - gen_op_load_gpr_T1(rB(ctx->opcode)); > + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); > + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); > gen_op_POWER_slq(); > gen_op_store_T0_gpr(rA(ctx->opcode)); > if (unlikely(Rc(ctx->opcode) != 0)) > @@ -4160,7 +4208,7 @@ GEN_HANDLER(slq, 0x1F, 0x18, 0x04, 0x00000000, > PPC_POWER_BR) > /* sraiq - sraiq. */ > GEN_HANDLER(sraiq, 0x1F, 0x18, 0x1D, 0x00000000, PPC_POWER_BR) > { > - gen_op_load_gpr_T0(rS(ctx->opcode)); > + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); > tcg_gen_movi_tl(cpu_T[1], SH(ctx->opcode)); > gen_op_POWER_sraq(); > gen_op_store_T0_gpr(rA(ctx->opcode)); > @@ -4171,8 +4219,8 @@ GEN_HANDLER(sraiq, 0x1F, 0x18, 0x1D, 0x00000000, > PPC_POWER_BR) > /* sraq - sraq. */ > GEN_HANDLER(sraq, 0x1F, 0x18, 0x1C, 0x00000000, PPC_POWER_BR) > { > - gen_op_load_gpr_T0(rS(ctx->opcode)); > - gen_op_load_gpr_T1(rB(ctx->opcode)); > + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); > + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); > gen_op_POWER_sraq(); > gen_op_store_T0_gpr(rA(ctx->opcode)); > if (unlikely(Rc(ctx->opcode) != 0)) > @@ -4182,8 +4230,8 @@ GEN_HANDLER(sraq, 0x1F, 0x18, 0x1C, 0x00000000, > PPC_POWER_BR) > /* sre - sre. */ > GEN_HANDLER(sre, 0x1F, 0x19, 0x14, 0x00000000, PPC_POWER_BR) > { > - gen_op_load_gpr_T0(rS(ctx->opcode)); > - gen_op_load_gpr_T1(rB(ctx->opcode)); > + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); > + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); > gen_op_POWER_sre(); > gen_op_store_T0_gpr(rA(ctx->opcode)); > if (unlikely(Rc(ctx->opcode) != 0)) > @@ -4193,8 +4241,8 @@ GEN_HANDLER(sre, 0x1F, 0x19, 0x14, 0x00000000, > PPC_POWER_BR) > /* srea - srea. */ > GEN_HANDLER(srea, 0x1F, 0x19, 0x1C, 0x00000000, PPC_POWER_BR) > { > - gen_op_load_gpr_T0(rS(ctx->opcode)); > - gen_op_load_gpr_T1(rB(ctx->opcode)); > + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); > + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); > gen_op_POWER_srea(); > gen_op_store_T0_gpr(rA(ctx->opcode)); > if (unlikely(Rc(ctx->opcode) != 0)) > @@ -4204,8 +4252,8 @@ GEN_HANDLER(srea, 0x1F, 0x19, 0x1C, 0x00000000, > PPC_POWER_BR) > /* sreq */ > GEN_HANDLER(sreq, 0x1F, 0x19, 0x16, 0x00000000, PPC_POWER_BR) > { > - gen_op_load_gpr_T0(rS(ctx->opcode)); > - gen_op_load_gpr_T1(rB(ctx->opcode)); > + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); > + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); > gen_op_POWER_sreq(); > gen_op_store_T0_gpr(rA(ctx->opcode)); > if (unlikely(Rc(ctx->opcode) != 0)) > @@ -4215,7 +4263,7 @@ GEN_HANDLER(sreq, 0x1F, 0x19, 0x16, 0x00000000, > PPC_POWER_BR) > /* sriq */ > GEN_HANDLER(sriq, 0x1F, 0x18, 0x15, 0x00000000, PPC_POWER_BR) > { > - gen_op_load_gpr_T0(rS(ctx->opcode)); > + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); > tcg_gen_movi_tl(cpu_T[1], SH(ctx->opcode)); > gen_op_POWER_srq(); > gen_op_store_T0_gpr(rA(ctx->opcode)); > @@ -4226,8 +4274,8 @@ GEN_HANDLER(sriq, 0x1F, 0x18, 0x15, 0x00000000, > PPC_POWER_BR) > /* srliq */ > GEN_HANDLER(srliq, 0x1F, 0x18, 0x17, 0x00000000, PPC_POWER_BR) > { > - gen_op_load_gpr_T0(rS(ctx->opcode)); > - gen_op_load_gpr_T1(rB(ctx->opcode)); > + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); > + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); > tcg_gen_movi_tl(cpu_T[1], SH(ctx->opcode)); > gen_op_POWER_srlq(); > gen_op_store_T0_gpr(rA(ctx->opcode)); > @@ -4238,8 +4286,8 @@ GEN_HANDLER(srliq, 0x1F, 0x18, 0x17, 0x00000000, > PPC_POWER_BR) > /* srlq */ > GEN_HANDLER(srlq, 0x1F, 0x18, 0x16, 0x00000000, PPC_POWER_BR) > { > - gen_op_load_gpr_T0(rS(ctx->opcode)); > - gen_op_load_gpr_T1(rB(ctx->opcode)); > + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); > + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); > gen_op_POWER_srlq(); > gen_op_store_T0_gpr(rA(ctx->opcode)); > if (unlikely(Rc(ctx->opcode) != 0)) > @@ -4249,8 +4297,8 @@ GEN_HANDLER(srlq, 0x1F, 0x18, 0x16, 0x00000000, > PPC_POWER_BR) > /* srq */ > GEN_HANDLER(srq, 0x1F, 0x18, 0x14, 0x00000000, PPC_POWER_BR) > { > - gen_op_load_gpr_T0(rS(ctx->opcode)); > - gen_op_load_gpr_T1(rB(ctx->opcode)); > + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); > + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); > gen_op_POWER_srq(); > gen_op_store_T0_gpr(rA(ctx->opcode)); > if (unlikely(Rc(ctx->opcode) != 0)) > @@ -4282,7 +4330,7 @@ GEN_HANDLER(mfrom, 0x1F, 0x09, 0x08, 0x03E0F801, > PPC_602_SPEC) > GEN_EXCP_PRIVOPC(ctx); > return; > } > - gen_op_load_gpr_T0(rA(ctx->opcode)); > + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); > gen_op_602_mfrom(); > gen_op_store_T0_gpr(rD(ctx->opcode)); > #endif > @@ -4299,7 +4347,7 @@ GEN_HANDLER2(tlbld_6xx, "tlbld", 0x1F, 0x12, 0x1E, > 0x03FF0001, PPC_6xx_TLB) > GEN_EXCP_PRIVOPC(ctx); > return; > } > - gen_op_load_gpr_T0(rB(ctx->opcode)); > + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rB(ctx->opcode)]); > gen_op_6xx_tlbld(); > #endif > } > @@ -4314,7 +4362,7 @@ GEN_HANDLER2(tlbli_6xx, "tlbli", 0x1F, 0x12, 0x1F, > 0x03FF0001, PPC_6xx_TLB) > GEN_EXCP_PRIVOPC(ctx); > return; > } > - gen_op_load_gpr_T0(rB(ctx->opcode)); > + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rB(ctx->opcode)]); > gen_op_6xx_tlbli(); > #endif > } > @@ -4330,7 +4378,7 @@ GEN_HANDLER2(tlbld_74xx, "tlbld", 0x1F, 0x12, > 0x1E, 0x03FF0001, PPC_74xx_TLB) > GEN_EXCP_PRIVOPC(ctx); > return; > } > - gen_op_load_gpr_T0(rB(ctx->opcode)); > + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rB(ctx->opcode)]); > gen_op_74xx_tlbld(); > #endif > } > @@ -4345,7 +4393,7 @@ GEN_HANDLER2(tlbli_74xx, "tlbli", 0x1F, 0x12, > 0x1F, 0x03FF0001, PPC_74xx_TLB) > GEN_EXCP_PRIVOPC(ctx); > return; > } > - gen_op_load_gpr_T0(rB(ctx->opcode)); > + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rB(ctx->opcode)]); > gen_op_74xx_tlbli(); > #endif > } > @@ -4594,8 +4642,8 @@ static always_inline void gen_405_mulladd_insn > (DisasContext *ctx, > int opc2, int opc3, > int ra, int rb, int rt, > int Rc) > { > - gen_op_load_gpr_T0(ra); > - gen_op_load_gpr_T1(rb); > + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[ra]); > + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rb]); > switch (opc3 & 0x0D) { > case 0x05: > /* macchw - macchw. - macchwo - macchwo. */ > @@ -4646,7 +4694,7 @@ static always_inline void gen_405_mulladd_insn > (DisasContext *ctx, > } > if (opc2 & 0x04) { > /* (n)multiply-and-accumulate (0x0C - 0x0E) */ > - gen_op_load_gpr_T2(rt); > + tcg_gen_mov_tl(cpu_T[2], cpu_gpr[rt]); > tcg_gen_mov_tl(cpu_T[1], cpu_T[0]); > gen_op_405_add_T0_T2(); > } > @@ -4795,7 +4843,7 @@ GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, > PPC_DCR) > return; > } > tcg_gen_movi_tl(cpu_T[0], dcrn); > - gen_op_load_gpr_T1(rS(ctx->opcode)); > + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]); > gen_op_store_dcr(); > #endif > } > @@ -4811,7 +4859,7 @@ GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000000, > PPC_DCRX) > GEN_EXCP_PRIVREG(ctx); > return; > } > - gen_op_load_gpr_T0(rA(ctx->opcode)); > + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); > gen_op_load_dcr(); > gen_op_store_T0_gpr(rD(ctx->opcode)); > /* Note: Rc update flag set leads to undefined state of Rc0 */ > @@ -4829,8 +4877,8 @@ GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000, > PPC_DCRX) > GEN_EXCP_PRIVREG(ctx); > return; > } > - gen_op_load_gpr_T0(rA(ctx->opcode)); > - gen_op_load_gpr_T1(rS(ctx->opcode)); > + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); > + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]); > gen_op_store_dcr(); > /* Note: Rc update flag set leads to undefined state of Rc0 */ > #endif > @@ -4839,7 +4887,7 @@ GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000, > PPC_DCRX) > /* mfdcrux (PPC 460) : user-mode access to DCR */ > GEN_HANDLER(mfdcrux, 0x1F, 0x03, 0x09, 0x00000000, PPC_DCRUX) > { > - gen_op_load_gpr_T0(rA(ctx->opcode)); > + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); > gen_op_load_dcr(); > gen_op_store_T0_gpr(rD(ctx->opcode)); > /* Note: Rc update flag set leads to undefined state of Rc0 */ > @@ -4848,8 +4896,8 @@ GEN_HANDLER(mfdcrux, 0x1F, 0x03, 0x09, 0x00000000, > PPC_DCRUX) > /* mtdcrux (PPC 460) : user-mode access to DCR */ > GEN_HANDLER(mtdcrux, 0x1F, 0x03, 0x0D, 0x00000000, PPC_DCRUX) > { > - gen_op_load_gpr_T0(rA(ctx->opcode)); > - gen_op_load_gpr_T1(rS(ctx->opcode)); > + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); > + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]); > gen_op_store_dcr(); > /* Note: Rc update flag set leads to undefined state of Rc0 */ > } > @@ -4998,12 +5046,12 @@ GEN_HANDLER2(tlbre_40x, "tlbre", 0x1F, 0x12, > 0x1D, 0x00000001, PPC_40x_TLB) > } > switch (rB(ctx->opcode)) { > case 0: > - gen_op_load_gpr_T0(rA(ctx->opcode)); > + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); > gen_op_4xx_tlbre_hi(); > gen_op_store_T0_gpr(rD(ctx->opcode)); > break; > case 1: > - gen_op_load_gpr_T0(rA(ctx->opcode)); > + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); > gen_op_4xx_tlbre_lo(); > gen_op_store_T0_gpr(rD(ctx->opcode)); > break; > @@ -5044,13 +5092,13 @@ GEN_HANDLER2(tlbwe_40x, "tlbwe", 0x1F, 0x12, > 0x1E, 0x00000001, PPC_40x_TLB) > } > switch (rB(ctx->opcode)) { > case 0: > - gen_op_load_gpr_T0(rA(ctx->opcode)); > - gen_op_load_gpr_T1(rS(ctx->opcode)); > + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); > + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]); > gen_op_4xx_tlbwe_hi(); > break; > case 1: > - gen_op_load_gpr_T0(rA(ctx->opcode)); > - gen_op_load_gpr_T1(rS(ctx->opcode)); > + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); > + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]); > gen_op_4xx_tlbwe_lo(); > break; > default: > @@ -5075,7 +5123,7 @@ GEN_HANDLER2(tlbre_440, "tlbre", 0x1F, 0x12, 0x1D, > 0x00000001, PPC_BOOKE) > case 0: > case 1: > case 2: > - gen_op_load_gpr_T0(rA(ctx->opcode)); > + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); > gen_op_440_tlbre(rB(ctx->opcode)); > gen_op_store_T0_gpr(rD(ctx->opcode)); > break; > @@ -5118,8 +5166,8 @@ GEN_HANDLER2(tlbwe_440, "tlbwe", 0x1F, 0x12, 0x1E, > 0x00000001, PPC_BOOKE) > case 0: > case 1: > case 2: > - gen_op_load_gpr_T0(rA(ctx->opcode)); > - gen_op_load_gpr_T1(rS(ctx->opcode)); > + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); > + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]); > gen_op_440_tlbwe(rB(ctx->opcode)); > break; > default: > @@ -5139,7 +5187,7 @@ GEN_HANDLER(wrtee, 0x1F, 0x03, 0x04, 0x000FFC01, > PPC_WRTEE) > GEN_EXCP_PRIVOPC(ctx); > return; > } > - gen_op_load_gpr_T0(rD(ctx->opcode)); > + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rD(ctx->opcode)]); > gen_op_wrte(); > /* Stop translation to have a chance to raise an exception > * if we just set msr_ee to 1 > @@ -5171,8 +5219,8 @@ GEN_HANDLER(wrteei, 0x1F, 0x03, 0x05, 0x000EFC01, > PPC_WRTEE) > /* dlmzb */ > GEN_HANDLER(dlmzb, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC) > { > - gen_op_load_gpr_T0(rS(ctx->opcode)); > - gen_op_load_gpr_T1(rB(ctx->opcode)); > + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); > + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); > gen_op_440_dlmzb(); > gen_op_store_T0_gpr(rA(ctx->opcode)); > gen_op_store_xer_bc(); > @@ -5317,7 +5365,7 @@ static always_inline void gen_addr_spe_imm_index > (DisasContext *ctx, int sh) > if (rA(ctx->opcode) == 0) { > tcg_gen_movi_tl(cpu_T[0], simm << sh); > } else { > - gen_op_load_gpr_T0(rA(ctx->opcode)); > + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); > if (likely(simm != 0)) > gen_op_addi(simm << sh); > } > @@ -5465,8 +5513,8 @@ GEN_SPEOP_ARITH1(evcntlsw); > static always_inline void gen_brinc (DisasContext *ctx) > { > /* Note: brinc is usable even if SPE is disabled */ > - gen_op_load_gpr_T0(rA(ctx->opcode)); > - gen_op_load_gpr_T1(rB(ctx->opcode)); > + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); > + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); > gen_op_brinc(); > gen_op_store_T0_gpr(rD(ctx->opcode)); > } > -- > 1.5.5.1 > > -- .''`. Aurelien Jarno | GPG: 1024D/F1BCDB73 : :' : Debian developer | Electrical Engineer `. `' aurel32@debian.org | aurelien@aurel32.net `- people.debian.org/~aurel32 | www.aurel32.net ^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [Qemu-devel] [PATCH 5/x] ppc: Convert op_load_gpr_{T0, T1, T2} to TCG 2008-09-02 23:20 ` Aurelien Jarno @ 2008-09-03 0:39 ` Andreas Färber 2008-09-03 5:07 ` Aurelien Jarno 0 siblings, 1 reply; 42+ messages in thread From: Andreas Färber @ 2008-09-03 0:39 UTC (permalink / raw) To: Aurelien Jarno; +Cc: qemu-devel Am 03.09.2008 um 01:20 schrieb Aurelien Jarno: > On Wed, Sep 03, 2008 at 12:22:48AM +0200, Andreas Färber wrote: >> + static const char* const gprnames[32] = { >> + "r0", >> + "r1", >> + "r2", >> + "r3", >> + "r4", >> + "r5", >> + "r6", >> + "r7", >> + "r8", >> + "r9", >> + "r10", >> + "r11", >> + "r12", >> + "r13", >> + "r14", >> + "r15", >> + "r16", >> + "r17", >> + "r18", >> + "r19", >> + "r20", >> + "r21", >> + "r22", >> + "r23", >> + "r24", >> + "r25", >> + "r26", >> + "r27", >> + "r28", >> + "r29", >> + "r30", >> + "r31" >> + }; >> + > > You may want to use a sprintf() function instead (see other targets). I based this on SH4. Will check the others. > >> + for (i = 0; i < 32; i++) { >> + cpu_gpr[i] = tcg_global_mem_new(TCG_TYPE_TL, TCG_AREG0, >> + offsetof(CPUState, gpr[i]), >> + gprnames[i]); > > This is most probably wrong given the definition of ppc_gpr_t in > cpu.h: > - 64 bits on 64-bit targets > - 32 bits on 32-bit targets and 32-bit hosts > - *64 bits* on 32-bit targets and 64-bit hosts > > I think it is a bit weird, and I think the best is to modify cpu.h in > order to have ppc_gpr_t matching the target bitness. This might be related to the 64-on-32 issue I just posted about. I don't remember seeing code that makes use of this sophisticated definition though, for non-ppc64 it apparently uses a set of 32-bit gpr and gprh variables. Let's not change ppc_gpr_t for now. > Care to also replace the ops in the same > patch? The related dyngen ops can't be removed yet due to SPE, in case that's what you meant? > It's actually a general request, would nice to have a few more > instructions switched in a patch, to avoid spending to much time in > handling patches. The op_moven before was only separate because it was the first to translate a ~ operation to TCG. This one is actually the largest patch in the series so far... Since it's my first stab at (this side of) TCG and since translate.c has several thousand lines of code, I appreciate early feedback on whether I have to revert my branch and redo a commit/patch. I don't really care if you apply it right away, the review is the more important part and reviewing small chunks is easier, no? I'll rebase tomorrow and start pushing to repo.or.cz, that should make testing and applying patches easier. Andreas ^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [Qemu-devel] [PATCH 5/x] ppc: Convert op_load_gpr_{T0, T1, T2} to TCG 2008-09-03 0:39 ` [Qemu-devel] [PATCH 5/x] ppc: Convert op_load_gpr_{T0, T1, T2} " Andreas Färber @ 2008-09-03 5:07 ` Aurelien Jarno 2008-09-03 10:41 ` Andreas Färber 0 siblings, 1 reply; 42+ messages in thread From: Aurelien Jarno @ 2008-09-03 5:07 UTC (permalink / raw) To: qemu-devel On Wed, Sep 03, 2008 at 02:39:52AM +0200, Andreas Färber wrote: > > Am 03.09.2008 um 01:20 schrieb Aurelien Jarno: > >> On Wed, Sep 03, 2008 at 12:22:48AM +0200, Andreas Färber wrote: >>> + static const char* const gprnames[32] = { >>> + "r0", >>> + "r1", >>> + "r2", >>> + "r3", >>> + "r4", >>> + "r5", >>> + "r6", >>> + "r7", >>> + "r8", >>> + "r9", >>> + "r10", >>> + "r11", >>> + "r12", >>> + "r13", >>> + "r14", >>> + "r15", >>> + "r16", >>> + "r17", >>> + "r18", >>> + "r19", >>> + "r20", >>> + "r21", >>> + "r22", >>> + "r23", >>> + "r24", >>> + "r25", >>> + "r26", >>> + "r27", >>> + "r28", >>> + "r29", >>> + "r30", >>> + "r31" >>> + }; >>> + >> >> You may want to use a sprintf() function instead (see other targets). > > I based this on SH4. Will check the others. > > >> >>> + for (i = 0; i < 32; i++) { >>> + cpu_gpr[i] = tcg_global_mem_new(TCG_TYPE_TL, TCG_AREG0, >>> + offsetof(CPUState, gpr[i]), >>> + gprnames[i]); >> >> This is most probably wrong given the definition of ppc_gpr_t in >> cpu.h: >> - 64 bits on 64-bit targets >> - 32 bits on 32-bit targets and 32-bit hosts >> - *64 bits* on 32-bit targets and 64-bit hosts >> >> I think it is a bit weird, and I think the best is to modify cpu.h in >> order to have ppc_gpr_t matching the target bitness. > > This might be related to the 64-on-32 issue I just posted about. I don't > remember seeing code that makes use of this sophisticated definition > though, for non-ppc64 it apparently uses a set of 32-bit gpr and gprh > variables. Let's not change ppc_gpr_t for now. Well that's different, your previous post is about T_* registers, I am speaking about the GPR registers. And either ppc_gpr_t or the init code of cpu_gpr[i] has to be changed, otherwise you will break existing targets. >> Care to also replace the ops in the same >> patch? Oops sorry I was tired, I forget the most important word. I was asking for also replacing the store ops in the same patch. > The related dyngen ops can't be removed yet due to SPE, in case that's > what you meant? > > >> It's actually a general request, would nice to have a few more >> instructions switched in a patch, to avoid spending to much time in >> handling patches. > > The op_moven before was only separate because it was the first to > translate a ~ operation to TCG. > > This one is actually the largest patch in the series so far... Since > it's my first stab at (this side of) TCG and since translate.c has > several thousand lines of code, I appreciate early feedback on whether I > have to revert my branch and redo a commit/patch. I don't really care if > you apply it right away, the review is the more important part and > reviewing small chunks is easier, no? Well, except that until know they basically corresponds to automatic replacement of a pattern by another. Even if the patch is big, the changes are simple. I agree that for more complex changes, smaller chunks are better. > I'll rebase tomorrow and start pushing to repo.or.cz, that should make > testing and applying patches easier. > > Andreas > > > > -- .''`. Aurelien Jarno | GPG: 1024D/F1BCDB73 : :' : Debian developer | Electrical Engineer `. `' aurel32@debian.org | aurelien@aurel32.net `- people.debian.org/~aurel32 | www.aurel32.net ^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [Qemu-devel] [PATCH 5/x] ppc: Convert op_load_gpr_{T0, T1, T2} to TCG 2008-09-03 5:07 ` Aurelien Jarno @ 2008-09-03 10:41 ` Andreas Färber 2008-09-03 11:28 ` Thiemo Seufer 2008-09-03 12:41 ` Aurélien Jarno 0 siblings, 2 replies; 42+ messages in thread From: Andreas Färber @ 2008-09-03 10:41 UTC (permalink / raw) To: qemu-devel; +Cc: Aurélien Jarno Am 03.09.2008 um 07:07 schrieb Aurelien Jarno: > On Wed, Sep 03, 2008 at 02:39:52AM +0200, Andreas Färber wrote: >> >> Am 03.09.2008 um 01:20 schrieb Aurelien Jarno: >> >>> >>>> + for (i = 0; i < 32; i++) { >>>> + cpu_gpr[i] = tcg_global_mem_new(TCG_TYPE_TL, TCG_AREG0, >>>> + offsetof(CPUState, >>>> gpr[i]), >>>> + gprnames[i]); >>> >>> This is most probably wrong given the definition of ppc_gpr_t in >>> cpu.h: >>> - 64 bits on 64-bit targets >>> - 32 bits on 32-bit targets and 32-bit hosts >>> - *64 bits* on 32-bit targets and 64-bit hosts >>> >>> I think it is a bit weird, and I think the best is to modify cpu.h >>> in >>> order to have ppc_gpr_t matching the target bitness. >> >> This might be related to the 64-on-32 issue I just posted about. I >> don't >> remember seeing code that makes use of this sophisticated definition >> though, for non-ppc64 it apparently uses a set of 32-bit gpr and gprh >> variables. Let's not change ppc_gpr_t for now. > > Well that's different, your previous post is about T_* registers, I am > speaking about the GPR registers. And either ppc_gpr_t or the init > code > of cpu_gpr[i] has to be changed, otherwise you will break existing > targets. I'm quite sure it is related - the issue is that GPR / T TCGv size does not always correspond to tl, and the only problem is the 32-bit target with 64-bit host. Would there be a problem with using i64 in the 32-on-64 case? That is, would it hurt to do i32 TCG operations on i64 variables on a 64-bit host? If not, we could keep tl for the regular instructions and use i64 for ppc64/ppc-on-64 and 2x i32 on ppc-on-32. That sounds more efficient than reverting the ppc_gpr_t optimization and always using 2x i32 independent of the host bitness. We'll need an inlined helper for these any way. Andreas ^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [Qemu-devel] [PATCH 5/x] ppc: Convert op_load_gpr_{T0, T1, T2} to TCG 2008-09-03 10:41 ` Andreas Färber @ 2008-09-03 11:28 ` Thiemo Seufer 2008-09-03 18:07 ` Andreas Färber 2008-09-03 12:41 ` Aurélien Jarno 1 sibling, 1 reply; 42+ messages in thread From: Thiemo Seufer @ 2008-09-03 11:28 UTC (permalink / raw) To: Andreas Färber; +Cc: qemu-devel, Aurélien Jarno Andreas Färber wrote: [snip] > Would there be a problem with using i64 in the 32-on-64 case? That is, > would it hurt to do i32 TCG operations on i64 variables on a 64-bit > host? I did that accidentially for the mips target and got hard to debug segfaults. I believe TCG requires ops and registers to have the same type, abart from explicit conversion functions. Another problem might be sign/zero extensions. Thiemo ^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [Qemu-devel] [PATCH 5/x] ppc: Convert op_load_gpr_{T0, T1, T2} to TCG 2008-09-03 11:28 ` Thiemo Seufer @ 2008-09-03 18:07 ` Andreas Färber 2008-09-03 18:26 ` Blue Swirl 0 siblings, 1 reply; 42+ messages in thread From: Andreas Färber @ 2008-09-03 18:07 UTC (permalink / raw) To: qemu-devel, Thiemo Seufer; +Cc: Aurélien Jarno Am 03.09.2008 um 13:28 schrieb Thiemo Seufer: > Andreas Färber wrote: > [snip] >> Would there be a problem with using i64 in the 32-on-64 case? That >> is, >> would it hurt to do i32 TCG operations on i64 variables on a 64-bit >> host? > > I did that accidentially for the mips target and got hard to debug > segfaults. I believe TCG requires ops and registers to have the > same type, abart from explicit conversion functions. > > Another problem might be sign/zero extensions. tcg-op.h actually uses two i32 ops (one with TCGV_HIGH) to implement i64 ops on 32-bit host. Any suggestion how to get i32 var(s) into i64 without using i32 ops? There appears to be no special TCG function for this. Since it was decided that for a 32-bit guest we should use tl==i32 registers vars, I need to get two of those into an i64 temporary (cpu_T64). Here's what I've pieced together: - for ppc64 just use i64 op - for ppc on 32-bit host use 2x i32 move, w/ TCGV_HIGH and w/o - for ppc on 64-bit host use i32 move + i64 shift + i32 move static always_inline void gen_op_load_gpr64(TCGv t, int reg) { #if defined(TARGET_PPC64) tcg_gen_mov_i64(t, cpu_gpr[reg]); #else #if TCG_TARGET_REG_BITS == 32 tcg_gen_mov_i32(TCGV_HIGH(t), cpu_gprh[reg]); #else tcg_gen_mov_i32(t, cpu_gprh[reg]); tcg_gen_shli_i64(t, t, 32); #endif tcg_gen_mov_i32(t, cpu_gpr[reg]); #endif } Thoughts? Andreas ^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [Qemu-devel] [PATCH 5/x] ppc: Convert op_load_gpr_{T0, T1, T2} to TCG 2008-09-03 18:07 ` Andreas Färber @ 2008-09-03 18:26 ` Blue Swirl 2008-09-03 19:00 ` Andreas Färber 0 siblings, 1 reply; 42+ messages in thread From: Blue Swirl @ 2008-09-03 18:26 UTC (permalink / raw) To: qemu-devel; +Cc: Aurélien Jarno On 9/3/08, Andreas Färber <andreas.faerber@web.de> wrote: > > Am 03.09.2008 um 13:28 schrieb Thiemo Seufer: > > > > Andreas Färber wrote: > > [snip] > > > > > Would there be a problem with using i64 in the 32-on-64 case? That is, > > > would it hurt to do i32 TCG operations on i64 variables on a 64-bit > > > host? > > > > > > > I did that accidentially for the mips target and got hard to debug > > segfaults. I believe TCG requires ops and registers to have the > > same type, abart from explicit conversion functions. > > > > Another problem might be sign/zero extensions. > > > > tcg-op.h actually uses two i32 ops (one with TCGV_HIGH) to implement i64 > ops on 32-bit host. > > Any suggestion how to get i32 var(s) into i64 without using i32 ops? There > appears to be no special TCG function for this. > > Since it was decided that for a 32-bit guest we should use tl==i32 > registers vars, I need to get two of those into an i64 temporary (cpu_T64). > > Here's what I've pieced together: > > - for ppc64 just use i64 op > - for ppc on 32-bit host use 2x i32 move, w/ TCGV_HIGH and w/o > - for ppc on 64-bit host use i32 move + i64 shift + i32 move > > static always_inline void gen_op_load_gpr64(TCGv t, int reg) { > #if defined(TARGET_PPC64) > tcg_gen_mov_i64(t, cpu_gpr[reg]); > #else > #if TCG_TARGET_REG_BITS == 32 > tcg_gen_mov_i32(TCGV_HIGH(t), cpu_gprh[reg]); > #else > tcg_gen_mov_i32(t, cpu_gprh[reg]); > tcg_gen_shli_i64(t, t, 32); > #endif > tcg_gen_mov_i32(t, cpu_gpr[reg]); > #endif > } Can't you use extu_i32_i64 followed by shift and then or? I think you should not use TCGV_HIGH outside tcg directory, it's an implementation detail. ^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [Qemu-devel] [PATCH 5/x] ppc: Convert op_load_gpr_{T0, T1, T2} to TCG 2008-09-03 18:26 ` Blue Swirl @ 2008-09-03 19:00 ` Andreas Färber 2008-09-03 19:12 ` Blue Swirl 2008-09-07 14:22 ` [Qemu-devel] [PATCH 5/x] ppc: Convert op_load_gpr_{T0, T1, T2} " Paul Brook 0 siblings, 2 replies; 42+ messages in thread From: Andreas Färber @ 2008-09-03 19:00 UTC (permalink / raw) To: qemu-devel Am 03.09.2008 um 20:26 schrieb Blue Swirl: > On 9/3/08, Andreas Färber <andreas.faerber@web.de> wrote: >> Here's what I've pieced together: >> >> - for ppc64 just use i64 op >> - for ppc on 32-bit host use 2x i32 move, w/ TCGV_HIGH and w/o >> - for ppc on 64-bit host use i32 move + i64 shift + i32 move >> >> static always_inline void gen_op_load_gpr64(TCGv t, int reg) { >> #if defined(TARGET_PPC64) >> tcg_gen_mov_i64(t, cpu_gpr[reg]); >> #else >> #if TCG_TARGET_REG_BITS == 32 >> tcg_gen_mov_i32(TCGV_HIGH(t), cpu_gprh[reg]); >> #else >> tcg_gen_mov_i32(t, cpu_gprh[reg]); >> tcg_gen_shli_i64(t, t, 32); >> #endif >> tcg_gen_mov_i32(t, cpu_gpr[reg]); >> #endif >> } > > Can't you use extu_i32_i64 followed by shift and then or? I think you > should not use TCGV_HIGH outside tcg directory, it's an implementation > detail. Thanks for the suggestion! You mean like this? static always_inline void gen_load_gpr64(TCGv t, int reg) { #if defined(TARGET_PPC64) tcg_gen_mov_i64(t, cpu_gpr[reg]); #else tcg_gen_extu_i32_i64(t, cpu_gprh[reg]); tcg_gen_shli_i64(t, t, 32); TCGv tmp = tcg_temp_local_new(TCG_TYPE_I64); tcg_gen_extu_i32_i64(tmp, cpu_gpr[reg]); tcg_gen_or_i64(t, t, tmp); tcg_temp_free(tmp); #endif } static always_inline void gen_store_gpr64(int reg, TCGv t) { #if defined(TARGET_PPC64) tcg_gen_mov_i64(cpu_gpr[reg], t); #else tcg_gen_trunc_i64_i32(cpu_gpr[reg], t); TCGv tmp = tcg_temp_local_new(TCG_TYPE_I64); tcg_gen_shri_i64(tmp, t, 32); tcg_gen_trunc_i64_i32(cpu_gprh[reg], tmp); tcg_temp_free(tmp); #endif } Andreas ^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [Qemu-devel] [PATCH 5/x] ppc: Convert op_load_gpr_{T0, T1, T2} to TCG 2008-09-03 19:00 ` Andreas Färber @ 2008-09-03 19:12 ` Blue Swirl 2008-09-03 20:04 ` [Qemu-devel] [PATCH 5/x v2] ppc: Convert GPR moves " Andreas Färber 2008-09-07 14:22 ` [Qemu-devel] [PATCH 5/x] ppc: Convert op_load_gpr_{T0, T1, T2} " Paul Brook 1 sibling, 1 reply; 42+ messages in thread From: Blue Swirl @ 2008-09-03 19:12 UTC (permalink / raw) To: qemu-devel On 9/3/08, Andreas Färber <andreas.faerber@web.de> wrote: > > Am 03.09.2008 um 20:26 schrieb Blue Swirl: > > > > On 9/3/08, Andreas Färber <andreas.faerber@web.de> wrote: > > > > > Here's what I've pieced together: > > > > > > - for ppc64 just use i64 op > > > - for ppc on 32-bit host use 2x i32 move, w/ TCGV_HIGH and w/o > > > - for ppc on 64-bit host use i32 move + i64 shift + i32 move > > > > > > static always_inline void gen_op_load_gpr64(TCGv t, int reg) { > > > #if defined(TARGET_PPC64) > > > tcg_gen_mov_i64(t, cpu_gpr[reg]); > > > #else > > > #if TCG_TARGET_REG_BITS == 32 > > > tcg_gen_mov_i32(TCGV_HIGH(t), cpu_gprh[reg]); > > > #else > > > tcg_gen_mov_i32(t, cpu_gprh[reg]); > > > tcg_gen_shli_i64(t, t, 32); > > > #endif > > > tcg_gen_mov_i32(t, cpu_gpr[reg]); > > > #endif > > > } > > > > > > > Can't you use extu_i32_i64 followed by shift and then or? I think you > > should not use TCGV_HIGH outside tcg directory, it's an implementation > > detail. > > > > > Thanks for the suggestion! You mean like this? > > static always_inline void gen_load_gpr64(TCGv t, int reg) { > #if defined(TARGET_PPC64) > tcg_gen_mov_i64(t, cpu_gpr[reg]); > #else > tcg_gen_extu_i32_i64(t, cpu_gprh[reg]); > tcg_gen_shli_i64(t, t, 32); > TCGv tmp = tcg_temp_local_new(TCG_TYPE_I64); > tcg_gen_extu_i32_i64(tmp, cpu_gpr[reg]); > tcg_gen_or_i64(t, t, tmp); > tcg_temp_free(tmp); > #endif > } > > static always_inline void gen_store_gpr64(int reg, TCGv t) { > #if defined(TARGET_PPC64) > tcg_gen_mov_i64(cpu_gpr[reg], t); > #else > tcg_gen_trunc_i64_i32(cpu_gpr[reg], t); > TCGv tmp = tcg_temp_local_new(TCG_TYPE_I64); > tcg_gen_shri_i64(tmp, t, 32); > tcg_gen_trunc_i64_i32(cpu_gprh[reg], tmp); > tcg_temp_free(tmp); > #endif > } Yes. ^ permalink raw reply [flat|nested] 42+ messages in thread
* [Qemu-devel] [PATCH 5/x v2] ppc: Convert GPR moves to TCG 2008-09-03 19:12 ` Blue Swirl @ 2008-09-03 20:04 ` Andreas Färber 2008-09-04 5:25 ` Aurelien Jarno 2008-09-04 12:24 ` [Qemu-devel] [PATCH 6/x] ppc: Convert Altivec register " Andreas Färber 0 siblings, 2 replies; 42+ messages in thread From: Andreas Färber @ 2008-09-03 20:04 UTC (permalink / raw) To: qemu-devel [-- Attachment #1: Type: text/plain, Size: 626 bytes --] Replace op_load_gpr_{T0,T1,T2} and op_store_{T0,T1,T2} with tcg_gen_mov_tl. Introduce TCG variables cpu_gpr[0..31]. For the SPE extension, assure that ppc_gpr_t is only uint64_t for ppc64. Introduce TCG variables cpu_gprh[0..31] for upper 32 bits on ppc and helpers gen_{load,store}_gpr64. Based on suggestions by Aurelien, Thiemo and Blue. Signed-off-by: Andreas Faerber <andreas.faerber@web.de> --- target-ppc/cpu.h | 12 +- target-ppc/op_template.h | 85 ------ target-ppc/translate.c | 747 +++++++++++++++++++++++ +---------------------- 3 files changed, 390 insertions(+), 454 deletions(-) [-- Attachment #2: 0001-ppc-Convert-GPR-moves-to-TCG.patch --] [-- Type: application/octet-stream, Size: 97322 bytes --] From 32df42f476e7656621c0da3a55c9f54612ab5258 Mon Sep 17 00:00:00 2001 From: =?utf-8?q?Andreas=20F=C3=A4rber?= <andreas.faerber@web.de> Date: Wed, 3 Sep 2008 21:52:00 +0200 Subject: [PATCH] ppc: Convert GPR moves to TCG --- target-ppc/cpu.h | 12 +- target-ppc/op_template.h | 85 ------ target-ppc/translate.c | 747 ++++++++++++++++++++++++---------------------- 3 files changed, 390 insertions(+), 454 deletions(-) diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h index 834c08d..c7291ed 100644 --- a/target-ppc/cpu.h +++ b/target-ppc/cpu.h @@ -33,17 +33,7 @@ typedef uint64_t ppc_gpr_t; #else /* defined (TARGET_PPC64) */ /* PowerPC 32 definitions */ -#if (HOST_LONG_BITS >= 64) -/* When using 64 bits temporary registers, - * we can use 64 bits GPR with no extra cost - * It's even an optimization as this will prevent - * the compiler to do unuseful masking in the micro-ops. - */ -typedef uint64_t ppc_gpr_t; -#else /* (HOST_LONG_BITS >= 64) */ typedef uint32_t ppc_gpr_t; -#endif /* (HOST_LONG_BITS >= 64) */ - #define TARGET_LONG_BITS 32 #if defined(TARGET_PPCEMB) @@ -541,7 +531,7 @@ struct CPUPPCState { /* First are the most commonly used resources * during translated code execution */ -#if (HOST_LONG_BITS == 32) +#if (TARGET_LONG_BITS > HOST_LONG_BITS) || !defined(TARGET_PPC64) /* temporary fixed-point registers * used to emulate 64 bits registers on 32 bits hosts */ diff --git a/target-ppc/op_template.h b/target-ppc/op_template.h index e6d6afa..8c65e49 100644 --- a/target-ppc/op_template.h +++ b/target-ppc/op_template.h @@ -18,91 +18,6 @@ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ -/* General purpose registers moves */ -void OPPROTO glue(op_load_gpr_T0_gpr, REG) (void) -{ - T0 = env->gpr[REG]; - RETURN(); -} - -void OPPROTO glue(op_load_gpr_T1_gpr, REG) (void) -{ - T1 = env->gpr[REG]; - RETURN(); -} - -void OPPROTO glue(op_load_gpr_T2_gpr, REG) (void) -{ - T2 = env->gpr[REG]; - RETURN(); -} - -void OPPROTO glue(op_store_T0_gpr_gpr, REG) (void) -{ - env->gpr[REG] = T0; - RETURN(); -} - -void OPPROTO glue(op_store_T1_gpr_gpr, REG) (void) -{ - env->gpr[REG] = T1; - RETURN(); -} - -#if 0 // unused -void OPPROTO glue(op_store_T2_gpr_gpr, REG) (void) -{ - env->gpr[REG] = T2; - RETURN(); -} -#endif - -/* General purpose registers containing vector operands moves */ -#if !defined(TARGET_PPC64) -void OPPROTO glue(op_load_gpr64_T0_gpr, REG) (void) -{ - T0_64 = (uint64_t)env->gpr[REG] | ((uint64_t)env->gprh[REG] << 32); - RETURN(); -} - -void OPPROTO glue(op_load_gpr64_T1_gpr, REG) (void) -{ - T1_64 = (uint64_t)env->gpr[REG] | ((uint64_t)env->gprh[REG] << 32); - RETURN(); -} - -#if 0 // unused -void OPPROTO glue(op_load_gpr64_T2_gpr, REG) (void) -{ - T2_64 = (uint64_t)env->gpr[REG] | ((uint64_t)env->gprh[REG] << 32); - RETURN(); -} -#endif - -void OPPROTO glue(op_store_T0_gpr64_gpr, REG) (void) -{ - env->gpr[REG] = T0_64; - env->gprh[REG] = T0_64 >> 32; - RETURN(); -} - -void OPPROTO glue(op_store_T1_gpr64_gpr, REG) (void) -{ - env->gpr[REG] = T1_64; - env->gprh[REG] = T1_64 >> 32; - RETURN(); -} - -#if 0 // unused -void OPPROTO glue(op_store_T2_gpr64_gpr, REG) (void) -{ - env->gpr[REG] = T2_64; - env->gprh[REG] = T2_64 >> 32; - RETURN(); -} -#endif -#endif /* !defined(TARGET_PPC64) */ - /* Altivec registers moves */ void OPPROTO glue(op_load_avr_A0_avr, REG) (void) { diff --git a/target-ppc/translate.c b/target-ppc/translate.c index 9068936..8fa6056 100644 --- a/target-ppc/translate.c +++ b/target-ppc/translate.c @@ -44,15 +44,37 @@ /*****************************************************************************/ /* Code translation helpers */ -static TCGv cpu_env, cpu_T[3]; +/* global register indexes */ +static TCGv cpu_env; +static char cpu_reg_names[10*3 + 22*4 +#if !defined(TARGET_PPC64) + + 10*4 + 22*5 +#endif +]; +static TCGv cpu_gpr[32]; +#if !defined(TARGET_PPC64) +static TCGv cpu_gprh[32]; +#endif + +/* dyngen register indexes */ +static TCGv cpu_T[3]; +#if defined(TARGET_PPC64) +#define cpu_T64 cpu_T +#else +static TCGv cpu_T64[3]; +#endif #include "gen-icount.h" void ppc_translate_init(void) { + int i; + char* p; static int done_init = 0; + if (done_init) return; + cpu_env = tcg_global_reg_new(TCG_TYPE_PTR, TCG_AREG0, "env"); #if TARGET_LONG_BITS > HOST_LONG_BITS cpu_T[0] = tcg_global_mem_new(TCG_TYPE_TL, @@ -66,6 +88,31 @@ void ppc_translate_init(void) cpu_T[1] = tcg_global_reg_new(TCG_TYPE_TL, TCG_AREG2, "T1"); cpu_T[2] = tcg_global_reg_new(TCG_TYPE_TL, TCG_AREG3, "T2"); #endif +#if !defined(TARGET_PPC64) + cpu_T64[0] = tcg_global_mem_new(TCG_TYPE_I64, + TCG_AREG0, offsetof(CPUState, t0), + "T0_64"); + cpu_T64[1] = tcg_global_mem_new(TCG_TYPE_I64, + TCG_AREG0, offsetof(CPUState, t1), + "T1_64"); + cpu_T64[2] = tcg_global_mem_new(TCG_TYPE_I64, + TCG_AREG0, offsetof(CPUState, t2), + "T2_64"); +#endif + + p = cpu_reg_names; + for (i = 0; i < 32; i++) { + sprintf(p, "r%d", i); + cpu_gpr[i] = tcg_global_mem_new(TCG_TYPE_TL, + TCG_AREG0, offsetof(CPUState, gpr[i]), p); + p += (i < 10) ? 3 : 4; +#if !defined(TARGET_PPC64) + sprintf(p, "r%dH", i); + cpu_gprh[i] = tcg_global_mem_new(TCG_TYPE_I32, + TCG_AREG0, offsetof(CPUState, gprh[i]), p); + p += (i < 10) ? 4 : 5; +#endif + } /* register helpers */ #undef DEF_HELPER @@ -126,17 +173,6 @@ GEN8(gen_op_store_T0_crf, gen_op_store_T0_crf_crf); GEN8(gen_op_store_T1_crf, gen_op_store_T1_crf_crf); #endif -/* General purpose registers moves */ -GEN32(gen_op_load_gpr_T0, gen_op_load_gpr_T0_gpr); -GEN32(gen_op_load_gpr_T1, gen_op_load_gpr_T1_gpr); -GEN32(gen_op_load_gpr_T2, gen_op_load_gpr_T2_gpr); - -GEN32(gen_op_store_T0_gpr, gen_op_store_T0_gpr_gpr); -GEN32(gen_op_store_T1_gpr, gen_op_store_T1_gpr_gpr); -#if 0 // unused -GEN32(gen_op_store_T2_gpr, gen_op_store_T2_gpr_gpr); -#endif - /* floating point registers moves */ GEN32(gen_op_load_fpr_FT0, gen_op_load_fpr_FT0_fpr); GEN32(gen_op_load_fpr_FT1, gen_op_load_fpr_FT1_fpr); @@ -667,10 +703,10 @@ static opc_handler_t invalid_handler = { #define __GEN_INT_ARITH2(name, opc1, opc2, opc3, inval, type) \ GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \ { \ - gen_op_load_gpr_T0(rA(ctx->opcode)); \ - gen_op_load_gpr_T1(rB(ctx->opcode)); \ + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); \ + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); \ gen_op_##name(); \ - gen_op_store_T0_gpr(rD(ctx->opcode)); \ + tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]); \ if (unlikely(Rc(ctx->opcode) != 0)) \ gen_set_Rc0(ctx); \ } @@ -678,10 +714,10 @@ GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \ #define __GEN_INT_ARITH2_O(name, opc1, opc2, opc3, inval, type) \ GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \ { \ - gen_op_load_gpr_T0(rA(ctx->opcode)); \ - gen_op_load_gpr_T1(rB(ctx->opcode)); \ + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); \ + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); \ gen_op_##name(); \ - gen_op_store_T0_gpr(rD(ctx->opcode)); \ + tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]); \ if (unlikely(Rc(ctx->opcode) != 0)) \ gen_set_Rc0(ctx); \ } @@ -689,18 +725,18 @@ GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \ #define __GEN_INT_ARITH1(name, opc1, opc2, opc3, type) \ GEN_HANDLER(name, opc1, opc2, opc3, 0x0000F800, type) \ { \ - gen_op_load_gpr_T0(rA(ctx->opcode)); \ + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); \ gen_op_##name(); \ - gen_op_store_T0_gpr(rD(ctx->opcode)); \ + tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]); \ if (unlikely(Rc(ctx->opcode) != 0)) \ gen_set_Rc0(ctx); \ } #define __GEN_INT_ARITH1_O(name, opc1, opc2, opc3, type) \ GEN_HANDLER(name, opc1, opc2, opc3, 0x0000F800, type) \ { \ - gen_op_load_gpr_T0(rA(ctx->opcode)); \ + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); \ gen_op_##name(); \ - gen_op_store_T0_gpr(rD(ctx->opcode)); \ + tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]); \ if (unlikely(Rc(ctx->opcode) != 0)) \ gen_set_Rc0(ctx); \ } @@ -723,13 +759,13 @@ __GEN_INT_ARITH1_O(name##o, opc1, opc2, opc3 | 0x10, type) #define __GEN_INT_ARITH2_64(name, opc1, opc2, opc3, inval, type) \ GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \ { \ - gen_op_load_gpr_T0(rA(ctx->opcode)); \ - gen_op_load_gpr_T1(rB(ctx->opcode)); \ + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); \ + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); \ if (ctx->sf_mode) \ gen_op_##name##_64(); \ else \ gen_op_##name(); \ - gen_op_store_T0_gpr(rD(ctx->opcode)); \ + tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]); \ if (unlikely(Rc(ctx->opcode) != 0)) \ gen_set_Rc0(ctx); \ } @@ -737,13 +773,13 @@ GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \ #define __GEN_INT_ARITH2_O_64(name, opc1, opc2, opc3, inval, type) \ GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \ { \ - gen_op_load_gpr_T0(rA(ctx->opcode)); \ - gen_op_load_gpr_T1(rB(ctx->opcode)); \ + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); \ + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); \ if (ctx->sf_mode) \ gen_op_##name##_64(); \ else \ gen_op_##name(); \ - gen_op_store_T0_gpr(rD(ctx->opcode)); \ + tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]); \ if (unlikely(Rc(ctx->opcode) != 0)) \ gen_set_Rc0(ctx); \ } @@ -751,24 +787,24 @@ GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \ #define __GEN_INT_ARITH1_64(name, opc1, opc2, opc3, type) \ GEN_HANDLER(name, opc1, opc2, opc3, 0x0000F800, type) \ { \ - gen_op_load_gpr_T0(rA(ctx->opcode)); \ + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); \ if (ctx->sf_mode) \ gen_op_##name##_64(); \ else \ gen_op_##name(); \ - gen_op_store_T0_gpr(rD(ctx->opcode)); \ + tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]); \ if (unlikely(Rc(ctx->opcode) != 0)) \ gen_set_Rc0(ctx); \ } #define __GEN_INT_ARITH1_O_64(name, opc1, opc2, opc3, type) \ GEN_HANDLER(name, opc1, opc2, opc3, 0x0000F800, type) \ { \ - gen_op_load_gpr_T0(rA(ctx->opcode)); \ + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); \ if (ctx->sf_mode) \ gen_op_##name##_64(); \ else \ gen_op_##name(); \ - gen_op_store_T0_gpr(rD(ctx->opcode)); \ + tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]); \ if (unlikely(Rc(ctx->opcode) != 0)) \ gen_set_Rc0(ctx); \ } @@ -986,18 +1022,18 @@ GEN_HANDLER(addi, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) /* li case */ tcg_gen_movi_tl(cpu_T[0], simm); } else { - gen_op_load_gpr_T0(rA(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); if (likely(simm != 0)) gen_op_addi(simm); } - gen_op_store_T0_gpr(rD(ctx->opcode)); + tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]); } /* addic */ GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) { target_long simm = SIMM(ctx->opcode); - gen_op_load_gpr_T0(rA(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); if (likely(simm != 0)) { tcg_gen_mov_tl(cpu_T[2], cpu_T[0]); gen_op_addi(simm); @@ -1010,14 +1046,14 @@ GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) } else { gen_op_clear_xer_ca(); } - gen_op_store_T0_gpr(rD(ctx->opcode)); + tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]); } /* addic. */ GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) { target_long simm = SIMM(ctx->opcode); - gen_op_load_gpr_T0(rA(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); if (likely(simm != 0)) { tcg_gen_mov_tl(cpu_T[2], cpu_T[0]); gen_op_addi(simm); @@ -1030,7 +1066,7 @@ GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) } else { gen_op_clear_xer_ca(); } - gen_op_store_T0_gpr(rD(ctx->opcode)); + tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]); gen_set_Rc0(ctx); } /* addis */ @@ -1042,30 +1078,30 @@ GEN_HANDLER(addis, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) /* lis case */ tcg_gen_movi_tl(cpu_T[0], simm << 16); } else { - gen_op_load_gpr_T0(rA(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); if (likely(simm != 0)) gen_op_addi(simm << 16); } - gen_op_store_T0_gpr(rD(ctx->opcode)); + tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]); } /* mulli */ GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) { - gen_op_load_gpr_T0(rA(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); gen_op_mulli(SIMM(ctx->opcode)); - gen_op_store_T0_gpr(rD(ctx->opcode)); + tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]); } /* subfic */ GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) { - gen_op_load_gpr_T0(rA(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); #if defined(TARGET_PPC64) if (ctx->sf_mode) gen_op_subfic_64(SIMM(ctx->opcode)); else #endif gen_op_subfic(SIMM(ctx->opcode)); - gen_op_store_T0_gpr(rD(ctx->opcode)); + tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]); } #if defined(TARGET_PPC64) @@ -1086,8 +1122,8 @@ GEN_INT_ARITH2 (divdu, 0x1F, 0x09, 0x0E, PPC_64B); #define GEN_CMP(name, opc, type) \ GEN_HANDLER(name, 0x1F, 0x00, opc, 0x00400000, type) \ { \ - gen_op_load_gpr_T0(rA(ctx->opcode)); \ - gen_op_load_gpr_T1(rB(ctx->opcode)); \ + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); \ + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); \ if (ctx->sf_mode && (ctx->opcode & 0x00200000)) \ gen_op_##name##_64(); \ else \ @@ -1098,8 +1134,8 @@ GEN_HANDLER(name, 0x1F, 0x00, opc, 0x00400000, type) \ #define GEN_CMP(name, opc, type) \ GEN_HANDLER(name, 0x1F, 0x00, opc, 0x00400000, type) \ { \ - gen_op_load_gpr_T0(rA(ctx->opcode)); \ - gen_op_load_gpr_T1(rB(ctx->opcode)); \ + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); \ + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); \ gen_op_##name(); \ gen_op_store_T0_crf(crfD(ctx->opcode)); \ } @@ -1110,7 +1146,7 @@ GEN_CMP(cmp, 0x00, PPC_INTEGER); /* cmpi */ GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER) { - gen_op_load_gpr_T0(rA(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); #if defined(TARGET_PPC64) if (ctx->sf_mode && (ctx->opcode & 0x00200000)) gen_op_cmpi_64(SIMM(ctx->opcode)); @@ -1124,7 +1160,7 @@ GEN_CMP(cmpl, 0x01, PPC_INTEGER); /* cmpli */ GEN_HANDLER(cmpli, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER) { - gen_op_load_gpr_T0(rA(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); #if defined(TARGET_PPC64) if (ctx->sf_mode && (ctx->opcode & 0x00200000)) gen_op_cmpli_64(UIMM(ctx->opcode)); @@ -1143,24 +1179,24 @@ GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL) if (rA(ctx->opcode) == 0) { tcg_gen_movi_tl(cpu_T[0], 0); } else { - gen_op_load_gpr_T1(rA(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rA(ctx->opcode)]); } - gen_op_load_gpr_T2(rB(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[2], cpu_gpr[rB(ctx->opcode)]); mask = 1 << (3 - (bi & 0x03)); gen_op_load_crf_T0(bi >> 2); gen_op_test_true(mask); gen_op_isel(); - gen_op_store_T0_gpr(rD(ctx->opcode)); + tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]); } /*** Integer logical ***/ #define __GEN_LOGICAL2(name, opc2, opc3, type) \ GEN_HANDLER(name, 0x1F, opc2, opc3, 0x00000000, type) \ { \ - gen_op_load_gpr_T0(rS(ctx->opcode)); \ - gen_op_load_gpr_T1(rB(ctx->opcode)); \ + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); \ + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); \ gen_op_##name(); \ - gen_op_store_T0_gpr(rA(ctx->opcode)); \ + tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]); \ if (unlikely(Rc(ctx->opcode) != 0)) \ gen_set_Rc0(ctx); \ } @@ -1170,9 +1206,9 @@ __GEN_LOGICAL2(name, 0x1C, opc, type) #define GEN_LOGICAL1(name, opc, type) \ GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type) \ { \ - gen_op_load_gpr_T0(rS(ctx->opcode)); \ + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); \ gen_op_##name(); \ - gen_op_store_T0_gpr(rA(ctx->opcode)); \ + tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]); \ if (unlikely(Rc(ctx->opcode) != 0)) \ gen_set_Rc0(ctx); \ } @@ -1184,17 +1220,17 @@ GEN_LOGICAL2(andc, 0x01, PPC_INTEGER); /* andi. */ GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) { - gen_op_load_gpr_T0(rS(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); gen_op_andi_T0(UIMM(ctx->opcode)); - gen_op_store_T0_gpr(rA(ctx->opcode)); + tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]); gen_set_Rc0(ctx); } /* andis. */ GEN_HANDLER2(andis_, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) { - gen_op_load_gpr_T0(rS(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); gen_op_andi_T0(UIMM(ctx->opcode) << 16); - gen_op_store_T0_gpr(rA(ctx->opcode)); + tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]); gen_set_Rc0(ctx); } @@ -1221,16 +1257,16 @@ GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER) rb = rB(ctx->opcode); /* Optimisation for mr. ri case */ if (rs != ra || rs != rb) { - gen_op_load_gpr_T0(rs); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rs]); if (rs != rb) { - gen_op_load_gpr_T1(rb); + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rb]); gen_op_or(); } - gen_op_store_T0_gpr(ra); + tcg_gen_mov_tl(cpu_gpr[ra], cpu_T[0]); if (unlikely(Rc(ctx->opcode) != 0)) gen_set_Rc0(ctx); } else if (unlikely(Rc(ctx->opcode) != 0)) { - gen_op_load_gpr_T0(rs); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rs]); gen_set_Rc0(ctx); #if defined(TARGET_PPC64) } else { @@ -1286,15 +1322,15 @@ GEN_LOGICAL2(orc, 0x0C, PPC_INTEGER); /* xor & xor. */ GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER) { - gen_op_load_gpr_T0(rS(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); /* Optimisation for "set to zero" case */ if (rS(ctx->opcode) != rB(ctx->opcode)) { - gen_op_load_gpr_T1(rB(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); gen_op_xor(); } else { tcg_gen_movi_tl(cpu_T[0], 0); } - gen_op_store_T0_gpr(rA(ctx->opcode)); + tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]); if (unlikely(Rc(ctx->opcode) != 0)) gen_set_Rc0(ctx); } @@ -1308,10 +1344,10 @@ GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) /* XXX: should handle special NOPs for POWER series */ return; } - gen_op_load_gpr_T0(rS(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); if (likely(uimm != 0)) gen_op_ori(uimm); - gen_op_store_T0_gpr(rA(ctx->opcode)); + tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]); } /* oris */ GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) @@ -1322,10 +1358,10 @@ GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) /* NOP */ return; } - gen_op_load_gpr_T0(rS(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); if (likely(uimm != 0)) gen_op_ori(uimm << 16); - gen_op_store_T0_gpr(rA(ctx->opcode)); + tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]); } /* xori */ GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) @@ -1336,10 +1372,10 @@ GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) /* NOP */ return; } - gen_op_load_gpr_T0(rS(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); if (likely(uimm != 0)) gen_op_xori(uimm); - gen_op_store_T0_gpr(rA(ctx->opcode)); + tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]); } /* xoris */ @@ -1351,23 +1387,23 @@ GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) /* NOP */ return; } - gen_op_load_gpr_T0(rS(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); if (likely(uimm != 0)) gen_op_xori(uimm << 16); - gen_op_store_T0_gpr(rA(ctx->opcode)); + tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]); } /* popcntb : PowerPC 2.03 specification */ GEN_HANDLER(popcntb, 0x1F, 0x03, 0x03, 0x0000F801, PPC_POPCNTB) { - gen_op_load_gpr_T0(rS(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); #if defined(TARGET_PPC64) if (ctx->sf_mode) gen_op_popcntb_64(); else #endif gen_op_popcntb(); - gen_op_store_T0_gpr(rA(ctx->opcode)); + tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]); } #if defined(TARGET_PPC64) @@ -1389,18 +1425,18 @@ GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) sh = SH(ctx->opcode); if (likely(sh == 0)) { if (likely(mb == 0 && me == 31)) { - gen_op_load_gpr_T0(rS(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); goto do_store; } else if (likely(mb == 31 && me == 0)) { - gen_op_load_gpr_T0(rA(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); goto do_store; } - gen_op_load_gpr_T0(rS(ctx->opcode)); - gen_op_load_gpr_T1(rA(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rA(ctx->opcode)]); goto do_mask; } - gen_op_load_gpr_T0(rS(ctx->opcode)); - gen_op_load_gpr_T1(rA(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rA(ctx->opcode)]); gen_op_rotli32_T0(SH(ctx->opcode)); do_mask: #if defined(TARGET_PPC64) @@ -1412,7 +1448,7 @@ GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) gen_op_andi_T1(~mask); gen_op_or(); do_store: - gen_op_store_T0_gpr(rA(ctx->opcode)); + tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]); if (unlikely(Rc(ctx->opcode) != 0)) gen_set_Rc0(ctx); } @@ -1424,7 +1460,7 @@ GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) sh = SH(ctx->opcode); mb = MB(ctx->opcode); me = ME(ctx->opcode); - gen_op_load_gpr_T0(rS(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); if (likely(sh == 0)) { goto do_mask; } @@ -1450,7 +1486,7 @@ GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) #endif gen_op_andi_T0(MASK(mb, me)); do_store: - gen_op_store_T0_gpr(rA(ctx->opcode)); + tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]); if (unlikely(Rc(ctx->opcode) != 0)) gen_set_Rc0(ctx); } @@ -1461,8 +1497,8 @@ GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) mb = MB(ctx->opcode); me = ME(ctx->opcode); - gen_op_load_gpr_T0(rS(ctx->opcode)); - gen_op_load_gpr_T1(rB(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); gen_op_rotl32_T0_T1(); if (unlikely(mb != 0 || me != 31)) { #if defined(TARGET_PPC64) @@ -1471,7 +1507,7 @@ GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) #endif gen_op_andi_T0(MASK(mb, me)); } - gen_op_store_T0_gpr(rA(ctx->opcode)); + tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]); if (unlikely(Rc(ctx->opcode) != 0)) gen_set_Rc0(ctx); } @@ -1527,7 +1563,7 @@ static always_inline void gen_andi_T1_64 (DisasContext *ctx, uint64_t mask) static always_inline void gen_rldinm (DisasContext *ctx, uint32_t mb, uint32_t me, uint32_t sh) { - gen_op_load_gpr_T0(rS(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); if (likely(sh == 0)) { goto do_mask; } @@ -1549,7 +1585,7 @@ static always_inline void gen_rldinm (DisasContext *ctx, uint32_t mb, do_mask: gen_andi_T0_64(ctx, MASK(mb, me)); do_store: - gen_op_store_T0_gpr(rA(ctx->opcode)); + tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]); if (unlikely(Rc(ctx->opcode) != 0)) gen_set_Rc0(ctx); } @@ -1587,13 +1623,13 @@ GEN_PPC64_R4(rldic, 0x1E, 0x04); static always_inline void gen_rldnm (DisasContext *ctx, uint32_t mb, uint32_t me) { - gen_op_load_gpr_T0(rS(ctx->opcode)); - gen_op_load_gpr_T1(rB(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); gen_op_rotl64_T0_T1(); if (unlikely(mb != 0 || me != 63)) { gen_andi_T0_64(ctx, MASK(mb, me)); } - gen_op_store_T0_gpr(rA(ctx->opcode)); + tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]); if (unlikely(Rc(ctx->opcode) != 0)) gen_set_Rc0(ctx); } @@ -1627,15 +1663,15 @@ static always_inline void gen_rldimi (DisasContext *ctx, int mbn, int shn) me = 63 - sh; if (likely(sh == 0)) { if (likely(mb == 0)) { - gen_op_load_gpr_T0(rS(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); goto do_store; } - gen_op_load_gpr_T0(rS(ctx->opcode)); - gen_op_load_gpr_T1(rA(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rA(ctx->opcode)]); goto do_mask; } - gen_op_load_gpr_T0(rS(ctx->opcode)); - gen_op_load_gpr_T1(rA(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rA(ctx->opcode)]); gen_op_rotli64_T0(sh); do_mask: mask = MASK(mb, me); @@ -1643,7 +1679,7 @@ static always_inline void gen_rldimi (DisasContext *ctx, int mbn, int shn) gen_andi_T1_64(ctx, ~mask); gen_op_or(); do_store: - gen_op_store_T0_gpr(rA(ctx->opcode)); + tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]); if (unlikely(Rc(ctx->opcode) != 0)) gen_set_Rc0(ctx); } @@ -1659,7 +1695,7 @@ __GEN_LOGICAL2(sraw, 0x18, 0x18, PPC_INTEGER); GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER) { int mb, me; - gen_op_load_gpr_T0(rS(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); if (SH(ctx->opcode) != 0) { tcg_gen_mov_tl(cpu_T[1], cpu_T[0]); mb = 32 - SH(ctx->opcode); @@ -1670,7 +1706,7 @@ GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER) #endif gen_op_srawi(SH(ctx->opcode), MASK(mb, me)); } - gen_op_store_T0_gpr(rA(ctx->opcode)); + tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]); if (unlikely(Rc(ctx->opcode) != 0)) gen_set_Rc0(ctx); } @@ -1688,7 +1724,7 @@ static always_inline void gen_sradi (DisasContext *ctx, int n) uint64_t mask; int sh, mb, me; - gen_op_load_gpr_T0(rS(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); sh = SH(ctx->opcode) + (n << 5); if (sh != 0) { tcg_gen_mov_tl(cpu_T[1], cpu_T[0]); @@ -1697,7 +1733,7 @@ static always_inline void gen_sradi (DisasContext *ctx, int n) mask = MASK(mb, me); gen_op_sradi(sh, mask >> 32, mask); } - gen_op_store_T0_gpr(rA(ctx->opcode)); + tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]); if (unlikely(Rc(ctx->opcode) != 0)) gen_set_Rc0(ctx); } @@ -2082,7 +2118,7 @@ static always_inline void gen_addr_imm_index (DisasContext *ctx, if (rA(ctx->opcode) == 0) { tcg_gen_movi_tl(cpu_T[0], simm); } else { - gen_op_load_gpr_T0(rA(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); if (likely(simm != 0)) gen_op_addi(simm); } @@ -2094,10 +2130,10 @@ static always_inline void gen_addr_imm_index (DisasContext *ctx, static always_inline void gen_addr_reg_index (DisasContext *ctx) { if (rA(ctx->opcode) == 0) { - gen_op_load_gpr_T0(rB(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rB(ctx->opcode)]); } else { - gen_op_load_gpr_T0(rA(ctx->opcode)); - gen_op_load_gpr_T1(rB(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); gen_op_add(); } #ifdef DEBUG_MEMORY_ACCESSES @@ -2110,7 +2146,7 @@ static always_inline void gen_addr_register (DisasContext *ctx) if (rA(ctx->opcode) == 0) { tcg_gen_movi_tl(cpu_T[0], 0); } else { - gen_op_load_gpr_T0(rA(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); } #ifdef DEBUG_MEMORY_ACCESSES gen_op_print_mem_EA(); @@ -2181,7 +2217,7 @@ GEN_HANDLER(l##width, opc, 0xFF, 0xFF, 0x00000000, type) \ { \ gen_addr_imm_index(ctx, 0); \ op_ldst(l##width); \ - gen_op_store_T1_gpr(rD(ctx->opcode)); \ + tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[1]); \ } #define GEN_LDU(width, opc, type) \ @@ -2197,8 +2233,8 @@ GEN_HANDLER(l##width##u, opc, 0xFF, 0xFF, 0x00000000, type) \ else \ gen_addr_imm_index(ctx, 0); \ op_ldst(l##width); \ - gen_op_store_T1_gpr(rD(ctx->opcode)); \ - gen_op_store_T0_gpr(rA(ctx->opcode)); \ + tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[1]); \ + tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]); \ } #define GEN_LDUX(width, opc2, opc3, type) \ @@ -2211,8 +2247,8 @@ GEN_HANDLER(l##width##ux, 0x1F, opc2, opc3, 0x00000001, type) \ } \ gen_addr_reg_index(ctx); \ op_ldst(l##width); \ - gen_op_store_T1_gpr(rD(ctx->opcode)); \ - gen_op_store_T0_gpr(rA(ctx->opcode)); \ + tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[1]); \ + tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]); \ } #define GEN_LDX(width, opc2, opc3, type) \ @@ -2220,7 +2256,7 @@ GEN_HANDLER(l##width##x, 0x1F, opc2, opc3, 0x00000001, type) \ { \ gen_addr_reg_index(ctx); \ op_ldst(l##width); \ - gen_op_store_T1_gpr(rD(ctx->opcode)); \ + tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[1]); \ } #define GEN_LDS(width, op, type) \ @@ -2266,9 +2302,9 @@ GEN_HANDLER(ld, 0x3A, 0xFF, 0xFF, 0x00000000, PPC_64B) /* ld - ldu */ op_ldst(ld); } - gen_op_store_T1_gpr(rD(ctx->opcode)); + tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[1]); if (Rc(ctx->opcode)) - gen_op_store_T0_gpr(rA(ctx->opcode)); + tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]); } /* lq */ GEN_HANDLER(lq, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX) @@ -2296,10 +2332,10 @@ GEN_HANDLER(lq, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX) } gen_addr_imm_index(ctx, 0x0F); op_ldst(ld); - gen_op_store_T1_gpr(rd); + tcg_gen_mov_tl(cpu_gpr[rd], cpu_T[1]); gen_op_addi(8); op_ldst(ld); - gen_op_store_T1_gpr(rd + 1); + tcg_gen_mov_tl(cpu_gpr[rd + 1], cpu_T[1]); #endif } #endif @@ -2309,7 +2345,7 @@ GEN_HANDLER(lq, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX) GEN_HANDLER(st##width, opc, 0xFF, 0xFF, 0x00000000, type) \ { \ gen_addr_imm_index(ctx, 0); \ - gen_op_load_gpr_T1(rS(ctx->opcode)); \ + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]); \ op_ldst(st##width); \ } @@ -2324,9 +2360,9 @@ GEN_HANDLER(st##width##u, opc, 0xFF, 0xFF, 0x00000000, type) \ gen_addr_imm_index(ctx, 0x03); \ else \ gen_addr_imm_index(ctx, 0); \ - gen_op_load_gpr_T1(rS(ctx->opcode)); \ + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]); \ op_ldst(st##width); \ - gen_op_store_T0_gpr(rA(ctx->opcode)); \ + tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]); \ } #define GEN_STUX(width, opc2, opc3, type) \ @@ -2337,16 +2373,16 @@ GEN_HANDLER(st##width##ux, 0x1F, opc2, opc3, 0x00000001, type) \ return; \ } \ gen_addr_reg_index(ctx); \ - gen_op_load_gpr_T1(rS(ctx->opcode)); \ + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]); \ op_ldst(st##width); \ - gen_op_store_T0_gpr(rA(ctx->opcode)); \ + tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]); \ } #define GEN_STX(width, opc2, opc3, type) \ GEN_HANDLER(st##width##x, 0x1F, opc2, opc3, 0x00000001, type) \ { \ gen_addr_reg_index(ctx); \ - gen_op_load_gpr_T1(rS(ctx->opcode)); \ + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]); \ op_ldst(st##width); \ } @@ -2391,10 +2427,10 @@ GEN_HANDLER(std, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B) return; } gen_addr_imm_index(ctx, 0x03); - gen_op_load_gpr_T1(rs); + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rs]); op_ldst(std); gen_op_addi(8); - gen_op_load_gpr_T1(rs + 1); + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rs + 1]); op_ldst(std); #endif } else { @@ -2406,10 +2442,10 @@ GEN_HANDLER(std, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B) } } gen_addr_imm_index(ctx, 0x03); - gen_op_load_gpr_T1(rs); + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rs]); op_ldst(std); if (Rc(ctx->opcode)) - gen_op_store_T0_gpr(rA(ctx->opcode)); + tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]); } } #endif @@ -2590,7 +2626,7 @@ GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000001, PPC_RES) gen_update_nip(ctx, ctx->nip - 4); gen_addr_reg_index(ctx); op_lwarx(); - gen_op_store_T1_gpr(rD(ctx->opcode)); + tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[1]); } /* stwcx. */ @@ -2599,7 +2635,7 @@ GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES) /* NIP cannot be restored if the memory exception comes from an helper */ gen_update_nip(ctx, ctx->nip - 4); gen_addr_reg_index(ctx); - gen_op_load_gpr_T1(rS(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]); op_stwcx(); } @@ -2620,7 +2656,7 @@ GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000001, PPC_64B) gen_update_nip(ctx, ctx->nip - 4); gen_addr_reg_index(ctx); op_ldarx(); - gen_op_store_T1_gpr(rD(ctx->opcode)); + tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[1]); } /* stdcx. */ @@ -2629,7 +2665,7 @@ GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B) /* NIP cannot be restored if the memory exception comes from an helper */ gen_update_nip(ctx, ctx->nip - 4); gen_addr_reg_index(ctx); - gen_op_load_gpr_T1(rS(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]); op_stdcx(); } #endif /* defined(TARGET_PPC64) */ @@ -2674,7 +2710,7 @@ GEN_HANDLER(l##width##u, opc, 0xFF, 0xFF, 0x00000000, type) \ gen_addr_imm_index(ctx, 0); \ op_ldst(l##width); \ gen_op_store_FT0_fpr(rD(ctx->opcode)); \ - gen_op_store_T0_gpr(rA(ctx->opcode)); \ + tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]); \ } #define GEN_LDUXF(width, opc, type) \ @@ -2691,7 +2727,7 @@ GEN_HANDLER(l##width##ux, 0x1F, 0x17, opc, 0x00000001, type) \ gen_addr_reg_index(ctx); \ op_ldst(l##width); \ gen_op_store_FT0_fpr(rD(ctx->opcode)); \ - gen_op_store_T0_gpr(rA(ctx->opcode)); \ + tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]); \ } #define GEN_LDXF(width, opc2, opc3, type) \ @@ -2745,7 +2781,7 @@ GEN_HANDLER(st##width##u, opc, 0xFF, 0xFF, 0x00000000, type) \ gen_addr_imm_index(ctx, 0); \ gen_op_load_fpr_FT0(rS(ctx->opcode)); \ op_ldst(st##width); \ - gen_op_store_T0_gpr(rA(ctx->opcode)); \ + tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]); \ } #define GEN_STUXF(width, opc, type) \ @@ -2762,7 +2798,7 @@ GEN_HANDLER(st##width##ux, 0x1F, 0x17, opc, 0x00000001, type) \ gen_addr_reg_index(ctx); \ gen_op_load_fpr_FT0(rS(ctx->opcode)); \ op_ldst(st##width); \ - gen_op_store_T0_gpr(rA(ctx->opcode)); \ + tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]); \ } #define GEN_STXF(width, opc2, opc3, type) \ @@ -3154,8 +3190,8 @@ GEN_HANDLER(sc, 0x11, 0xFF, 0xFF, 0x03FFF01D, PPC_FLOW) /* tw */ GEN_HANDLER(tw, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW) { - gen_op_load_gpr_T0(rA(ctx->opcode)); - gen_op_load_gpr_T1(rB(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); /* Update the nip since this might generate a trap exception */ gen_update_nip(ctx, ctx->nip); gen_op_tw(TO(ctx->opcode)); @@ -3164,7 +3200,7 @@ GEN_HANDLER(tw, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW) /* twi */ GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW) { - gen_op_load_gpr_T0(rA(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); tcg_gen_movi_tl(cpu_T[1], SIMM(ctx->opcode)); /* Update the nip since this might generate a trap exception */ gen_update_nip(ctx, ctx->nip); @@ -3175,8 +3211,8 @@ GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW) /* td */ GEN_HANDLER(td, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B) { - gen_op_load_gpr_T0(rA(ctx->opcode)); - gen_op_load_gpr_T1(rB(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); /* Update the nip since this might generate a trap exception */ gen_update_nip(ctx, ctx->nip); gen_op_td(TO(ctx->opcode)); @@ -3185,7 +3221,7 @@ GEN_HANDLER(td, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B) /* tdi */ GEN_HANDLER(tdi, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B) { - gen_op_load_gpr_T0(rA(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); tcg_gen_movi_tl(cpu_T[1], SIMM(ctx->opcode)); /* Update the nip since this might generate a trap exception */ gen_update_nip(ctx, ctx->nip); @@ -3217,7 +3253,7 @@ GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC) } else { gen_op_load_cr(); } - gen_op_store_T0_gpr(rD(ctx->opcode)); + tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]); } /* mfmsr */ @@ -3231,7 +3267,7 @@ GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC) return; } gen_op_load_msr(); - gen_op_store_T0_gpr(rD(ctx->opcode)); + tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]); #endif } @@ -3263,7 +3299,7 @@ static always_inline void gen_op_mfspr (DisasContext *ctx) if (likely(read_cb != NULL)) { if (likely(read_cb != SPR_NOACCESS)) { (*read_cb)(ctx, sprn); - gen_op_store_T0_gpr(rD(ctx->opcode)); + tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]); } else { /* Privilege exception */ /* This is a hack to avoid warnings when running Linux: @@ -3309,7 +3345,7 @@ GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC) { uint32_t crm, crn; - gen_op_load_gpr_T0(rS(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); crm = CRM(ctx->opcode); if (likely((ctx->opcode & 0x00100000) || (crm ^ (crm - 1)) == 0)) { crn = ffs(crm); @@ -3332,7 +3368,7 @@ GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B) GEN_EXCP_PRIVREG(ctx); return; } - gen_op_load_gpr_T0(rS(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); if (ctx->opcode & 0x00010000) { /* Special form that does not need any synchronisation */ gen_op_update_riee(); @@ -3360,7 +3396,7 @@ GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001FF801, PPC_MISC) GEN_EXCP_PRIVREG(ctx); return; } - gen_op_load_gpr_T0(rS(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); if (ctx->opcode & 0x00010000) { /* Special form that does not need any synchronisation */ gen_op_update_riee(); @@ -3399,7 +3435,7 @@ GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000001, PPC_MISC) write_cb = ctx->spr_cb[sprn].uea_write; if (likely(write_cb != NULL)) { if (likely(write_cb != SPR_NOACCESS)) { - gen_op_load_gpr_T0(rS(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); (*write_cb)(ctx, sprn); } else { /* Privilege exception */ @@ -3614,7 +3650,7 @@ GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT) } tcg_gen_movi_tl(cpu_T[1], SR(ctx->opcode)); gen_op_load_sr(); - gen_op_store_T0_gpr(rD(ctx->opcode)); + tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]); #endif } @@ -3628,10 +3664,10 @@ GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT) GEN_EXCP_PRIVREG(ctx); return; } - gen_op_load_gpr_T1(rB(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); gen_op_srli_T1(28); gen_op_load_sr(); - gen_op_store_T0_gpr(rD(ctx->opcode)); + tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]); #endif } @@ -3645,7 +3681,7 @@ GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT) GEN_EXCP_PRIVREG(ctx); return; } - gen_op_load_gpr_T0(rS(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); tcg_gen_movi_tl(cpu_T[1], SR(ctx->opcode)); gen_op_store_sr(); #endif @@ -3661,8 +3697,8 @@ GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT) GEN_EXCP_PRIVREG(ctx); return; } - gen_op_load_gpr_T0(rS(ctx->opcode)); - gen_op_load_gpr_T1(rB(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); gen_op_srli_T1(28); gen_op_store_sr(); #endif @@ -3682,7 +3718,7 @@ GEN_HANDLER2(mfsr_64b, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B) } tcg_gen_movi_tl(cpu_T[1], SR(ctx->opcode)); gen_op_load_slb(); - gen_op_store_T0_gpr(rD(ctx->opcode)); + tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]); #endif } @@ -3697,10 +3733,10 @@ GEN_HANDLER2(mfsrin_64b, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001, GEN_EXCP_PRIVREG(ctx); return; } - gen_op_load_gpr_T1(rB(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); gen_op_srli_T1(28); gen_op_load_slb(); - gen_op_store_T0_gpr(rD(ctx->opcode)); + tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]); #endif } @@ -3714,7 +3750,7 @@ GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B) GEN_EXCP_PRIVREG(ctx); return; } - gen_op_load_gpr_T0(rS(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); tcg_gen_movi_tl(cpu_T[1], SR(ctx->opcode)); gen_op_store_slb(); #endif @@ -3731,8 +3767,8 @@ GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001, GEN_EXCP_PRIVREG(ctx); return; } - gen_op_load_gpr_T0(rS(ctx->opcode)); - gen_op_load_gpr_T1(rB(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); gen_op_srli_T1(28); gen_op_store_slb(); #endif @@ -3765,7 +3801,7 @@ GEN_HANDLER(tlbie, 0x1F, 0x12, 0x09, 0x03FF0001, PPC_MEM_TLBIE) GEN_EXCP_PRIVOPC(ctx); return; } - gen_op_load_gpr_T0(rB(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rB(ctx->opcode)]); #if defined(TARGET_PPC64) if (ctx->sf_mode) gen_op_tlbie_64(); @@ -3817,7 +3853,7 @@ GEN_HANDLER(slbie, 0x1F, 0x12, 0x0D, 0x03FF0001, PPC_SLBI) GEN_EXCP_PRIVOPC(ctx); return; } - gen_op_load_gpr_T0(rB(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rB(ctx->opcode)]); gen_op_slbie(); #endif } @@ -3840,7 +3876,7 @@ GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN) /* Should check EAR[E] & alignment ! */ gen_addr_reg_index(ctx); op_eciwx(); - gen_op_store_T0_gpr(rD(ctx->opcode)); + tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]); } /* ecowx */ @@ -3848,7 +3884,7 @@ GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN) { /* Should check EAR[E] & alignment ! */ gen_addr_reg_index(ctx); - gen_op_load_gpr_T1(rS(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]); op_ecowx(); } @@ -3856,9 +3892,9 @@ GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN) /* abs - abs. */ GEN_HANDLER(abs, 0x1F, 0x08, 0x0B, 0x0000F800, PPC_POWER_BR) { - gen_op_load_gpr_T0(rA(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); gen_op_POWER_abs(); - gen_op_store_T0_gpr(rD(ctx->opcode)); + tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]); if (unlikely(Rc(ctx->opcode) != 0)) gen_set_Rc0(ctx); } @@ -3866,9 +3902,9 @@ GEN_HANDLER(abs, 0x1F, 0x08, 0x0B, 0x0000F800, PPC_POWER_BR) /* abso - abso. */ GEN_HANDLER(abso, 0x1F, 0x08, 0x1B, 0x0000F800, PPC_POWER_BR) { - gen_op_load_gpr_T0(rA(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); gen_op_POWER_abso(); - gen_op_store_T0_gpr(rD(ctx->opcode)); + tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]); if (unlikely(Rc(ctx->opcode) != 0)) gen_set_Rc0(ctx); } @@ -3876,19 +3912,19 @@ GEN_HANDLER(abso, 0x1F, 0x08, 0x1B, 0x0000F800, PPC_POWER_BR) /* clcs */ GEN_HANDLER(clcs, 0x1F, 0x10, 0x13, 0x0000F800, PPC_POWER_BR) { - gen_op_load_gpr_T0(rA(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); gen_op_POWER_clcs(); /* Rc=1 sets CR0 to an undefined state */ - gen_op_store_T0_gpr(rD(ctx->opcode)); + tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]); } /* div - div. */ GEN_HANDLER(div, 0x1F, 0x0B, 0x0A, 0x00000000, PPC_POWER_BR) { - gen_op_load_gpr_T0(rA(ctx->opcode)); - gen_op_load_gpr_T1(rB(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); gen_op_POWER_div(); - gen_op_store_T0_gpr(rD(ctx->opcode)); + tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]); if (unlikely(Rc(ctx->opcode) != 0)) gen_set_Rc0(ctx); } @@ -3896,10 +3932,10 @@ GEN_HANDLER(div, 0x1F, 0x0B, 0x0A, 0x00000000, PPC_POWER_BR) /* divo - divo. */ GEN_HANDLER(divo, 0x1F, 0x0B, 0x1A, 0x00000000, PPC_POWER_BR) { - gen_op_load_gpr_T0(rA(ctx->opcode)); - gen_op_load_gpr_T1(rB(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); gen_op_POWER_divo(); - gen_op_store_T0_gpr(rD(ctx->opcode)); + tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]); if (unlikely(Rc(ctx->opcode) != 0)) gen_set_Rc0(ctx); } @@ -3907,10 +3943,10 @@ GEN_HANDLER(divo, 0x1F, 0x0B, 0x1A, 0x00000000, PPC_POWER_BR) /* divs - divs. */ GEN_HANDLER(divs, 0x1F, 0x0B, 0x0B, 0x00000000, PPC_POWER_BR) { - gen_op_load_gpr_T0(rA(ctx->opcode)); - gen_op_load_gpr_T1(rB(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); gen_op_POWER_divs(); - gen_op_store_T0_gpr(rD(ctx->opcode)); + tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]); if (unlikely(Rc(ctx->opcode) != 0)) gen_set_Rc0(ctx); } @@ -3918,10 +3954,10 @@ GEN_HANDLER(divs, 0x1F, 0x0B, 0x0B, 0x00000000, PPC_POWER_BR) /* divso - divso. */ GEN_HANDLER(divso, 0x1F, 0x0B, 0x1B, 0x00000000, PPC_POWER_BR) { - gen_op_load_gpr_T0(rA(ctx->opcode)); - gen_op_load_gpr_T1(rB(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); gen_op_POWER_divso(); - gen_op_store_T0_gpr(rD(ctx->opcode)); + tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]); if (unlikely(Rc(ctx->opcode) != 0)) gen_set_Rc0(ctx); } @@ -3929,10 +3965,10 @@ GEN_HANDLER(divso, 0x1F, 0x0B, 0x1B, 0x00000000, PPC_POWER_BR) /* doz - doz. */ GEN_HANDLER(doz, 0x1F, 0x08, 0x08, 0x00000000, PPC_POWER_BR) { - gen_op_load_gpr_T0(rA(ctx->opcode)); - gen_op_load_gpr_T1(rB(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); gen_op_POWER_doz(); - gen_op_store_T0_gpr(rD(ctx->opcode)); + tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]); if (unlikely(Rc(ctx->opcode) != 0)) gen_set_Rc0(ctx); } @@ -3940,10 +3976,10 @@ GEN_HANDLER(doz, 0x1F, 0x08, 0x08, 0x00000000, PPC_POWER_BR) /* dozo - dozo. */ GEN_HANDLER(dozo, 0x1F, 0x08, 0x18, 0x00000000, PPC_POWER_BR) { - gen_op_load_gpr_T0(rA(ctx->opcode)); - gen_op_load_gpr_T1(rB(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); gen_op_POWER_dozo(); - gen_op_store_T0_gpr(rD(ctx->opcode)); + tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]); if (unlikely(Rc(ctx->opcode) != 0)) gen_set_Rc0(ctx); } @@ -3951,10 +3987,10 @@ GEN_HANDLER(dozo, 0x1F, 0x08, 0x18, 0x00000000, PPC_POWER_BR) /* dozi */ GEN_HANDLER(dozi, 0x09, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR) { - gen_op_load_gpr_T0(rA(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); tcg_gen_movi_tl(cpu_T[1], SIMM(ctx->opcode)); gen_op_POWER_doz(); - gen_op_store_T0_gpr(rD(ctx->opcode)); + tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]); } /* As lscbx load from memory byte after byte, it's always endian safe. @@ -4001,10 +4037,10 @@ GEN_HANDLER(lscbx, 0x1F, 0x15, 0x08, 0x00000000, PPC_POWER_BR) /* maskg - maskg. */ GEN_HANDLER(maskg, 0x1F, 0x1D, 0x00, 0x00000000, PPC_POWER_BR) { - gen_op_load_gpr_T0(rS(ctx->opcode)); - gen_op_load_gpr_T1(rB(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); gen_op_POWER_maskg(); - gen_op_store_T0_gpr(rA(ctx->opcode)); + tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]); if (unlikely(Rc(ctx->opcode) != 0)) gen_set_Rc0(ctx); } @@ -4012,11 +4048,11 @@ GEN_HANDLER(maskg, 0x1F, 0x1D, 0x00, 0x00000000, PPC_POWER_BR) /* maskir - maskir. */ GEN_HANDLER(maskir, 0x1F, 0x1D, 0x10, 0x00000000, PPC_POWER_BR) { - gen_op_load_gpr_T0(rA(ctx->opcode)); - gen_op_load_gpr_T1(rS(ctx->opcode)); - gen_op_load_gpr_T2(rB(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]); + tcg_gen_mov_tl(cpu_T[2], cpu_gpr[rB(ctx->opcode)]); gen_op_POWER_maskir(); - gen_op_store_T0_gpr(rA(ctx->opcode)); + tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]); if (unlikely(Rc(ctx->opcode) != 0)) gen_set_Rc0(ctx); } @@ -4024,10 +4060,10 @@ GEN_HANDLER(maskir, 0x1F, 0x1D, 0x10, 0x00000000, PPC_POWER_BR) /* mul - mul. */ GEN_HANDLER(mul, 0x1F, 0x0B, 0x03, 0x00000000, PPC_POWER_BR) { - gen_op_load_gpr_T0(rA(ctx->opcode)); - gen_op_load_gpr_T1(rB(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); gen_op_POWER_mul(); - gen_op_store_T0_gpr(rD(ctx->opcode)); + tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]); if (unlikely(Rc(ctx->opcode) != 0)) gen_set_Rc0(ctx); } @@ -4035,10 +4071,10 @@ GEN_HANDLER(mul, 0x1F, 0x0B, 0x03, 0x00000000, PPC_POWER_BR) /* mulo - mulo. */ GEN_HANDLER(mulo, 0x1F, 0x0B, 0x13, 0x00000000, PPC_POWER_BR) { - gen_op_load_gpr_T0(rA(ctx->opcode)); - gen_op_load_gpr_T1(rB(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); gen_op_POWER_mulo(); - gen_op_store_T0_gpr(rD(ctx->opcode)); + tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]); if (unlikely(Rc(ctx->opcode) != 0)) gen_set_Rc0(ctx); } @@ -4046,9 +4082,9 @@ GEN_HANDLER(mulo, 0x1F, 0x0B, 0x13, 0x00000000, PPC_POWER_BR) /* nabs - nabs. */ GEN_HANDLER(nabs, 0x1F, 0x08, 0x0F, 0x00000000, PPC_POWER_BR) { - gen_op_load_gpr_T0(rA(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); gen_op_POWER_nabs(); - gen_op_store_T0_gpr(rD(ctx->opcode)); + tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]); if (unlikely(Rc(ctx->opcode) != 0)) gen_set_Rc0(ctx); } @@ -4056,9 +4092,9 @@ GEN_HANDLER(nabs, 0x1F, 0x08, 0x0F, 0x00000000, PPC_POWER_BR) /* nabso - nabso. */ GEN_HANDLER(nabso, 0x1F, 0x08, 0x1F, 0x00000000, PPC_POWER_BR) { - gen_op_load_gpr_T0(rA(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); gen_op_POWER_nabso(); - gen_op_store_T0_gpr(rD(ctx->opcode)); + tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]); if (unlikely(Rc(ctx->opcode) != 0)) gen_set_Rc0(ctx); } @@ -4070,11 +4106,11 @@ GEN_HANDLER(rlmi, 0x16, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR) mb = MB(ctx->opcode); me = ME(ctx->opcode); - gen_op_load_gpr_T0(rS(ctx->opcode)); - gen_op_load_gpr_T1(rA(ctx->opcode)); - gen_op_load_gpr_T2(rB(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rA(ctx->opcode)]); + tcg_gen_mov_tl(cpu_T[2], cpu_gpr[rB(ctx->opcode)]); gen_op_POWER_rlmi(MASK(mb, me), ~MASK(mb, me)); - gen_op_store_T0_gpr(rA(ctx->opcode)); + tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]); if (unlikely(Rc(ctx->opcode) != 0)) gen_set_Rc0(ctx); } @@ -4082,11 +4118,11 @@ GEN_HANDLER(rlmi, 0x16, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR) /* rrib - rrib. */ GEN_HANDLER(rrib, 0x1F, 0x19, 0x10, 0x00000000, PPC_POWER_BR) { - gen_op_load_gpr_T0(rS(ctx->opcode)); - gen_op_load_gpr_T1(rA(ctx->opcode)); - gen_op_load_gpr_T2(rB(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rA(ctx->opcode)]); + tcg_gen_mov_tl(cpu_T[2], cpu_gpr[rB(ctx->opcode)]); gen_op_POWER_rrib(); - gen_op_store_T0_gpr(rA(ctx->opcode)); + tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]); if (unlikely(Rc(ctx->opcode) != 0)) gen_set_Rc0(ctx); } @@ -4094,10 +4130,10 @@ GEN_HANDLER(rrib, 0x1F, 0x19, 0x10, 0x00000000, PPC_POWER_BR) /* sle - sle. */ GEN_HANDLER(sle, 0x1F, 0x19, 0x04, 0x00000000, PPC_POWER_BR) { - gen_op_load_gpr_T0(rS(ctx->opcode)); - gen_op_load_gpr_T1(rB(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); gen_op_POWER_sle(); - gen_op_store_T0_gpr(rA(ctx->opcode)); + tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]); if (unlikely(Rc(ctx->opcode) != 0)) gen_set_Rc0(ctx); } @@ -4105,10 +4141,10 @@ GEN_HANDLER(sle, 0x1F, 0x19, 0x04, 0x00000000, PPC_POWER_BR) /* sleq - sleq. */ GEN_HANDLER(sleq, 0x1F, 0x19, 0x06, 0x00000000, PPC_POWER_BR) { - gen_op_load_gpr_T0(rS(ctx->opcode)); - gen_op_load_gpr_T1(rB(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); gen_op_POWER_sleq(); - gen_op_store_T0_gpr(rA(ctx->opcode)); + tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]); if (unlikely(Rc(ctx->opcode) != 0)) gen_set_Rc0(ctx); } @@ -4116,10 +4152,10 @@ GEN_HANDLER(sleq, 0x1F, 0x19, 0x06, 0x00000000, PPC_POWER_BR) /* sliq - sliq. */ GEN_HANDLER(sliq, 0x1F, 0x18, 0x05, 0x00000000, PPC_POWER_BR) { - gen_op_load_gpr_T0(rS(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); tcg_gen_movi_tl(cpu_T[1], SH(ctx->opcode)); gen_op_POWER_sle(); - gen_op_store_T0_gpr(rA(ctx->opcode)); + tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]); if (unlikely(Rc(ctx->opcode) != 0)) gen_set_Rc0(ctx); } @@ -4127,10 +4163,10 @@ GEN_HANDLER(sliq, 0x1F, 0x18, 0x05, 0x00000000, PPC_POWER_BR) /* slliq - slliq. */ GEN_HANDLER(slliq, 0x1F, 0x18, 0x07, 0x00000000, PPC_POWER_BR) { - gen_op_load_gpr_T0(rS(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); tcg_gen_movi_tl(cpu_T[1], SH(ctx->opcode)); gen_op_POWER_sleq(); - gen_op_store_T0_gpr(rA(ctx->opcode)); + tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]); if (unlikely(Rc(ctx->opcode) != 0)) gen_set_Rc0(ctx); } @@ -4138,10 +4174,10 @@ GEN_HANDLER(slliq, 0x1F, 0x18, 0x07, 0x00000000, PPC_POWER_BR) /* sllq - sllq. */ GEN_HANDLER(sllq, 0x1F, 0x18, 0x06, 0x00000000, PPC_POWER_BR) { - gen_op_load_gpr_T0(rS(ctx->opcode)); - gen_op_load_gpr_T1(rB(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); gen_op_POWER_sllq(); - gen_op_store_T0_gpr(rA(ctx->opcode)); + tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]); if (unlikely(Rc(ctx->opcode) != 0)) gen_set_Rc0(ctx); } @@ -4149,10 +4185,10 @@ GEN_HANDLER(sllq, 0x1F, 0x18, 0x06, 0x00000000, PPC_POWER_BR) /* slq - slq. */ GEN_HANDLER(slq, 0x1F, 0x18, 0x04, 0x00000000, PPC_POWER_BR) { - gen_op_load_gpr_T0(rS(ctx->opcode)); - gen_op_load_gpr_T1(rB(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); gen_op_POWER_slq(); - gen_op_store_T0_gpr(rA(ctx->opcode)); + tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]); if (unlikely(Rc(ctx->opcode) != 0)) gen_set_Rc0(ctx); } @@ -4160,10 +4196,10 @@ GEN_HANDLER(slq, 0x1F, 0x18, 0x04, 0x00000000, PPC_POWER_BR) /* sraiq - sraiq. */ GEN_HANDLER(sraiq, 0x1F, 0x18, 0x1D, 0x00000000, PPC_POWER_BR) { - gen_op_load_gpr_T0(rS(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); tcg_gen_movi_tl(cpu_T[1], SH(ctx->opcode)); gen_op_POWER_sraq(); - gen_op_store_T0_gpr(rA(ctx->opcode)); + tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]); if (unlikely(Rc(ctx->opcode) != 0)) gen_set_Rc0(ctx); } @@ -4171,10 +4207,10 @@ GEN_HANDLER(sraiq, 0x1F, 0x18, 0x1D, 0x00000000, PPC_POWER_BR) /* sraq - sraq. */ GEN_HANDLER(sraq, 0x1F, 0x18, 0x1C, 0x00000000, PPC_POWER_BR) { - gen_op_load_gpr_T0(rS(ctx->opcode)); - gen_op_load_gpr_T1(rB(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); gen_op_POWER_sraq(); - gen_op_store_T0_gpr(rA(ctx->opcode)); + tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]); if (unlikely(Rc(ctx->opcode) != 0)) gen_set_Rc0(ctx); } @@ -4182,10 +4218,10 @@ GEN_HANDLER(sraq, 0x1F, 0x18, 0x1C, 0x00000000, PPC_POWER_BR) /* sre - sre. */ GEN_HANDLER(sre, 0x1F, 0x19, 0x14, 0x00000000, PPC_POWER_BR) { - gen_op_load_gpr_T0(rS(ctx->opcode)); - gen_op_load_gpr_T1(rB(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); gen_op_POWER_sre(); - gen_op_store_T0_gpr(rA(ctx->opcode)); + tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]); if (unlikely(Rc(ctx->opcode) != 0)) gen_set_Rc0(ctx); } @@ -4193,10 +4229,10 @@ GEN_HANDLER(sre, 0x1F, 0x19, 0x14, 0x00000000, PPC_POWER_BR) /* srea - srea. */ GEN_HANDLER(srea, 0x1F, 0x19, 0x1C, 0x00000000, PPC_POWER_BR) { - gen_op_load_gpr_T0(rS(ctx->opcode)); - gen_op_load_gpr_T1(rB(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); gen_op_POWER_srea(); - gen_op_store_T0_gpr(rA(ctx->opcode)); + tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]); if (unlikely(Rc(ctx->opcode) != 0)) gen_set_Rc0(ctx); } @@ -4204,10 +4240,10 @@ GEN_HANDLER(srea, 0x1F, 0x19, 0x1C, 0x00000000, PPC_POWER_BR) /* sreq */ GEN_HANDLER(sreq, 0x1F, 0x19, 0x16, 0x00000000, PPC_POWER_BR) { - gen_op_load_gpr_T0(rS(ctx->opcode)); - gen_op_load_gpr_T1(rB(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); gen_op_POWER_sreq(); - gen_op_store_T0_gpr(rA(ctx->opcode)); + tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]); if (unlikely(Rc(ctx->opcode) != 0)) gen_set_Rc0(ctx); } @@ -4215,10 +4251,10 @@ GEN_HANDLER(sreq, 0x1F, 0x19, 0x16, 0x00000000, PPC_POWER_BR) /* sriq */ GEN_HANDLER(sriq, 0x1F, 0x18, 0x15, 0x00000000, PPC_POWER_BR) { - gen_op_load_gpr_T0(rS(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); tcg_gen_movi_tl(cpu_T[1], SH(ctx->opcode)); gen_op_POWER_srq(); - gen_op_store_T0_gpr(rA(ctx->opcode)); + tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]); if (unlikely(Rc(ctx->opcode) != 0)) gen_set_Rc0(ctx); } @@ -4226,11 +4262,11 @@ GEN_HANDLER(sriq, 0x1F, 0x18, 0x15, 0x00000000, PPC_POWER_BR) /* srliq */ GEN_HANDLER(srliq, 0x1F, 0x18, 0x17, 0x00000000, PPC_POWER_BR) { - gen_op_load_gpr_T0(rS(ctx->opcode)); - gen_op_load_gpr_T1(rB(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); tcg_gen_movi_tl(cpu_T[1], SH(ctx->opcode)); gen_op_POWER_srlq(); - gen_op_store_T0_gpr(rA(ctx->opcode)); + tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]); if (unlikely(Rc(ctx->opcode) != 0)) gen_set_Rc0(ctx); } @@ -4238,10 +4274,10 @@ GEN_HANDLER(srliq, 0x1F, 0x18, 0x17, 0x00000000, PPC_POWER_BR) /* srlq */ GEN_HANDLER(srlq, 0x1F, 0x18, 0x16, 0x00000000, PPC_POWER_BR) { - gen_op_load_gpr_T0(rS(ctx->opcode)); - gen_op_load_gpr_T1(rB(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); gen_op_POWER_srlq(); - gen_op_store_T0_gpr(rA(ctx->opcode)); + tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]); if (unlikely(Rc(ctx->opcode) != 0)) gen_set_Rc0(ctx); } @@ -4249,10 +4285,10 @@ GEN_HANDLER(srlq, 0x1F, 0x18, 0x16, 0x00000000, PPC_POWER_BR) /* srq */ GEN_HANDLER(srq, 0x1F, 0x18, 0x14, 0x00000000, PPC_POWER_BR) { - gen_op_load_gpr_T0(rS(ctx->opcode)); - gen_op_load_gpr_T1(rB(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); gen_op_POWER_srq(); - gen_op_store_T0_gpr(rA(ctx->opcode)); + tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]); if (unlikely(Rc(ctx->opcode) != 0)) gen_set_Rc0(ctx); } @@ -4282,9 +4318,9 @@ GEN_HANDLER(mfrom, 0x1F, 0x09, 0x08, 0x03E0F801, PPC_602_SPEC) GEN_EXCP_PRIVOPC(ctx); return; } - gen_op_load_gpr_T0(rA(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); gen_op_602_mfrom(); - gen_op_store_T0_gpr(rD(ctx->opcode)); + tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]); #endif } @@ -4299,7 +4335,7 @@ GEN_HANDLER2(tlbld_6xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB) GEN_EXCP_PRIVOPC(ctx); return; } - gen_op_load_gpr_T0(rB(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rB(ctx->opcode)]); gen_op_6xx_tlbld(); #endif } @@ -4314,7 +4350,7 @@ GEN_HANDLER2(tlbli_6xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB) GEN_EXCP_PRIVOPC(ctx); return; } - gen_op_load_gpr_T0(rB(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rB(ctx->opcode)]); gen_op_6xx_tlbli(); #endif } @@ -4330,7 +4366,7 @@ GEN_HANDLER2(tlbld_74xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_74xx_TLB) GEN_EXCP_PRIVOPC(ctx); return; } - gen_op_load_gpr_T0(rB(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rB(ctx->opcode)]); gen_op_74xx_tlbld(); #endif } @@ -4345,7 +4381,7 @@ GEN_HANDLER2(tlbli_74xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_74xx_TLB) GEN_EXCP_PRIVOPC(ctx); return; } - gen_op_load_gpr_T0(rB(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rB(ctx->opcode)]); gen_op_74xx_tlbli(); #endif } @@ -4391,9 +4427,9 @@ GEN_HANDLER(mfsri, 0x1F, 0x13, 0x13, 0x00000001, PPC_POWER) gen_addr_reg_index(ctx); gen_op_POWER_mfsri(); - gen_op_store_T0_gpr(rd); + tcg_gen_mov_tl(cpu_gpr[rd], cpu_T[0]); if (ra != 0 && ra != rd) - gen_op_store_T1_gpr(ra); + tcg_gen_mov_tl(cpu_gpr[ra], cpu_T[1]); #endif } @@ -4408,7 +4444,7 @@ GEN_HANDLER(rac, 0x1F, 0x12, 0x19, 0x00000001, PPC_POWER) } gen_addr_reg_index(ctx); gen_op_POWER_rac(); - gen_op_store_T0_gpr(rD(ctx->opcode)); + tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]); #endif } @@ -4479,7 +4515,7 @@ GEN_HANDLER(lfqu, 0x39, 0xFF, 0xFF, 0x00000003, PPC_POWER2) gen_op_store_FT0_fpr(rD(ctx->opcode)); gen_op_store_FT1_fpr(rD(ctx->opcode) + 1); if (ra != 0) - gen_op_store_T0_gpr(ra); + tcg_gen_mov_tl(cpu_gpr[ra], cpu_T[0]); } /* lfqux */ @@ -4494,7 +4530,7 @@ GEN_HANDLER(lfqux, 0x1F, 0x17, 0x19, 0x00000001, PPC_POWER2) gen_op_store_FT0_fpr(rD(ctx->opcode)); gen_op_store_FT1_fpr(rD(ctx->opcode) + 1); if (ra != 0) - gen_op_store_T0_gpr(ra); + tcg_gen_mov_tl(cpu_gpr[ra], cpu_T[0]); } /* lfqx */ @@ -4531,7 +4567,7 @@ GEN_HANDLER(stfqu, 0x3D, 0xFF, 0xFF, 0x00000003, PPC_POWER2) gen_op_load_fpr_FT1(rS(ctx->opcode) + 1); op_POWER2_stfq(); if (ra != 0) - gen_op_store_T0_gpr(ra); + tcg_gen_mov_tl(cpu_gpr[ra], cpu_T[0]); } /* stfqux */ @@ -4546,7 +4582,7 @@ GEN_HANDLER(stfqux, 0x1F, 0x17, 0x1D, 0x00000001, PPC_POWER2) gen_op_load_fpr_FT1(rS(ctx->opcode) + 1); op_POWER2_stfq(); if (ra != 0) - gen_op_store_T0_gpr(ra); + tcg_gen_mov_tl(cpu_gpr[ra], cpu_T[0]); } /* stfqx */ @@ -4594,8 +4630,8 @@ static always_inline void gen_405_mulladd_insn (DisasContext *ctx, int opc2, int opc3, int ra, int rb, int rt, int Rc) { - gen_op_load_gpr_T0(ra); - gen_op_load_gpr_T1(rb); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[ra]); + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rb]); switch (opc3 & 0x0D) { case 0x05: /* macchw - macchw. - macchwo - macchwo. */ @@ -4646,7 +4682,7 @@ static always_inline void gen_405_mulladd_insn (DisasContext *ctx, } if (opc2 & 0x04) { /* (n)multiply-and-accumulate (0x0C - 0x0E) */ - gen_op_load_gpr_T2(rt); + tcg_gen_mov_tl(cpu_T[2], cpu_gpr[rt]); tcg_gen_mov_tl(cpu_T[1], cpu_T[0]); gen_op_405_add_T0_T2(); } @@ -4664,7 +4700,7 @@ static always_inline void gen_405_mulladd_insn (DisasContext *ctx, else gen_op_405_check_satu(); } - gen_op_store_T0_gpr(rt); + tcg_gen_mov_tl(cpu_gpr[rt], cpu_T[0]); if (unlikely(Rc) != 0) { /* Update Rc0 */ gen_set_Rc0(ctx); @@ -4778,7 +4814,7 @@ GEN_HANDLER(mfdcr, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR) } tcg_gen_movi_tl(cpu_T[0], dcrn); gen_op_load_dcr(); - gen_op_store_T0_gpr(rD(ctx->opcode)); + tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]); #endif } @@ -4795,7 +4831,7 @@ GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR) return; } tcg_gen_movi_tl(cpu_T[0], dcrn); - gen_op_load_gpr_T1(rS(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]); gen_op_store_dcr(); #endif } @@ -4811,9 +4847,9 @@ GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX) GEN_EXCP_PRIVREG(ctx); return; } - gen_op_load_gpr_T0(rA(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); gen_op_load_dcr(); - gen_op_store_T0_gpr(rD(ctx->opcode)); + tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]); /* Note: Rc update flag set leads to undefined state of Rc0 */ #endif } @@ -4829,8 +4865,8 @@ GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX) GEN_EXCP_PRIVREG(ctx); return; } - gen_op_load_gpr_T0(rA(ctx->opcode)); - gen_op_load_gpr_T1(rS(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]); gen_op_store_dcr(); /* Note: Rc update flag set leads to undefined state of Rc0 */ #endif @@ -4839,17 +4875,17 @@ GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX) /* mfdcrux (PPC 460) : user-mode access to DCR */ GEN_HANDLER(mfdcrux, 0x1F, 0x03, 0x09, 0x00000000, PPC_DCRUX) { - gen_op_load_gpr_T0(rA(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); gen_op_load_dcr(); - gen_op_store_T0_gpr(rD(ctx->opcode)); + tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]); /* Note: Rc update flag set leads to undefined state of Rc0 */ } /* mtdcrux (PPC 460) : user-mode access to DCR */ GEN_HANDLER(mtdcrux, 0x1F, 0x03, 0x0D, 0x00000000, PPC_DCRUX) { - gen_op_load_gpr_T0(rA(ctx->opcode)); - gen_op_load_gpr_T1(rS(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]); gen_op_store_dcr(); /* Note: Rc update flag set leads to undefined state of Rc0 */ } @@ -4880,7 +4916,7 @@ GEN_HANDLER(dcread, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON) } gen_addr_reg_index(ctx); op_ldst(lwz); - gen_op_store_T0_gpr(rD(ctx->opcode)); + tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]); #endif } @@ -4998,14 +5034,14 @@ GEN_HANDLER2(tlbre_40x, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB) } switch (rB(ctx->opcode)) { case 0: - gen_op_load_gpr_T0(rA(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); gen_op_4xx_tlbre_hi(); - gen_op_store_T0_gpr(rD(ctx->opcode)); + tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]); break; case 1: - gen_op_load_gpr_T0(rA(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); gen_op_4xx_tlbre_lo(); - gen_op_store_T0_gpr(rD(ctx->opcode)); + tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]); break; default: GEN_EXCP_INVAL(ctx); @@ -5028,7 +5064,7 @@ GEN_HANDLER2(tlbsx_40x, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB) gen_op_4xx_tlbsx(); if (Rc(ctx->opcode)) gen_op_4xx_tlbsx_check(); - gen_op_store_T0_gpr(rD(ctx->opcode)); + tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]); #endif } @@ -5044,13 +5080,13 @@ GEN_HANDLER2(tlbwe_40x, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB) } switch (rB(ctx->opcode)) { case 0: - gen_op_load_gpr_T0(rA(ctx->opcode)); - gen_op_load_gpr_T1(rS(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]); gen_op_4xx_tlbwe_hi(); break; case 1: - gen_op_load_gpr_T0(rA(ctx->opcode)); - gen_op_load_gpr_T1(rS(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]); gen_op_4xx_tlbwe_lo(); break; default: @@ -5075,9 +5111,9 @@ GEN_HANDLER2(tlbre_440, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE) case 0: case 1: case 2: - gen_op_load_gpr_T0(rA(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); gen_op_440_tlbre(rB(ctx->opcode)); - gen_op_store_T0_gpr(rD(ctx->opcode)); + tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]); break; default: GEN_EXCP_INVAL(ctx); @@ -5100,7 +5136,7 @@ GEN_HANDLER2(tlbsx_440, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE) gen_op_440_tlbsx(); if (Rc(ctx->opcode)) gen_op_4xx_tlbsx_check(); - gen_op_store_T0_gpr(rD(ctx->opcode)); + tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]); #endif } @@ -5118,8 +5154,8 @@ GEN_HANDLER2(tlbwe_440, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE) case 0: case 1: case 2: - gen_op_load_gpr_T0(rA(ctx->opcode)); - gen_op_load_gpr_T1(rS(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]); gen_op_440_tlbwe(rB(ctx->opcode)); break; default: @@ -5139,7 +5175,7 @@ GEN_HANDLER(wrtee, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE) GEN_EXCP_PRIVOPC(ctx); return; } - gen_op_load_gpr_T0(rD(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rD(ctx->opcode)]); gen_op_wrte(); /* Stop translation to have a chance to raise an exception * if we just set msr_ee to 1 @@ -5171,10 +5207,10 @@ GEN_HANDLER(wrteei, 0x1F, 0x03, 0x05, 0x000EFC01, PPC_WRTEE) /* dlmzb */ GEN_HANDLER(dlmzb, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC) { - gen_op_load_gpr_T0(rS(ctx->opcode)); - gen_op_load_gpr_T1(rB(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); gen_op_440_dlmzb(); - gen_op_store_T0_gpr(rA(ctx->opcode)); + tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]); gen_op_store_xer_bc(); if (Rc(ctx->opcode)) { gen_op_440_dlmzb_update_Rc(); @@ -5263,36 +5299,31 @@ GEN_VR_STX(vxl, 0x07, 0x0F); /*** SPE extension ***/ /* Register moves */ -#if !defined(TARGET_PPC64) -GEN32(gen_op_load_gpr64_T0, gen_op_load_gpr64_T0_gpr); -GEN32(gen_op_load_gpr64_T1, gen_op_load_gpr64_T1_gpr); -#if 0 // unused -GEN32(gen_op_load_gpr64_T2, gen_op_load_gpr64_T2_gpr); -#endif - -GEN32(gen_op_store_T0_gpr64, gen_op_store_T0_gpr64_gpr); -GEN32(gen_op_store_T1_gpr64, gen_op_store_T1_gpr64_gpr); -#if 0 // unused -GEN32(gen_op_store_T2_gpr64, gen_op_store_T2_gpr64_gpr); -#endif - -#else /* !defined(TARGET_PPC64) */ - -/* No specific load/store functions: GPRs are already 64 bits */ -#define gen_op_load_gpr64_T0 gen_op_load_gpr_T0 -#define gen_op_load_gpr64_T1 gen_op_load_gpr_T1 -#if 0 // unused -#define gen_op_load_gpr64_T2 gen_op_load_gpr_T2 +static always_inline void gen_load_gpr64(TCGv t, int reg) { +#if defined(TARGET_PPC64) + tcg_gen_mov_i64(t, cpu_gpr[reg]); +#else + tcg_gen_extu_i32_i64(t, cpu_gprh[reg]); + tcg_gen_shli_i64(t, t, 32); + TCGv tmp = tcg_temp_local_new(TCG_TYPE_I64); + tcg_gen_extu_i32_i64(tmp, cpu_gpr[reg]); + tcg_gen_or_i64(t, t, tmp); + tcg_temp_free(tmp); #endif +} -#define gen_op_store_T0_gpr64 gen_op_store_T0_gpr -#define gen_op_store_T1_gpr64 gen_op_store_T1_gpr -#if 0 // unused -#define gen_op_store_T2_gpr64 gen_op_store_T2_gpr +static always_inline void gen_store_gpr64(int reg, TCGv t) { +#if defined(TARGET_PPC64) + tcg_gen_mov_i64(cpu_gpr[reg], t); +#else + tcg_gen_trunc_i64_i32(cpu_gpr[reg], t); + TCGv tmp = tcg_temp_local_new(TCG_TYPE_I64); + tcg_gen_shri_i64(tmp, t, 32); + tcg_gen_trunc_i64_i32(cpu_gprh[reg], tmp); + tcg_temp_free(tmp); #endif - -#endif /* !defined(TARGET_PPC64) */ +} #define GEN_SPE(name0, name1, opc2, opc3, inval, type) \ GEN_HANDLER(name0##_##name1, 0x04, opc2, opc3, inval, type) \ @@ -5317,7 +5348,7 @@ static always_inline void gen_addr_spe_imm_index (DisasContext *ctx, int sh) if (rA(ctx->opcode) == 0) { tcg_gen_movi_tl(cpu_T[0], simm << sh); } else { - gen_op_load_gpr_T0(rA(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); if (likely(simm != 0)) gen_op_addi(simm << sh); } @@ -5342,7 +5373,7 @@ static always_inline void gen_evl##name (DisasContext *ctx) \ } \ gen_addr_spe_imm_index(ctx, sh); \ op_spe_ldst(spe_l##name); \ - gen_op_store_T1_gpr64(rD(ctx->opcode)); \ + gen_store_gpr64(rD(ctx->opcode), cpu_T64[1]); \ } #define GEN_SPE_LDX(name) \ @@ -5354,7 +5385,7 @@ static always_inline void gen_evl##name##x (DisasContext *ctx) \ } \ gen_addr_reg_index(ctx); \ op_spe_ldst(spe_l##name); \ - gen_op_store_T1_gpr64(rD(ctx->opcode)); \ + gen_store_gpr64(rD(ctx->opcode), cpu_T64[1]); \ } #define GEN_SPEOP_LD(name, sh) \ @@ -5370,7 +5401,7 @@ static always_inline void gen_evst##name (DisasContext *ctx) \ return; \ } \ gen_addr_spe_imm_index(ctx, sh); \ - gen_op_load_gpr64_T1(rS(ctx->opcode)); \ + gen_load_gpr64(cpu_T64[1], rS(ctx->opcode)); \ op_spe_ldst(spe_st##name); \ } @@ -5382,7 +5413,7 @@ static always_inline void gen_evst##name##x (DisasContext *ctx) \ return; \ } \ gen_addr_reg_index(ctx); \ - gen_op_load_gpr64_T1(rS(ctx->opcode)); \ + gen_load_gpr64(cpu_T64[1], rS(ctx->opcode)); \ op_spe_ldst(spe_st##name); \ } @@ -5403,10 +5434,10 @@ static always_inline void gen_##name (DisasContext *ctx) \ GEN_EXCP_NO_AP(ctx); \ return; \ } \ - gen_op_load_gpr64_T0(rA(ctx->opcode)); \ - gen_op_load_gpr64_T1(rB(ctx->opcode)); \ + gen_load_gpr64(cpu_T64[0], rA(ctx->opcode)); \ + gen_load_gpr64(cpu_T64[1], rB(ctx->opcode)); \ gen_op_##name(); \ - gen_op_store_T0_gpr64(rD(ctx->opcode)); \ + gen_store_gpr64(rD(ctx->opcode), cpu_T64[0]); \ } #define GEN_SPEOP_ARITH1(name) \ @@ -5416,9 +5447,9 @@ static always_inline void gen_##name (DisasContext *ctx) \ GEN_EXCP_NO_AP(ctx); \ return; \ } \ - gen_op_load_gpr64_T0(rA(ctx->opcode)); \ + gen_load_gpr64(cpu_T64[0], rA(ctx->opcode)); \ gen_op_##name(); \ - gen_op_store_T0_gpr64(rD(ctx->opcode)); \ + gen_store_gpr64(rD(ctx->opcode), cpu_T64[0]); \ } #define GEN_SPEOP_COMP(name) \ @@ -5428,8 +5459,8 @@ static always_inline void gen_##name (DisasContext *ctx) \ GEN_EXCP_NO_AP(ctx); \ return; \ } \ - gen_op_load_gpr64_T0(rA(ctx->opcode)); \ - gen_op_load_gpr64_T1(rB(ctx->opcode)); \ + gen_load_gpr64(cpu_T64[0], rA(ctx->opcode)); \ + gen_load_gpr64(cpu_T64[1], rB(ctx->opcode)); \ gen_op_##name(); \ gen_op_store_T0_crf(crfD(ctx->opcode)); \ } @@ -5465,10 +5496,10 @@ GEN_SPEOP_ARITH1(evcntlsw); static always_inline void gen_brinc (DisasContext *ctx) { /* Note: brinc is usable even if SPE is disabled */ - gen_op_load_gpr_T0(rA(ctx->opcode)); - gen_op_load_gpr_T1(rB(ctx->opcode)); + tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); + tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); gen_op_brinc(); - gen_op_store_T0_gpr(rD(ctx->opcode)); + tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]); } #define GEN_SPEOP_ARITH_IMM2(name) \ @@ -5478,10 +5509,10 @@ static always_inline void gen_##name##i (DisasContext *ctx) \ GEN_EXCP_NO_AP(ctx); \ return; \ } \ - gen_op_load_gpr64_T0(rB(ctx->opcode)); \ + gen_load_gpr64(cpu_T64[0], rB(ctx->opcode)); \ gen_op_splatwi_T1_64(rA(ctx->opcode)); \ gen_op_##name(); \ - gen_op_store_T0_gpr64(rD(ctx->opcode)); \ + gen_store_gpr64(rD(ctx->opcode), cpu_T64[0]); \ } #define GEN_SPEOP_LOGIC_IMM2(name) \ @@ -5491,10 +5522,10 @@ static always_inline void gen_##name##i (DisasContext *ctx) \ GEN_EXCP_NO_AP(ctx); \ return; \ } \ - gen_op_load_gpr64_T0(rA(ctx->opcode)); \ + gen_load_gpr64(cpu_T64[0], rA(ctx->opcode)); \ gen_op_splatwi_T1_64(rB(ctx->opcode)); \ gen_op_##name(); \ - gen_op_store_T0_gpr64(rD(ctx->opcode)); \ + gen_store_gpr64(rD(ctx->opcode), cpu_T64[0]); \ } GEN_SPEOP_ARITH_IMM2(evaddw); @@ -5513,7 +5544,7 @@ static always_inline void gen_evsplati (DisasContext *ctx) int32_t imm = (int32_t)(rA(ctx->opcode) << 27) >> 27; gen_op_splatwi_T0_64(imm); - gen_op_store_T0_gpr64(rD(ctx->opcode)); + gen_store_gpr64(rD(ctx->opcode), cpu_T64[0]); } static always_inline void gen_evsplatfi (DisasContext *ctx) @@ -5521,7 +5552,7 @@ static always_inline void gen_evsplatfi (DisasContext *ctx) uint32_t imm = rA(ctx->opcode) << 27; gen_op_splatwi_T0_64(imm); - gen_op_store_T0_gpr64(rD(ctx->opcode)); + gen_store_gpr64(rD(ctx->opcode), cpu_T64[0]); } /* Comparison */ @@ -5564,10 +5595,10 @@ static always_inline void gen_evsel (DisasContext *ctx) return; } gen_op_load_crf_T0(ctx->opcode & 0x7); - gen_op_load_gpr64_T0(rA(ctx->opcode)); - gen_op_load_gpr64_T1(rB(ctx->opcode)); + gen_load_gpr64(cpu_T64[0], rA(ctx->opcode)); + gen_load_gpr64(cpu_T64[1], rB(ctx->opcode)); gen_op_evsel(); - gen_op_store_T0_gpr64(rD(ctx->opcode)); + gen_store_gpr64(rD(ctx->opcode), cpu_T64[0]); } GEN_HANDLER2(evsel0, "evsel", 0x04, 0x1c, 0x09, 0x00000000, PPC_SPE) @@ -5906,9 +5937,9 @@ GEN_SPE(speundef, evmwsmfan, 0x0D, 0x17, 0x00000000, PPC_SPE); #define GEN_SPEFPUOP_CONV(name) \ static always_inline void gen_##name (DisasContext *ctx) \ { \ - gen_op_load_gpr64_T0(rB(ctx->opcode)); \ + gen_load_gpr64(cpu_T64[0], rB(ctx->opcode)); \ gen_op_##name(); \ - gen_op_store_T0_gpr64(rD(ctx->opcode)); \ + gen_store_gpr64(rD(ctx->opcode), cpu_T64[0]); \ } /* Single precision floating-point vectors operations */ -- 1.5.5.1 [-- Attachment #3: Type: text/plain, Size: 1 bytes --] ^ permalink raw reply related [flat|nested] 42+ messages in thread
* Re: [Qemu-devel] [PATCH 5/x v2] ppc: Convert GPR moves to TCG 2008-09-03 20:04 ` [Qemu-devel] [PATCH 5/x v2] ppc: Convert GPR moves " Andreas Färber @ 2008-09-04 5:25 ` Aurelien Jarno 2008-09-04 10:21 ` Andreas Färber 2008-09-04 12:24 ` [Qemu-devel] [PATCH 6/x] ppc: Convert Altivec register " Andreas Färber 1 sibling, 1 reply; 42+ messages in thread From: Aurelien Jarno @ 2008-09-04 5:25 UTC (permalink / raw) To: qemu-devel On Wed, Sep 03, 2008 at 10:04:39PM +0200, Andreas Färber wrote: > Replace op_load_gpr_{T0,T1,T2} and op_store_{T0,T1,T2} with > tcg_gen_mov_tl. > Introduce TCG variables cpu_gpr[0..31]. > > For the SPE extension, assure that ppc_gpr_t is only uint64_t for ppc64. > Introduce TCG variables cpu_gprh[0..31] for upper 32 bits on ppc and > helpers > gen_{load,store}_gpr64. Based on suggestions by Aurelien, Thiemo and > Blue. > > Signed-off-by: Andreas Faerber <andreas.faerber@web.de> > --- > target-ppc/cpu.h | 12 +- > target-ppc/op_template.h | 85 ------ > target-ppc/translate.c | 747 +++++++++++++++++++++++ > +---------------------- > 3 files changed, 390 insertions(+), 454 deletions(-) > I do not feel comfortable of defining t0, t1, t2 as both 32-bit and 64-bit variables in TCG. I have already seen aliasing problems at some point. I have therefore applied your patch, as well as another one which defines separate t0_64, t1_64, t2_64 registers on 32-bit targets. At the end of the conversion to TCG, those variables will disappear anyway. Thanks for your work. -- .''`. Aurelien Jarno | GPG: 1024D/F1BCDB73 : :' : Debian developer | Electrical Engineer `. `' aurel32@debian.org | aurelien@aurel32.net `- people.debian.org/~aurel32 | www.aurel32.net ^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [Qemu-devel] [PATCH 5/x v2] ppc: Convert GPR moves to TCG 2008-09-04 5:25 ` Aurelien Jarno @ 2008-09-04 10:21 ` Andreas Färber 0 siblings, 0 replies; 42+ messages in thread From: Andreas Färber @ 2008-09-04 10:21 UTC (permalink / raw) To: qemu-devel Am 04.09.2008 um 07:25 schrieb Aurelien Jarno: > On Wed, Sep 03, 2008 at 10:04:39PM +0200, Andreas Färber wrote: >> Replace op_load_gpr_{T0,T1,T2} and op_store_{T0,T1,T2} with >> tcg_gen_mov_tl. >> Introduce TCG variables cpu_gpr[0..31]. >> >> For the SPE extension, assure that ppc_gpr_t is only uint64_t for >> ppc64. >> Introduce TCG variables cpu_gprh[0..31] for upper 32 bits on ppc and >> helpers >> gen_{load,store}_gpr64. Based on suggestions by Aurelien, Thiemo and >> Blue. >> >> Signed-off-by: Andreas Faerber <andreas.faerber@web.de> >> > > I do not feel comfortable of defining t0, t1, t2 as both 32-bit and > 64-bit variables in TCG. I have already seen aliasing problems at some > point. > > I have therefore applied your patch, as well as another one which > defines separate t0_64, t1_64, t2_64 registers on 32-bit targets. At > the > end of the conversion to TCG, those variables will disappear anyway. Looks reasonable to me, thanks. Andreas ^ permalink raw reply [flat|nested] 42+ messages in thread
* [Qemu-devel] [PATCH 6/x] ppc: Convert Altivec register moves to TCG 2008-09-03 20:04 ` [Qemu-devel] [PATCH 5/x v2] ppc: Convert GPR moves " Andreas Färber 2008-09-04 5:25 ` Aurelien Jarno @ 2008-09-04 12:24 ` Andreas Färber 2008-09-04 14:08 ` [Qemu-devel] [PATCH 7/x] ppc: Convert FPR " Andreas Färber 2008-09-04 14:39 ` [Qemu-devel] [PATCH 6/x] ppc: Convert Altivec register moves " Aurélien Jarno 1 sibling, 2 replies; 42+ messages in thread From: Andreas Färber @ 2008-09-04 12:24 UTC (permalink / raw) To: qemu-devel; +Cc: Aurélien Jarno [-- Attachment #1: Type: text/plain, Size: 6541 bytes --] Replace op_{load,store}_avr with helpers gen_{load,store}_avr. Introduce two sets of i64 TCG variables, cpu_avr{h,l}[0..31], and cpu_AVR{h,l}[0..2]. Signed-off-by: Andreas Faerber <andreas.faerber@web.de> --- In the future this might be improved with a tcg_mem_alloc_new(TCG_TYPE_I128, ...) and corresponding move op on the TCG side of things. But for now, handling it in the target cuts down op_template.h to floating point and condition register moves. Andreas target-ppc/op_template.h | 39 ----------------------------------- target-ppc/translate.c | 50 +++++++++++++++++++++++++++++++++ +------------ 2 files changed, 37 insertions(+), 52 deletions(-) diff --git a/target-ppc/op_template.h b/target-ppc/op_template.h index 8c65e49..64e38a9 100644 --- a/target-ppc/op_template.h +++ b/target-ppc/op_template.h @@ -18,45 +18,6 @@ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ -/* Altivec registers moves */ -void OPPROTO glue(op_load_avr_A0_avr, REG) (void) -{ - AVR0 = env->avr[REG]; - RETURN(); -} - -void OPPROTO glue(op_load_avr_A1_avr, REG) (void) -{ - AVR1 = env->avr[REG]; - RETURN(); -} - -void OPPROTO glue(op_load_avr_A2_avr, REG) (void) -{ - AVR2 = env->avr[REG]; - RETURN(); -} - -void OPPROTO glue(op_store_A0_avr_avr, REG) (void) -{ - env->avr[REG] = AVR0; - RETURN(); -} - -void OPPROTO glue(op_store_A1_avr_avr, REG) (void) -{ - env->avr[REG] = AVR1; - RETURN(); -} - -#if 0 // unused -void OPPROTO glue(op_store_A2_avr_avr, REG) (void) -{ - env->avr[REG] = AVR2; - RETURN(); -} -#endif - #if REG <= 7 /* Condition register moves */ void OPPROTO glue(op_load_crf_T0_crf, REG) (void) diff --git a/target-ppc/translate.c b/target-ppc/translate.c index ea51716..0674376 100644 --- a/target-ppc/translate.c +++ b/target-ppc/translate.c @@ -46,15 +46,16 @@ /* global register indexes */ static TCGv cpu_env; -static char cpu_reg_names[10*3 + 22*4 +static char cpu_reg_names[10*3 + 22*4 /* GPR */ #if !defined(TARGET_PPC64) - + 10*4 + 22*5 + + 10*4 + 22*5 /* SPE GPRh */ #endif -]; + + 2*(10*6 + 22*7) /* AVRh, AVRl */]; static TCGv cpu_gpr[32]; #if !defined(TARGET_PPC64) static TCGv cpu_gprh[32]; #endif +static TCGv cpu_avrh[32], cpu_avrl[32]; /* dyngen register indexes */ static TCGv cpu_T[3]; @@ -63,6 +64,7 @@ static TCGv cpu_T[3]; #else static TCGv cpu_T64[3]; #endif +static TCGv cpu_AVRh[3], cpu_AVRl[3]; #include "gen-icount.h" @@ -99,6 +101,18 @@ void ppc_translate_init(void) TCG_AREG0, offsetof(CPUState, t2_64), "T2_64"); #endif + cpu_AVRh[0] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0, + offsetof(CPUState, avr0.u64[0]), "AVR0H"); + cpu_AVRl[0] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0, + offsetof(CPUState, avr0.u64[1]), "AVR0L"); + cpu_AVRh[1] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0, + offsetof(CPUState, avr1.u64[0]), "AVR1H"); + cpu_AVRl[1] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0, + offsetof(CPUState, avr1.u64[1]), "AVR1L"); + cpu_AVRh[2] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0, + offsetof(CPUState, avr2.u64[0]), "AVR2H"); + cpu_AVRl[2] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0, + offsetof(CPUState, avr2.u64[1]), "AVR2L"); p = cpu_reg_names; for (i = 0; i < 32; i++) { @@ -112,6 +126,15 @@ void ppc_translate_init(void) offsetof(CPUState, gprh[i]), p); p += (i < 10) ? 4 : 5; #endif + + sprintf(p, "avr%dH", i); + cpu_avrh[i] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0, + offsetof(CPUState, avr[i].u64[0]), p); + p += (i < 10) ? 6 : 7; + sprintf(p, "avr%dL", i); + cpu_avrl[i] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0, + offsetof(CPUState, avr[i].u64[1]), p); + p += (i < 10) ? 6 : 7; } /* register helpers */ @@ -5241,15 +5264,16 @@ GEN_HANDLER2(icbt_440, "icbt", 0x1F, 0x16, 0x00, 0x03E00001, PPC_BOOKE) /*** Altivec vector extension ***/ /* Altivec registers moves */ -GEN32(gen_op_load_avr_A0, gen_op_load_avr_A0_avr); -GEN32(gen_op_load_avr_A1, gen_op_load_avr_A1_avr); -GEN32(gen_op_load_avr_A2, gen_op_load_avr_A2_avr); -GEN32(gen_op_store_A0_avr, gen_op_store_A0_avr_avr); -GEN32(gen_op_store_A1_avr, gen_op_store_A1_avr_avr); -#if 0 // unused -GEN32(gen_op_store_A2_avr, gen_op_store_A2_avr_avr); -#endif +static always_inline void gen_load_avr(int t, int reg) { + tcg_gen_mov_i64(cpu_AVRh[t], cpu_avrh[reg]); + tcg_gen_mov_i64(cpu_AVRl[t], cpu_avrl[reg]); +} + +static always_inline void gen_store_avr(int reg, int t) { + tcg_gen_mov_i64(cpu_avrh[reg], cpu_AVRh[t]); + tcg_gen_mov_i64(cpu_avrl[reg], cpu_AVRl[t]); +} #define op_vr_ldst(name) (*gen_op_##name[ctx->mem_idx])() #define OP_VR_LD_TABLE(name) \ @@ -5270,7 +5294,7 @@ GEN_HANDLER(l##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC) \ } \ gen_addr_reg_index (ctx); \ op_vr_ldst (vr_l##name); \ - gen_op_store_A0_avr(rD(ctx- >opcode)); \ + gen_store_avr(rD(ctx->opcode), 0); \ } #define GEN_VR_STX(name, opc2, opc3) \ @@ -5281,7 +5305,7 @@ GEN_HANDLER(st##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC) \ return; \ } \ gen_addr_reg_index (ctx); \ - gen_op_load_avr_A0(rS(ctx- >opcode)); \ + gen_load_avr(0, rS(ctx- >opcode)); \ op_vr_ldst (vr_st##name); \ } -- 1.5.5.1 [-- Attachment #2: AVR-moves.patch --] [-- Type: application/octet-stream, Size: 6392 bytes --] From c6da00868b291de126ee8f224bbf9b778161d1fe Mon Sep 17 00:00:00 2001 From: =?utf-8?q?Andreas=20F=C3=A4rber?= <andreas.faerber@web.de> Date: Thu, 4 Sep 2008 14:03:37 +0200 Subject: [PATCH] ppc: Convert Altivec register moves to TCG --- target-ppc/op_template.h | 39 ----------------------------------- target-ppc/translate.c | 50 ++++++++++++++++++++++++++++++++++------------ 2 files changed, 37 insertions(+), 52 deletions(-) diff --git a/target-ppc/op_template.h b/target-ppc/op_template.h index 8c65e49..64e38a9 100644 --- a/target-ppc/op_template.h +++ b/target-ppc/op_template.h @@ -18,45 +18,6 @@ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ -/* Altivec registers moves */ -void OPPROTO glue(op_load_avr_A0_avr, REG) (void) -{ - AVR0 = env->avr[REG]; - RETURN(); -} - -void OPPROTO glue(op_load_avr_A1_avr, REG) (void) -{ - AVR1 = env->avr[REG]; - RETURN(); -} - -void OPPROTO glue(op_load_avr_A2_avr, REG) (void) -{ - AVR2 = env->avr[REG]; - RETURN(); -} - -void OPPROTO glue(op_store_A0_avr_avr, REG) (void) -{ - env->avr[REG] = AVR0; - RETURN(); -} - -void OPPROTO glue(op_store_A1_avr_avr, REG) (void) -{ - env->avr[REG] = AVR1; - RETURN(); -} - -#if 0 // unused -void OPPROTO glue(op_store_A2_avr_avr, REG) (void) -{ - env->avr[REG] = AVR2; - RETURN(); -} -#endif - #if REG <= 7 /* Condition register moves */ void OPPROTO glue(op_load_crf_T0_crf, REG) (void) diff --git a/target-ppc/translate.c b/target-ppc/translate.c index ea51716..0674376 100644 --- a/target-ppc/translate.c +++ b/target-ppc/translate.c @@ -46,15 +46,16 @@ /* global register indexes */ static TCGv cpu_env; -static char cpu_reg_names[10*3 + 22*4 +static char cpu_reg_names[10*3 + 22*4 /* GPR */ #if !defined(TARGET_PPC64) - + 10*4 + 22*5 + + 10*4 + 22*5 /* SPE GPRh */ #endif -]; + + 2*(10*6 + 22*7) /* AVRh, AVRl */]; static TCGv cpu_gpr[32]; #if !defined(TARGET_PPC64) static TCGv cpu_gprh[32]; #endif +static TCGv cpu_avrh[32], cpu_avrl[32]; /* dyngen register indexes */ static TCGv cpu_T[3]; @@ -63,6 +64,7 @@ static TCGv cpu_T[3]; #else static TCGv cpu_T64[3]; #endif +static TCGv cpu_AVRh[3], cpu_AVRl[3]; #include "gen-icount.h" @@ -99,6 +101,18 @@ void ppc_translate_init(void) TCG_AREG0, offsetof(CPUState, t2_64), "T2_64"); #endif + cpu_AVRh[0] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0, + offsetof(CPUState, avr0.u64[0]), "AVR0H"); + cpu_AVRl[0] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0, + offsetof(CPUState, avr0.u64[1]), "AVR0L"); + cpu_AVRh[1] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0, + offsetof(CPUState, avr1.u64[0]), "AVR1H"); + cpu_AVRl[1] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0, + offsetof(CPUState, avr1.u64[1]), "AVR1L"); + cpu_AVRh[2] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0, + offsetof(CPUState, avr2.u64[0]), "AVR2H"); + cpu_AVRl[2] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0, + offsetof(CPUState, avr2.u64[1]), "AVR2L"); p = cpu_reg_names; for (i = 0; i < 32; i++) { @@ -112,6 +126,15 @@ void ppc_translate_init(void) offsetof(CPUState, gprh[i]), p); p += (i < 10) ? 4 : 5; #endif + + sprintf(p, "avr%dH", i); + cpu_avrh[i] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0, + offsetof(CPUState, avr[i].u64[0]), p); + p += (i < 10) ? 6 : 7; + sprintf(p, "avr%dL", i); + cpu_avrl[i] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0, + offsetof(CPUState, avr[i].u64[1]), p); + p += (i < 10) ? 6 : 7; } /* register helpers */ @@ -5241,15 +5264,16 @@ GEN_HANDLER2(icbt_440, "icbt", 0x1F, 0x16, 0x00, 0x03E00001, PPC_BOOKE) /*** Altivec vector extension ***/ /* Altivec registers moves */ -GEN32(gen_op_load_avr_A0, gen_op_load_avr_A0_avr); -GEN32(gen_op_load_avr_A1, gen_op_load_avr_A1_avr); -GEN32(gen_op_load_avr_A2, gen_op_load_avr_A2_avr); -GEN32(gen_op_store_A0_avr, gen_op_store_A0_avr_avr); -GEN32(gen_op_store_A1_avr, gen_op_store_A1_avr_avr); -#if 0 // unused -GEN32(gen_op_store_A2_avr, gen_op_store_A2_avr_avr); -#endif +static always_inline void gen_load_avr(int t, int reg) { + tcg_gen_mov_i64(cpu_AVRh[t], cpu_avrh[reg]); + tcg_gen_mov_i64(cpu_AVRl[t], cpu_avrl[reg]); +} + +static always_inline void gen_store_avr(int reg, int t) { + tcg_gen_mov_i64(cpu_avrh[reg], cpu_AVRh[t]); + tcg_gen_mov_i64(cpu_avrl[reg], cpu_AVRl[t]); +} #define op_vr_ldst(name) (*gen_op_##name[ctx->mem_idx])() #define OP_VR_LD_TABLE(name) \ @@ -5270,7 +5294,7 @@ GEN_HANDLER(l##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC) \ } \ gen_addr_reg_index(ctx); \ op_vr_ldst(vr_l##name); \ - gen_op_store_A0_avr(rD(ctx->opcode)); \ + gen_store_avr(rD(ctx->opcode), 0); \ } #define GEN_VR_STX(name, opc2, opc3) \ @@ -5281,7 +5305,7 @@ GEN_HANDLER(st##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC) \ return; \ } \ gen_addr_reg_index(ctx); \ - gen_op_load_avr_A0(rS(ctx->opcode)); \ + gen_load_avr(0, rS(ctx->opcode)); \ op_vr_ldst(vr_st##name); \ } -- 1.5.5.1 ^ permalink raw reply related [flat|nested] 42+ messages in thread
* [Qemu-devel] [PATCH 7/x] ppc: Convert FPR moves to TCG 2008-09-04 12:24 ` [Qemu-devel] [PATCH 6/x] ppc: Convert Altivec register " Andreas Färber @ 2008-09-04 14:08 ` Andreas Färber 2008-09-04 14:39 ` Aurélien Jarno 2008-09-04 14:39 ` [Qemu-devel] [PATCH 6/x] ppc: Convert Altivec register moves " Aurélien Jarno 1 sibling, 1 reply; 42+ messages in thread From: Andreas Färber @ 2008-09-04 14:08 UTC (permalink / raw) To: qemu-devel; +Cc: Aurélien Jarno [-- Attachment #1: Type: text/plain, Size: 23811 bytes --] Replace op_{load,store}_fpr with tcg_gen_mov_i64. Introduce i64 TCG variables cpu_fpr[0..31] and cpu_FT[0..2]. This obsoletes op_template.h for REG > 7. Signed-off-by: Andreas Faerber <andreas.faerber@web.de> --- target-ppc/op.c | 72 -------------------------- target-ppc/op_template.h | 50 ------------------ target-ppc/translate.c | 125 +++++++++++++++++++++++ +---------------------- 3 files changed, 65 insertions(+), 182 deletions(-) diff --git a/target-ppc/op.c b/target-ppc/op.c index e663e60..107817c 100644 --- a/target-ppc/op.c +++ b/target-ppc/op.c @@ -50,78 +50,6 @@ #define REG 7 #include "op_template.h" -#define REG 8 -#include "op_template.h" - -#define REG 9 -#include "op_template.h" - -#define REG 10 -#include "op_template.h" - -#define REG 11 -#include "op_template.h" - -#define REG 12 -#include "op_template.h" - -#define REG 13 -#include "op_template.h" - -#define REG 14 -#include "op_template.h" - -#define REG 15 -#include "op_template.h" - -#define REG 16 -#include "op_template.h" - -#define REG 17 -#include "op_template.h" - -#define REG 18 -#include "op_template.h" - -#define REG 19 -#include "op_template.h" - -#define REG 20 -#include "op_template.h" - -#define REG 21 -#include "op_template.h" - -#define REG 22 -#include "op_template.h" - -#define REG 23 -#include "op_template.h" - -#define REG 24 -#include "op_template.h" - -#define REG 25 -#include "op_template.h" - -#define REG 26 -#include "op_template.h" - -#define REG 27 -#include "op_template.h" - -#define REG 28 -#include "op_template.h" - -#define REG 29 -#include "op_template.h" - -#define REG 30 -#include "op_template.h" - -#define REG 31 -#include "op_template.h" - void OPPROTO op_print_mem_EA (void) { do_print_mem_EA(T0); diff --git a/target-ppc/op_template.h b/target-ppc/op_template.h index 64e38a9..0501256 100644 --- a/target-ppc/op_template.h +++ b/target-ppc/op_template.h @@ -18,7 +18,6 @@ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ -#if REG <= 7 /* Condition register moves */ void OPPROTO glue(op_load_crf_T0_crf, REG) (void) { @@ -38,53 +37,4 @@ void OPPROTO glue(op_store_T0_crf_crf, REG) (void) RETURN(); } -#if 0 // Unused -void OPPROTO glue(op_store_T1_crf_crf, REG) (void) -{ - env->crf[REG] = T1; - RETURN(); -} -#endif - -#endif /* REG <= 7 */ - -/* floating point registers moves */ -void OPPROTO glue(op_load_fpr_FT0_fpr, REG) (void) -{ - FT0 = env->fpr[REG]; - RETURN(); -} - -void OPPROTO glue(op_store_FT0_fpr_fpr, REG) (void) -{ - env->fpr[REG] = FT0; - RETURN(); -} - -void OPPROTO glue(op_load_fpr_FT1_fpr, REG) (void) -{ - FT1 = env->fpr[REG]; - RETURN(); -} - -void OPPROTO glue(op_store_FT1_fpr_fpr, REG) (void) -{ - env->fpr[REG] = FT1; - RETURN(); -} - -void OPPROTO glue(op_load_fpr_FT2_fpr, REG) (void) -{ - FT2 = env->fpr[REG]; - RETURN(); -} - -#if 0 // unused -void OPPROTO glue(op_store_FT2_fpr_fpr, REG) (void) -{ - env->fpr[REG] = FT2; - RETURN(); -} -#endif - #undef REG diff --git a/target-ppc/translate.c b/target-ppc/translate.c index 0674376..dcb64b4 100644 --- a/target-ppc/translate.c +++ b/target-ppc/translate.c @@ -50,11 +50,13 @@ static char cpu_reg_names[10*3 + 22*4 /* GPR */ #if !defined(TARGET_PPC64) + 10*4 + 22*5 /* SPE GPRh */ #endif + + 10*4 + 22*5 /* FPR */ + 2*(10*6 + 22*7) /* AVRh, AVRl */]; static TCGv cpu_gpr[32]; #if !defined(TARGET_PPC64) static TCGv cpu_gprh[32]; #endif +static TCGv cpu_fpr[32]; static TCGv cpu_avrh[32], cpu_avrl[32]; /* dyngen register indexes */ @@ -64,6 +66,7 @@ static TCGv cpu_T[3]; #else static TCGv cpu_T64[3]; #endif +static TCGv cpu_FT[3]; static TCGv cpu_AVRh[3], cpu_AVRl[3]; #include "gen-icount.h" @@ -101,6 +104,14 @@ void ppc_translate_init(void) TCG_AREG0, offsetof(CPUState, t2_64), "T2_64"); #endif + + cpu_FT[0] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0, + offsetof(CPUState, ft0), "FT0"); + cpu_FT[1] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0, + offsetof(CPUState, ft1), "FT1"); + cpu_FT[2] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0, + offsetof(CPUState, ft2), "FT2"); + cpu_AVRh[0] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0, offsetof(CPUState, avr0.u64[0]), "AVR0H"); cpu_AVRl[0] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0, @@ -127,6 +138,10 @@ void ppc_translate_init(void) p += (i < 10) ? 4 : 5; #endif + sprintf(p, "fp%d", i); + cpu_fpr[i] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0, + offsetof(CPUState, fpr[i]), p); + sprintf(p, "avr%dH", i); cpu_avrh[i] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0, offsetof(CPUState, avr[i].u64[0]), p); @@ -196,16 +211,6 @@ GEN8(gen_op_store_T0_crf, gen_op_store_T0_crf_crf); GEN8(gen_op_store_T1_crf, gen_op_store_T1_crf_crf); #endif -/* floating point registers moves */ -GEN32(gen_op_load_fpr_FT0, gen_op_load_fpr_FT0_fpr); -GEN32(gen_op_load_fpr_FT1, gen_op_load_fpr_FT1_fpr); -GEN32(gen_op_load_fpr_FT2, gen_op_load_fpr_FT2_fpr); -GEN32(gen_op_store_FT0_fpr, gen_op_store_FT0_fpr_fpr); -GEN32(gen_op_store_FT1_fpr, gen_op_store_FT1_fpr_fpr); -#if 0 // unused -GEN32(gen_op_store_FT2_fpr, gen_op_store_FT2_fpr_fpr); -#endif - /* internal defines */ typedef struct DisasContext { struct TranslationBlock *tb; @@ -1780,15 +1785,15 @@ GEN_HANDLER(f##name, op1, op2, 0xFF, 0x00000000, type) \ GEN_EXCP_NO_FP(ctx); \ return; \ } \ - gen_op_load_fpr_FT0(rA(ctx- >opcode)); \ - gen_op_load_fpr_FT1(rC(ctx- >opcode)); \ - gen_op_load_fpr_FT2(rB(ctx- >opcode)); \ + tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rA(ctx- >opcode)]); \ + tcg_gen_mov_i64(cpu_FT[1], cpu_fpr[rC(ctx- >opcode)]); \ + tcg_gen_mov_i64(cpu_FT[2], cpu_fpr[rB(ctx- >opcode)]); \ gen_reset_fpstatus (); \ gen_op_f ##op(); \ if (isfloat) { \ gen_op_frsp(); \ } \ - gen_op_store_FT0_fpr(rD(ctx- >opcode)); \ + tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]); \ gen_compute_fprf(set_fprf, Rc(ctx->opcode) != 0); \ } @@ -1803,14 +1808,14 @@ GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type) \ GEN_EXCP_NO_FP(ctx); \ return; \ } \ - gen_op_load_fpr_FT0(rA(ctx- >opcode)); \ - gen_op_load_fpr_FT1(rB(ctx- >opcode)); \ + tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rA(ctx- >opcode)]); \ + tcg_gen_mov_i64(cpu_FT[1], cpu_fpr[rB(ctx- >opcode)]); \ gen_reset_fpstatus (); \ gen_op_f ##op(); \ if (isfloat) { \ gen_op_frsp(); \ } \ - gen_op_store_FT0_fpr(rD(ctx- >opcode)); \ + tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]); \ gen_compute_fprf(set_fprf, Rc(ctx->opcode) != 0); \ } #define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) \ @@ -1824,14 +1829,14 @@ GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type) \ GEN_EXCP_NO_FP(ctx); \ return; \ } \ - gen_op_load_fpr_FT0(rA(ctx- >opcode)); \ - gen_op_load_fpr_FT1(rC(ctx- >opcode)); \ + tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rA(ctx- >opcode)]); \ + tcg_gen_mov_i64(cpu_FT[1], cpu_fpr[rC(ctx- >opcode)]); \ gen_reset_fpstatus (); \ gen_op_f ##op(); \ if (isfloat) { \ gen_op_frsp(); \ } \ - gen_op_store_FT0_fpr(rD(ctx- >opcode)); \ + tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]); \ gen_compute_fprf(set_fprf, Rc(ctx->opcode) != 0); \ } #define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) \ @@ -1845,10 +1850,10 @@ GEN_HANDLER(f##name, 0x3F, op2, op3, 0x001F0000, type) \ GEN_EXCP_NO_FP(ctx); \ return; \ } \ - gen_op_load_fpr_FT0(rB(ctx- >opcode)); \ + tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rB(ctx- >opcode)]); \ gen_reset_fpstatus (); \ gen_op_f ##name(); \ - gen_op_store_FT0_fpr(rD(ctx- >opcode)); \ + tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]); \ gen_compute_fprf(set_fprf, Rc(ctx->opcode) != 0); \ } @@ -1859,10 +1864,10 @@ GEN_HANDLER(f##name, op1, op2, 0xFF, 0x001F07C0, type) \ GEN_EXCP_NO_FP(ctx); \ return; \ } \ - gen_op_load_fpr_FT0(rB(ctx- >opcode)); \ + tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rB(ctx- >opcode)]); \ gen_reset_fpstatus (); \ gen_op_f ##name(); \ - gen_op_store_FT0_fpr(rD(ctx- >opcode)); \ + tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]); \ gen_compute_fprf(set_fprf, Rc(ctx->opcode) != 0); \ } @@ -1902,10 +1907,10 @@ GEN_HANDLER(fsqrt, 0x3F, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT) GEN_EXCP_NO_FP(ctx); return; } - gen_op_load_fpr_FT0(rB(ctx->opcode)); + tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rB(ctx->opcode)]); gen_reset_fpstatus(); gen_op_fsqrt(); - gen_op_store_FT0_fpr(rD(ctx->opcode)); + tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]); gen_compute_fprf(1, Rc(ctx->opcode) != 0); } @@ -1915,11 +1920,11 @@ GEN_HANDLER(fsqrts, 0x3B, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT) GEN_EXCP_NO_FP(ctx); return; } - gen_op_load_fpr_FT0(rB(ctx->opcode)); + tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rB(ctx->opcode)]); gen_reset_fpstatus(); gen_op_fsqrt(); gen_op_frsp(); - gen_op_store_FT0_fpr(rD(ctx->opcode)); + tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]); gen_compute_fprf(1, Rc(ctx->opcode) != 0); } @@ -1966,8 +1971,8 @@ GEN_HANDLER(fcmpo, 0x3F, 0x00, 0x01, 0x00600001, PPC_FLOAT) GEN_EXCP_NO_FP(ctx); return; } - gen_op_load_fpr_FT0(rA(ctx->opcode)); - gen_op_load_fpr_FT1(rB(ctx->opcode)); + tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rA(ctx->opcode)]); + tcg_gen_mov_i64(cpu_FT[1], cpu_fpr[rB(ctx->opcode)]); gen_reset_fpstatus(); gen_op_fcmpo(); gen_op_store_T0_crf(crfD(ctx->opcode)); @@ -1981,8 +1986,8 @@ GEN_HANDLER(fcmpu, 0x3F, 0x00, 0x00, 0x00600001, PPC_FLOAT) GEN_EXCP_NO_FP(ctx); return; } - gen_op_load_fpr_FT0(rA(ctx->opcode)); - gen_op_load_fpr_FT1(rB(ctx->opcode)); + tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rA(ctx->opcode)]); + tcg_gen_mov_i64(cpu_FT[1], cpu_fpr[rB(ctx->opcode)]); gen_reset_fpstatus(); gen_op_fcmpu(); gen_op_store_T0_crf(crfD(ctx->opcode)); @@ -2002,8 +2007,8 @@ GEN_HANDLER(fmr, 0x3F, 0x08, 0x02, 0x001F0000, PPC_FLOAT) GEN_EXCP_NO_FP(ctx); return; } - gen_op_load_fpr_FT0(rB(ctx->opcode)); - gen_op_store_FT0_fpr(rD(ctx->opcode)); + tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rB(ctx->opcode)]); + tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]); gen_compute_fprf(0, Rc(ctx->opcode) != 0); } @@ -2041,7 +2046,7 @@ GEN_HANDLER(mffs, 0x3F, 0x07, 0x12, 0x001FF800, PPC_FLOAT) gen_optimize_fprf(); gen_reset_fpstatus(); gen_op_load_fpscr_FT0(); - gen_op_store_FT0_fpr(rD(ctx->opcode)); + tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]); gen_compute_fprf(0, Rc(ctx->opcode) != 0); } @@ -2096,7 +2101,7 @@ GEN_HANDLER(mtfsf, 0x3F, 0x07, 0x16, 0x02010000, PPC_FLOAT) return; } gen_optimize_fprf(); - gen_op_load_fpr_FT0(rB(ctx->opcode)); + tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rB(ctx->opcode)]); gen_reset_fpstatus(); gen_op_store_fpscr(FM(ctx->opcode)); if (unlikely(Rc(ctx->opcode) != 0)) { @@ -2716,7 +2721,7 @@ GEN_HANDLER(l##width, opc, 0xFF, 0xFF, 0x00000000, type) \ } \ gen_addr_imm_index(ctx, 0); \ op_ldst (l##width); \ - gen_op_store_FT0_fpr(rD(ctx- >opcode)); \ + tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]); \ } #define GEN_LDUF(width, opc, type) \ @@ -2732,7 +2737,7 @@ GEN_HANDLER(l##width##u, opc, 0xFF, 0xFF, 0x00000000, type) \ } \ gen_addr_imm_index(ctx, 0); \ op_ldst (l##width); \ - gen_op_store_FT0_fpr(rD(ctx- >opcode)); \ + tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]); \ tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]); \ } @@ -2749,7 +2754,7 @@ GEN_HANDLER(l##width##ux, 0x1F, 0x17, opc, 0x00000001, type) \ } \ gen_addr_reg_index (ctx); \ op_ldst (l##width); \ - gen_op_store_FT0_fpr(rD(ctx- >opcode)); \ + tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]); \ tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]); \ } @@ -2762,7 +2767,7 @@ GEN_HANDLER(l##width##x, 0x1F, opc2, opc3, 0x00000001, type) \ } \ gen_addr_reg_index (ctx); \ op_ldst (l##width); \ - gen_op_store_FT0_fpr(rD(ctx- >opcode)); \ + tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]); \ } #define GEN_LDFS(width, op, type) \ @@ -2786,7 +2791,7 @@ GEN_HANDLER(st##width, opc, 0xFF, 0xFF, 0x00000000, type) \ return; \ } \ gen_addr_imm_index(ctx, 0); \ - gen_op_load_fpr_FT0(rS(ctx- >opcode)); \ + tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rS(ctx- >opcode)]); \ op_ldst (st##width); \ } @@ -2802,7 +2807,7 @@ GEN_HANDLER(st##width##u, opc, 0xFF, 0xFF, 0x00000000, type) \ return; \ } \ gen_addr_imm_index(ctx, 0); \ - gen_op_load_fpr_FT0(rS(ctx- >opcode)); \ + tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rS(ctx- >opcode)]); \ op_ldst (st##width); \ tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]); \ } @@ -2819,7 +2824,7 @@ GEN_HANDLER(st##width##ux, 0x1F, 0x17, opc, 0x00000001, type) \ return; \ } \ gen_addr_reg_index (ctx); \ - gen_op_load_fpr_FT0(rS(ctx- >opcode)); \ + tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rS(ctx- >opcode)]); \ op_ldst (st##width); \ tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]); \ } @@ -2832,7 +2837,7 @@ GEN_HANDLER(st##width##x, 0x1F, opc2, opc3, 0x00000001, type) \ return; \ } \ gen_addr_reg_index (ctx); \ - gen_op_load_fpr_FT0(rS(ctx- >opcode)); \ + tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rS(ctx- >opcode)]); \ op_ldst (st##width); \ } @@ -4522,8 +4527,8 @@ GEN_HANDLER(lfq, 0x38, 0xFF, 0xFF, 0x00000003, PPC_POWER2) gen_update_nip(ctx, ctx->nip - 4); gen_addr_imm_index(ctx, 0); op_POWER2_lfq(); - gen_op_store_FT0_fpr(rD(ctx->opcode)); - gen_op_store_FT1_fpr(rD(ctx->opcode) + 1); + tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]); + tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode) + 1], cpu_FT[1]); } /* lfqu */ @@ -4535,8 +4540,8 @@ GEN_HANDLER(lfqu, 0x39, 0xFF, 0xFF, 0x00000003, PPC_POWER2) gen_update_nip(ctx, ctx->nip - 4); gen_addr_imm_index(ctx, 0); op_POWER2_lfq(); - gen_op_store_FT0_fpr(rD(ctx->opcode)); - gen_op_store_FT1_fpr(rD(ctx->opcode) + 1); + tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]); + tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode) + 1], cpu_FT[1]); if (ra != 0) tcg_gen_mov_tl(cpu_gpr[ra], cpu_T[0]); } @@ -4550,8 +4555,8 @@ GEN_HANDLER(lfqux, 0x1F, 0x17, 0x19, 0x00000001, PPC_POWER2) gen_update_nip(ctx, ctx->nip - 4); gen_addr_reg_index(ctx); op_POWER2_lfq(); - gen_op_store_FT0_fpr(rD(ctx->opcode)); - gen_op_store_FT1_fpr(rD(ctx->opcode) + 1); + tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]); + tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode) + 1], cpu_FT[1]); if (ra != 0) tcg_gen_mov_tl(cpu_gpr[ra], cpu_T[0]); } @@ -4563,8 +4568,8 @@ GEN_HANDLER(lfqx, 0x1F, 0x17, 0x18, 0x00000001, PPC_POWER2) gen_update_nip(ctx, ctx->nip - 4); gen_addr_reg_index(ctx); op_POWER2_lfq(); - gen_op_store_FT0_fpr(rD(ctx->opcode)); - gen_op_store_FT1_fpr(rD(ctx->opcode) + 1); + tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]); + tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode) + 1], cpu_FT[1]); } /* stfq */ @@ -4573,8 +4578,8 @@ GEN_HANDLER(stfq, 0x3C, 0xFF, 0xFF, 0x00000003, PPC_POWER2) /* NIP cannot be restored if the memory exception comes from an helper */ gen_update_nip(ctx, ctx->nip - 4); gen_addr_imm_index(ctx, 0); - gen_op_load_fpr_FT0(rS(ctx->opcode)); - gen_op_load_fpr_FT1(rS(ctx->opcode) + 1); + tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rS(ctx->opcode)]); + tcg_gen_mov_i64(cpu_FT[1], cpu_fpr[rS(ctx->opcode) + 1]); op_POWER2_stfq(); } @@ -4586,8 +4591,8 @@ GEN_HANDLER(stfqu, 0x3D, 0xFF, 0xFF, 0x00000003, PPC_POWER2) /* NIP cannot be restored if the memory exception comes from an helper */ gen_update_nip(ctx, ctx->nip - 4); gen_addr_imm_index(ctx, 0); - gen_op_load_fpr_FT0(rS(ctx->opcode)); - gen_op_load_fpr_FT1(rS(ctx->opcode) + 1); + tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rS(ctx->opcode)]); + tcg_gen_mov_i64(cpu_FT[1], cpu_fpr[rS(ctx->opcode) + 1]); op_POWER2_stfq(); if (ra != 0) tcg_gen_mov_tl(cpu_gpr[ra], cpu_T[0]); @@ -4601,8 +4606,8 @@ GEN_HANDLER(stfqux, 0x1F, 0x17, 0x1D, 0x00000001, PPC_POWER2) /* NIP cannot be restored if the memory exception comes from an helper */ gen_update_nip(ctx, ctx->nip - 4); gen_addr_reg_index(ctx); - gen_op_load_fpr_FT0(rS(ctx->opcode)); - gen_op_load_fpr_FT1(rS(ctx->opcode) + 1); + tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rS(ctx->opcode)]); + tcg_gen_mov_i64(cpu_FT[1], cpu_fpr[rS(ctx->opcode) + 1]); op_POWER2_stfq(); if (ra != 0) tcg_gen_mov_tl(cpu_gpr[ra], cpu_T[0]); @@ -4614,8 +4619,8 @@ GEN_HANDLER(stfqx, 0x1F, 0x17, 0x1C, 0x00000001, PPC_POWER2) /* NIP cannot be restored if the memory exception comes from an helper */ gen_update_nip(ctx, ctx->nip - 4); gen_addr_reg_index(ctx); - gen_op_load_fpr_FT0(rS(ctx->opcode)); - gen_op_load_fpr_FT1(rS(ctx->opcode) + 1); + tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rS(ctx->opcode)]); + tcg_gen_mov_i64(cpu_FT[1], cpu_fpr[rS(ctx->opcode) + 1]); op_POWER2_stfq(); } -- 1.5.5.1 [-- Attachment #2: FPR-moves.patch --] [-- Type: application/octet-stream, Size: 23837 bytes --] From 5c752cde4dd9baac199a79ce70829e40747b11c4 Mon Sep 17 00:00:00 2001 From: =?utf-8?q?Andreas=20F=C3=A4rber?= <andreas.faerber@web.de> Date: Thu, 4 Sep 2008 15:38:12 +0200 Subject: [PATCH] ppc: Convert FPR moves to TCG --- target-ppc/op.c | 72 -------------------------- target-ppc/op_template.h | 50 ------------------ target-ppc/translate.c | 125 ++++++++++++++++++++++++---------------------- 3 files changed, 65 insertions(+), 182 deletions(-) diff --git a/target-ppc/op.c b/target-ppc/op.c index e663e60..107817c 100644 --- a/target-ppc/op.c +++ b/target-ppc/op.c @@ -50,78 +50,6 @@ #define REG 7 #include "op_template.h" -#define REG 8 -#include "op_template.h" - -#define REG 9 -#include "op_template.h" - -#define REG 10 -#include "op_template.h" - -#define REG 11 -#include "op_template.h" - -#define REG 12 -#include "op_template.h" - -#define REG 13 -#include "op_template.h" - -#define REG 14 -#include "op_template.h" - -#define REG 15 -#include "op_template.h" - -#define REG 16 -#include "op_template.h" - -#define REG 17 -#include "op_template.h" - -#define REG 18 -#include "op_template.h" - -#define REG 19 -#include "op_template.h" - -#define REG 20 -#include "op_template.h" - -#define REG 21 -#include "op_template.h" - -#define REG 22 -#include "op_template.h" - -#define REG 23 -#include "op_template.h" - -#define REG 24 -#include "op_template.h" - -#define REG 25 -#include "op_template.h" - -#define REG 26 -#include "op_template.h" - -#define REG 27 -#include "op_template.h" - -#define REG 28 -#include "op_template.h" - -#define REG 29 -#include "op_template.h" - -#define REG 30 -#include "op_template.h" - -#define REG 31 -#include "op_template.h" - void OPPROTO op_print_mem_EA (void) { do_print_mem_EA(T0); diff --git a/target-ppc/op_template.h b/target-ppc/op_template.h index 64e38a9..0501256 100644 --- a/target-ppc/op_template.h +++ b/target-ppc/op_template.h @@ -18,7 +18,6 @@ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ -#if REG <= 7 /* Condition register moves */ void OPPROTO glue(op_load_crf_T0_crf, REG) (void) { @@ -38,53 +37,4 @@ void OPPROTO glue(op_store_T0_crf_crf, REG) (void) RETURN(); } -#if 0 // Unused -void OPPROTO glue(op_store_T1_crf_crf, REG) (void) -{ - env->crf[REG] = T1; - RETURN(); -} -#endif - -#endif /* REG <= 7 */ - -/* floating point registers moves */ -void OPPROTO glue(op_load_fpr_FT0_fpr, REG) (void) -{ - FT0 = env->fpr[REG]; - RETURN(); -} - -void OPPROTO glue(op_store_FT0_fpr_fpr, REG) (void) -{ - env->fpr[REG] = FT0; - RETURN(); -} - -void OPPROTO glue(op_load_fpr_FT1_fpr, REG) (void) -{ - FT1 = env->fpr[REG]; - RETURN(); -} - -void OPPROTO glue(op_store_FT1_fpr_fpr, REG) (void) -{ - env->fpr[REG] = FT1; - RETURN(); -} - -void OPPROTO glue(op_load_fpr_FT2_fpr, REG) (void) -{ - FT2 = env->fpr[REG]; - RETURN(); -} - -#if 0 // unused -void OPPROTO glue(op_store_FT2_fpr_fpr, REG) (void) -{ - env->fpr[REG] = FT2; - RETURN(); -} -#endif - #undef REG diff --git a/target-ppc/translate.c b/target-ppc/translate.c index 0674376..dcb64b4 100644 --- a/target-ppc/translate.c +++ b/target-ppc/translate.c @@ -50,11 +50,13 @@ static char cpu_reg_names[10*3 + 22*4 /* GPR */ #if !defined(TARGET_PPC64) + 10*4 + 22*5 /* SPE GPRh */ #endif + + 10*4 + 22*5 /* FPR */ + 2*(10*6 + 22*7) /* AVRh, AVRl */]; static TCGv cpu_gpr[32]; #if !defined(TARGET_PPC64) static TCGv cpu_gprh[32]; #endif +static TCGv cpu_fpr[32]; static TCGv cpu_avrh[32], cpu_avrl[32]; /* dyngen register indexes */ @@ -64,6 +66,7 @@ static TCGv cpu_T[3]; #else static TCGv cpu_T64[3]; #endif +static TCGv cpu_FT[3]; static TCGv cpu_AVRh[3], cpu_AVRl[3]; #include "gen-icount.h" @@ -101,6 +104,14 @@ void ppc_translate_init(void) TCG_AREG0, offsetof(CPUState, t2_64), "T2_64"); #endif + + cpu_FT[0] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0, + offsetof(CPUState, ft0), "FT0"); + cpu_FT[1] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0, + offsetof(CPUState, ft1), "FT1"); + cpu_FT[2] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0, + offsetof(CPUState, ft2), "FT2"); + cpu_AVRh[0] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0, offsetof(CPUState, avr0.u64[0]), "AVR0H"); cpu_AVRl[0] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0, @@ -127,6 +138,10 @@ void ppc_translate_init(void) p += (i < 10) ? 4 : 5; #endif + sprintf(p, "fp%d", i); + cpu_fpr[i] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0, + offsetof(CPUState, fpr[i]), p); + sprintf(p, "avr%dH", i); cpu_avrh[i] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0, offsetof(CPUState, avr[i].u64[0]), p); @@ -196,16 +211,6 @@ GEN8(gen_op_store_T0_crf, gen_op_store_T0_crf_crf); GEN8(gen_op_store_T1_crf, gen_op_store_T1_crf_crf); #endif -/* floating point registers moves */ -GEN32(gen_op_load_fpr_FT0, gen_op_load_fpr_FT0_fpr); -GEN32(gen_op_load_fpr_FT1, gen_op_load_fpr_FT1_fpr); -GEN32(gen_op_load_fpr_FT2, gen_op_load_fpr_FT2_fpr); -GEN32(gen_op_store_FT0_fpr, gen_op_store_FT0_fpr_fpr); -GEN32(gen_op_store_FT1_fpr, gen_op_store_FT1_fpr_fpr); -#if 0 // unused -GEN32(gen_op_store_FT2_fpr, gen_op_store_FT2_fpr_fpr); -#endif - /* internal defines */ typedef struct DisasContext { struct TranslationBlock *tb; @@ -1780,15 +1785,15 @@ GEN_HANDLER(f##name, op1, op2, 0xFF, 0x00000000, type) \ GEN_EXCP_NO_FP(ctx); \ return; \ } \ - gen_op_load_fpr_FT0(rA(ctx->opcode)); \ - gen_op_load_fpr_FT1(rC(ctx->opcode)); \ - gen_op_load_fpr_FT2(rB(ctx->opcode)); \ + tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rA(ctx->opcode)]); \ + tcg_gen_mov_i64(cpu_FT[1], cpu_fpr[rC(ctx->opcode)]); \ + tcg_gen_mov_i64(cpu_FT[2], cpu_fpr[rB(ctx->opcode)]); \ gen_reset_fpstatus(); \ gen_op_f##op(); \ if (isfloat) { \ gen_op_frsp(); \ } \ - gen_op_store_FT0_fpr(rD(ctx->opcode)); \ + tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]); \ gen_compute_fprf(set_fprf, Rc(ctx->opcode) != 0); \ } @@ -1803,14 +1808,14 @@ GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type) \ GEN_EXCP_NO_FP(ctx); \ return; \ } \ - gen_op_load_fpr_FT0(rA(ctx->opcode)); \ - gen_op_load_fpr_FT1(rB(ctx->opcode)); \ + tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rA(ctx->opcode)]); \ + tcg_gen_mov_i64(cpu_FT[1], cpu_fpr[rB(ctx->opcode)]); \ gen_reset_fpstatus(); \ gen_op_f##op(); \ if (isfloat) { \ gen_op_frsp(); \ } \ - gen_op_store_FT0_fpr(rD(ctx->opcode)); \ + tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]); \ gen_compute_fprf(set_fprf, Rc(ctx->opcode) != 0); \ } #define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) \ @@ -1824,14 +1829,14 @@ GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type) \ GEN_EXCP_NO_FP(ctx); \ return; \ } \ - gen_op_load_fpr_FT0(rA(ctx->opcode)); \ - gen_op_load_fpr_FT1(rC(ctx->opcode)); \ + tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rA(ctx->opcode)]); \ + tcg_gen_mov_i64(cpu_FT[1], cpu_fpr[rC(ctx->opcode)]); \ gen_reset_fpstatus(); \ gen_op_f##op(); \ if (isfloat) { \ gen_op_frsp(); \ } \ - gen_op_store_FT0_fpr(rD(ctx->opcode)); \ + tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]); \ gen_compute_fprf(set_fprf, Rc(ctx->opcode) != 0); \ } #define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) \ @@ -1845,10 +1850,10 @@ GEN_HANDLER(f##name, 0x3F, op2, op3, 0x001F0000, type) \ GEN_EXCP_NO_FP(ctx); \ return; \ } \ - gen_op_load_fpr_FT0(rB(ctx->opcode)); \ + tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rB(ctx->opcode)]); \ gen_reset_fpstatus(); \ gen_op_f##name(); \ - gen_op_store_FT0_fpr(rD(ctx->opcode)); \ + tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]); \ gen_compute_fprf(set_fprf, Rc(ctx->opcode) != 0); \ } @@ -1859,10 +1864,10 @@ GEN_HANDLER(f##name, op1, op2, 0xFF, 0x001F07C0, type) \ GEN_EXCP_NO_FP(ctx); \ return; \ } \ - gen_op_load_fpr_FT0(rB(ctx->opcode)); \ + tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rB(ctx->opcode)]); \ gen_reset_fpstatus(); \ gen_op_f##name(); \ - gen_op_store_FT0_fpr(rD(ctx->opcode)); \ + tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]); \ gen_compute_fprf(set_fprf, Rc(ctx->opcode) != 0); \ } @@ -1902,10 +1907,10 @@ GEN_HANDLER(fsqrt, 0x3F, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT) GEN_EXCP_NO_FP(ctx); return; } - gen_op_load_fpr_FT0(rB(ctx->opcode)); + tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rB(ctx->opcode)]); gen_reset_fpstatus(); gen_op_fsqrt(); - gen_op_store_FT0_fpr(rD(ctx->opcode)); + tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]); gen_compute_fprf(1, Rc(ctx->opcode) != 0); } @@ -1915,11 +1920,11 @@ GEN_HANDLER(fsqrts, 0x3B, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT) GEN_EXCP_NO_FP(ctx); return; } - gen_op_load_fpr_FT0(rB(ctx->opcode)); + tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rB(ctx->opcode)]); gen_reset_fpstatus(); gen_op_fsqrt(); gen_op_frsp(); - gen_op_store_FT0_fpr(rD(ctx->opcode)); + tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]); gen_compute_fprf(1, Rc(ctx->opcode) != 0); } @@ -1966,8 +1971,8 @@ GEN_HANDLER(fcmpo, 0x3F, 0x00, 0x01, 0x00600001, PPC_FLOAT) GEN_EXCP_NO_FP(ctx); return; } - gen_op_load_fpr_FT0(rA(ctx->opcode)); - gen_op_load_fpr_FT1(rB(ctx->opcode)); + tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rA(ctx->opcode)]); + tcg_gen_mov_i64(cpu_FT[1], cpu_fpr[rB(ctx->opcode)]); gen_reset_fpstatus(); gen_op_fcmpo(); gen_op_store_T0_crf(crfD(ctx->opcode)); @@ -1981,8 +1986,8 @@ GEN_HANDLER(fcmpu, 0x3F, 0x00, 0x00, 0x00600001, PPC_FLOAT) GEN_EXCP_NO_FP(ctx); return; } - gen_op_load_fpr_FT0(rA(ctx->opcode)); - gen_op_load_fpr_FT1(rB(ctx->opcode)); + tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rA(ctx->opcode)]); + tcg_gen_mov_i64(cpu_FT[1], cpu_fpr[rB(ctx->opcode)]); gen_reset_fpstatus(); gen_op_fcmpu(); gen_op_store_T0_crf(crfD(ctx->opcode)); @@ -2002,8 +2007,8 @@ GEN_HANDLER(fmr, 0x3F, 0x08, 0x02, 0x001F0000, PPC_FLOAT) GEN_EXCP_NO_FP(ctx); return; } - gen_op_load_fpr_FT0(rB(ctx->opcode)); - gen_op_store_FT0_fpr(rD(ctx->opcode)); + tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rB(ctx->opcode)]); + tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]); gen_compute_fprf(0, Rc(ctx->opcode) != 0); } @@ -2041,7 +2046,7 @@ GEN_HANDLER(mffs, 0x3F, 0x07, 0x12, 0x001FF800, PPC_FLOAT) gen_optimize_fprf(); gen_reset_fpstatus(); gen_op_load_fpscr_FT0(); - gen_op_store_FT0_fpr(rD(ctx->opcode)); + tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]); gen_compute_fprf(0, Rc(ctx->opcode) != 0); } @@ -2096,7 +2101,7 @@ GEN_HANDLER(mtfsf, 0x3F, 0x07, 0x16, 0x02010000, PPC_FLOAT) return; } gen_optimize_fprf(); - gen_op_load_fpr_FT0(rB(ctx->opcode)); + tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rB(ctx->opcode)]); gen_reset_fpstatus(); gen_op_store_fpscr(FM(ctx->opcode)); if (unlikely(Rc(ctx->opcode) != 0)) { @@ -2716,7 +2721,7 @@ GEN_HANDLER(l##width, opc, 0xFF, 0xFF, 0x00000000, type) \ } \ gen_addr_imm_index(ctx, 0); \ op_ldst(l##width); \ - gen_op_store_FT0_fpr(rD(ctx->opcode)); \ + tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]); \ } #define GEN_LDUF(width, opc, type) \ @@ -2732,7 +2737,7 @@ GEN_HANDLER(l##width##u, opc, 0xFF, 0xFF, 0x00000000, type) \ } \ gen_addr_imm_index(ctx, 0); \ op_ldst(l##width); \ - gen_op_store_FT0_fpr(rD(ctx->opcode)); \ + tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]); \ tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]); \ } @@ -2749,7 +2754,7 @@ GEN_HANDLER(l##width##ux, 0x1F, 0x17, opc, 0x00000001, type) \ } \ gen_addr_reg_index(ctx); \ op_ldst(l##width); \ - gen_op_store_FT0_fpr(rD(ctx->opcode)); \ + tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]); \ tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]); \ } @@ -2762,7 +2767,7 @@ GEN_HANDLER(l##width##x, 0x1F, opc2, opc3, 0x00000001, type) \ } \ gen_addr_reg_index(ctx); \ op_ldst(l##width); \ - gen_op_store_FT0_fpr(rD(ctx->opcode)); \ + tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]); \ } #define GEN_LDFS(width, op, type) \ @@ -2786,7 +2791,7 @@ GEN_HANDLER(st##width, opc, 0xFF, 0xFF, 0x00000000, type) \ return; \ } \ gen_addr_imm_index(ctx, 0); \ - gen_op_load_fpr_FT0(rS(ctx->opcode)); \ + tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rS(ctx->opcode)]); \ op_ldst(st##width); \ } @@ -2802,7 +2807,7 @@ GEN_HANDLER(st##width##u, opc, 0xFF, 0xFF, 0x00000000, type) \ return; \ } \ gen_addr_imm_index(ctx, 0); \ - gen_op_load_fpr_FT0(rS(ctx->opcode)); \ + tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rS(ctx->opcode)]); \ op_ldst(st##width); \ tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]); \ } @@ -2819,7 +2824,7 @@ GEN_HANDLER(st##width##ux, 0x1F, 0x17, opc, 0x00000001, type) \ return; \ } \ gen_addr_reg_index(ctx); \ - gen_op_load_fpr_FT0(rS(ctx->opcode)); \ + tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rS(ctx->opcode)]); \ op_ldst(st##width); \ tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]); \ } @@ -2832,7 +2837,7 @@ GEN_HANDLER(st##width##x, 0x1F, opc2, opc3, 0x00000001, type) \ return; \ } \ gen_addr_reg_index(ctx); \ - gen_op_load_fpr_FT0(rS(ctx->opcode)); \ + tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rS(ctx->opcode)]); \ op_ldst(st##width); \ } @@ -4522,8 +4527,8 @@ GEN_HANDLER(lfq, 0x38, 0xFF, 0xFF, 0x00000003, PPC_POWER2) gen_update_nip(ctx, ctx->nip - 4); gen_addr_imm_index(ctx, 0); op_POWER2_lfq(); - gen_op_store_FT0_fpr(rD(ctx->opcode)); - gen_op_store_FT1_fpr(rD(ctx->opcode) + 1); + tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]); + tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode) + 1], cpu_FT[1]); } /* lfqu */ @@ -4535,8 +4540,8 @@ GEN_HANDLER(lfqu, 0x39, 0xFF, 0xFF, 0x00000003, PPC_POWER2) gen_update_nip(ctx, ctx->nip - 4); gen_addr_imm_index(ctx, 0); op_POWER2_lfq(); - gen_op_store_FT0_fpr(rD(ctx->opcode)); - gen_op_store_FT1_fpr(rD(ctx->opcode) + 1); + tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]); + tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode) + 1], cpu_FT[1]); if (ra != 0) tcg_gen_mov_tl(cpu_gpr[ra], cpu_T[0]); } @@ -4550,8 +4555,8 @@ GEN_HANDLER(lfqux, 0x1F, 0x17, 0x19, 0x00000001, PPC_POWER2) gen_update_nip(ctx, ctx->nip - 4); gen_addr_reg_index(ctx); op_POWER2_lfq(); - gen_op_store_FT0_fpr(rD(ctx->opcode)); - gen_op_store_FT1_fpr(rD(ctx->opcode) + 1); + tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]); + tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode) + 1], cpu_FT[1]); if (ra != 0) tcg_gen_mov_tl(cpu_gpr[ra], cpu_T[0]); } @@ -4563,8 +4568,8 @@ GEN_HANDLER(lfqx, 0x1F, 0x17, 0x18, 0x00000001, PPC_POWER2) gen_update_nip(ctx, ctx->nip - 4); gen_addr_reg_index(ctx); op_POWER2_lfq(); - gen_op_store_FT0_fpr(rD(ctx->opcode)); - gen_op_store_FT1_fpr(rD(ctx->opcode) + 1); + tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]); + tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode) + 1], cpu_FT[1]); } /* stfq */ @@ -4573,8 +4578,8 @@ GEN_HANDLER(stfq, 0x3C, 0xFF, 0xFF, 0x00000003, PPC_POWER2) /* NIP cannot be restored if the memory exception comes from an helper */ gen_update_nip(ctx, ctx->nip - 4); gen_addr_imm_index(ctx, 0); - gen_op_load_fpr_FT0(rS(ctx->opcode)); - gen_op_load_fpr_FT1(rS(ctx->opcode) + 1); + tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rS(ctx->opcode)]); + tcg_gen_mov_i64(cpu_FT[1], cpu_fpr[rS(ctx->opcode) + 1]); op_POWER2_stfq(); } @@ -4586,8 +4591,8 @@ GEN_HANDLER(stfqu, 0x3D, 0xFF, 0xFF, 0x00000003, PPC_POWER2) /* NIP cannot be restored if the memory exception comes from an helper */ gen_update_nip(ctx, ctx->nip - 4); gen_addr_imm_index(ctx, 0); - gen_op_load_fpr_FT0(rS(ctx->opcode)); - gen_op_load_fpr_FT1(rS(ctx->opcode) + 1); + tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rS(ctx->opcode)]); + tcg_gen_mov_i64(cpu_FT[1], cpu_fpr[rS(ctx->opcode) + 1]); op_POWER2_stfq(); if (ra != 0) tcg_gen_mov_tl(cpu_gpr[ra], cpu_T[0]); @@ -4601,8 +4606,8 @@ GEN_HANDLER(stfqux, 0x1F, 0x17, 0x1D, 0x00000001, PPC_POWER2) /* NIP cannot be restored if the memory exception comes from an helper */ gen_update_nip(ctx, ctx->nip - 4); gen_addr_reg_index(ctx); - gen_op_load_fpr_FT0(rS(ctx->opcode)); - gen_op_load_fpr_FT1(rS(ctx->opcode) + 1); + tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rS(ctx->opcode)]); + tcg_gen_mov_i64(cpu_FT[1], cpu_fpr[rS(ctx->opcode) + 1]); op_POWER2_stfq(); if (ra != 0) tcg_gen_mov_tl(cpu_gpr[ra], cpu_T[0]); @@ -4614,8 +4619,8 @@ GEN_HANDLER(stfqx, 0x1F, 0x17, 0x1C, 0x00000001, PPC_POWER2) /* NIP cannot be restored if the memory exception comes from an helper */ gen_update_nip(ctx, ctx->nip - 4); gen_addr_reg_index(ctx); - gen_op_load_fpr_FT0(rS(ctx->opcode)); - gen_op_load_fpr_FT1(rS(ctx->opcode) + 1); + tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rS(ctx->opcode)]); + tcg_gen_mov_i64(cpu_FT[1], cpu_fpr[rS(ctx->opcode) + 1]); op_POWER2_stfq(); } -- 1.5.5.1 ^ permalink raw reply related [flat|nested] 42+ messages in thread
* Re: [Qemu-devel] [PATCH 7/x] ppc: Convert FPR moves to TCG 2008-09-04 14:08 ` [Qemu-devel] [PATCH 7/x] ppc: Convert FPR " Andreas Färber @ 2008-09-04 14:39 ` Aurélien Jarno 2008-09-04 17:59 ` [Qemu-devel] [PATCH 8/x] ppc: Convert op_set_FT0 " Andreas Färber 0 siblings, 1 reply; 42+ messages in thread From: Aurélien Jarno @ 2008-09-04 14:39 UTC (permalink / raw) To: qemu-devel On Thu, Sep 04, 2008 at 04:08:05PM +0200, Andreas Färber wrote: > Replace op_{load,store}_fpr with tcg_gen_mov_i64. > Introduce i64 TCG variables cpu_fpr[0..31] and cpu_FT[0..2]. > > This obsoletes op_template.h for REG > 7. Applied, thanks. > > Signed-off-by: Andreas Faerber <andreas.faerber@web.de> > > --- > target-ppc/op.c | 72 -------------------------- > target-ppc/op_template.h | 50 ------------------ > target-ppc/translate.c | 125 +++++++++++++++++++++++ > +---------------------- > 3 files changed, 65 insertions(+), 182 deletions(-) > > diff --git a/target-ppc/op.c b/target-ppc/op.c > index e663e60..107817c 100644 > --- a/target-ppc/op.c > +++ b/target-ppc/op.c > @@ -50,78 +50,6 @@ > #define REG 7 > #include "op_template.h" > > -#define REG 8 > -#include "op_template.h" > - > -#define REG 9 > -#include "op_template.h" > - > -#define REG 10 > -#include "op_template.h" > - > -#define REG 11 > -#include "op_template.h" > - > -#define REG 12 > -#include "op_template.h" > - > -#define REG 13 > -#include "op_template.h" > - > -#define REG 14 > -#include "op_template.h" > - > -#define REG 15 > -#include "op_template.h" > - > -#define REG 16 > -#include "op_template.h" > - > -#define REG 17 > -#include "op_template.h" > - > -#define REG 18 > -#include "op_template.h" > - > -#define REG 19 > -#include "op_template.h" > - > -#define REG 20 > -#include "op_template.h" > - > -#define REG 21 > -#include "op_template.h" > - > -#define REG 22 > -#include "op_template.h" > - > -#define REG 23 > -#include "op_template.h" > - > -#define REG 24 > -#include "op_template.h" > - > -#define REG 25 > -#include "op_template.h" > - > -#define REG 26 > -#include "op_template.h" > - > -#define REG 27 > -#include "op_template.h" > - > -#define REG 28 > -#include "op_template.h" > - > -#define REG 29 > -#include "op_template.h" > - > -#define REG 30 > -#include "op_template.h" > - > -#define REG 31 > -#include "op_template.h" > - > void OPPROTO op_print_mem_EA (void) > { > do_print_mem_EA(T0); > diff --git a/target-ppc/op_template.h b/target-ppc/op_template.h > index 64e38a9..0501256 100644 > --- a/target-ppc/op_template.h > +++ b/target-ppc/op_template.h > @@ -18,7 +18,6 @@ > * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 > USA > */ > > -#if REG <= 7 > /* Condition register moves */ > void OPPROTO glue(op_load_crf_T0_crf, REG) (void) > { > @@ -38,53 +37,4 @@ void OPPROTO glue(op_store_T0_crf_crf, REG) (void) > RETURN(); > } > > -#if 0 // Unused > -void OPPROTO glue(op_store_T1_crf_crf, REG) (void) > -{ > - env->crf[REG] = T1; > - RETURN(); > -} > -#endif > - > -#endif /* REG <= 7 */ > - > -/* floating point registers moves */ > -void OPPROTO glue(op_load_fpr_FT0_fpr, REG) (void) > -{ > - FT0 = env->fpr[REG]; > - RETURN(); > -} > - > -void OPPROTO glue(op_store_FT0_fpr_fpr, REG) (void) > -{ > - env->fpr[REG] = FT0; > - RETURN(); > -} > - > -void OPPROTO glue(op_load_fpr_FT1_fpr, REG) (void) > -{ > - FT1 = env->fpr[REG]; > - RETURN(); > -} > - > -void OPPROTO glue(op_store_FT1_fpr_fpr, REG) (void) > -{ > - env->fpr[REG] = FT1; > - RETURN(); > -} > - > -void OPPROTO glue(op_load_fpr_FT2_fpr, REG) (void) > -{ > - FT2 = env->fpr[REG]; > - RETURN(); > -} > - > -#if 0 // unused > -void OPPROTO glue(op_store_FT2_fpr_fpr, REG) (void) > -{ > - env->fpr[REG] = FT2; > - RETURN(); > -} > -#endif > - > #undef REG > diff --git a/target-ppc/translate.c b/target-ppc/translate.c > index 0674376..dcb64b4 100644 > --- a/target-ppc/translate.c > +++ b/target-ppc/translate.c > @@ -50,11 +50,13 @@ static char cpu_reg_names[10*3 + 22*4 /* GPR */ > #if !defined(TARGET_PPC64) > + 10*4 + 22*5 /* SPE GPRh */ > #endif > + + 10*4 + 22*5 /* FPR */ > + 2*(10*6 + 22*7) /* AVRh, AVRl */]; > static TCGv cpu_gpr[32]; > #if !defined(TARGET_PPC64) > static TCGv cpu_gprh[32]; > #endif > +static TCGv cpu_fpr[32]; > static TCGv cpu_avrh[32], cpu_avrl[32]; > > /* dyngen register indexes */ > @@ -64,6 +66,7 @@ static TCGv cpu_T[3]; > #else > static TCGv cpu_T64[3]; > #endif > +static TCGv cpu_FT[3]; > static TCGv cpu_AVRh[3], cpu_AVRl[3]; > > #include "gen-icount.h" > @@ -101,6 +104,14 @@ void ppc_translate_init(void) > TCG_AREG0, offsetof(CPUState, > t2_64), > "T2_64"); > #endif > + > + cpu_FT[0] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0, > + offsetof(CPUState, ft0), "FT0"); > + cpu_FT[1] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0, > + offsetof(CPUState, ft1), "FT1"); > + cpu_FT[2] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0, > + offsetof(CPUState, ft2), "FT2"); > + > cpu_AVRh[0] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0, > offsetof(CPUState, avr0.u64[0]), > "AVR0H"); > cpu_AVRl[0] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0, > @@ -127,6 +138,10 @@ void ppc_translate_init(void) > p += (i < 10) ? 4 : 5; > #endif > > + sprintf(p, "fp%d", i); > + cpu_fpr[i] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0, > + offsetof(CPUState, fpr[i]), p); > + > sprintf(p, "avr%dH", i); > cpu_avrh[i] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0, > offsetof(CPUState, > avr[i].u64[0]), p); > @@ -196,16 +211,6 @@ GEN8(gen_op_store_T0_crf, gen_op_store_T0_crf_crf); > GEN8(gen_op_store_T1_crf, gen_op_store_T1_crf_crf); > #endif > > -/* floating point registers moves */ > -GEN32(gen_op_load_fpr_FT0, gen_op_load_fpr_FT0_fpr); > -GEN32(gen_op_load_fpr_FT1, gen_op_load_fpr_FT1_fpr); > -GEN32(gen_op_load_fpr_FT2, gen_op_load_fpr_FT2_fpr); > -GEN32(gen_op_store_FT0_fpr, gen_op_store_FT0_fpr_fpr); > -GEN32(gen_op_store_FT1_fpr, gen_op_store_FT1_fpr_fpr); > -#if 0 // unused > -GEN32(gen_op_store_FT2_fpr, gen_op_store_FT2_fpr_fpr); > -#endif > - > /* internal defines */ > typedef struct DisasContext { > struct TranslationBlock *tb; > @@ -1780,15 +1785,15 @@ GEN_HANDLER(f##name, op1, op2, 0xFF, 0x00000000, > type) \ > GEN_EXCP_NO_FP(ctx); > \ > return; > \ > } \ > - gen_op_load_fpr_FT0(rA(ctx->opcode)); > \ > - gen_op_load_fpr_FT1(rC(ctx->opcode)); > \ > - gen_op_load_fpr_FT2(rB(ctx->opcode)); > \ > + tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rA(ctx->opcode)]); > \ > + tcg_gen_mov_i64(cpu_FT[1], cpu_fpr[rC(ctx->opcode)]); > \ > + tcg_gen_mov_i64(cpu_FT[2], cpu_fpr[rB(ctx->opcode)]); > \ > gen_reset_fpstatus(); > \ > gen_op_f##op(); > \ > if (isfloat) { > \ > gen_op_frsp(); > \ > } \ > - gen_op_store_FT0_fpr(rD(ctx->opcode)); > \ > + tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]); > \ > gen_compute_fprf(set_fprf, Rc(ctx->opcode) != 0); > \ > } > > @@ -1803,14 +1808,14 @@ GEN_HANDLER(f##name, op1, op2, 0xFF, inval, > type) \ > GEN_EXCP_NO_FP(ctx); > \ > return; > \ > } \ > - gen_op_load_fpr_FT0(rA(ctx->opcode)); > \ > - gen_op_load_fpr_FT1(rB(ctx->opcode)); > \ > + tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rA(ctx->opcode)]); > \ > + tcg_gen_mov_i64(cpu_FT[1], cpu_fpr[rB(ctx->opcode)]); > \ > gen_reset_fpstatus(); > \ > gen_op_f##op(); > \ > if (isfloat) { > \ > gen_op_frsp(); > \ > } \ > - gen_op_store_FT0_fpr(rD(ctx->opcode)); > \ > + tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]); > \ > gen_compute_fprf(set_fprf, Rc(ctx->opcode) != 0); > \ > } > #define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) > \ > @@ -1824,14 +1829,14 @@ GEN_HANDLER(f##name, op1, op2, 0xFF, inval, > type) \ > GEN_EXCP_NO_FP(ctx); > \ > return; > \ > } \ > - gen_op_load_fpr_FT0(rA(ctx->opcode)); > \ > - gen_op_load_fpr_FT1(rC(ctx->opcode)); > \ > + tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rA(ctx->opcode)]); > \ > + tcg_gen_mov_i64(cpu_FT[1], cpu_fpr[rC(ctx->opcode)]); > \ > gen_reset_fpstatus(); > \ > gen_op_f##op(); > \ > if (isfloat) { > \ > gen_op_frsp(); > \ > } \ > - gen_op_store_FT0_fpr(rD(ctx->opcode)); > \ > + tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]); > \ > gen_compute_fprf(set_fprf, Rc(ctx->opcode) != 0); > \ > } > #define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) > \ > @@ -1845,10 +1850,10 @@ GEN_HANDLER(f##name, 0x3F, op2, op3, 0x001F0000, > type) \ > GEN_EXCP_NO_FP(ctx); > \ > return; > \ > } \ > - gen_op_load_fpr_FT0(rB(ctx->opcode)); > \ > + tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rB(ctx->opcode)]); > \ > gen_reset_fpstatus(); > \ > gen_op_f##name(); > \ > - gen_op_store_FT0_fpr(rD(ctx->opcode)); > \ > + tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]); > \ > gen_compute_fprf(set_fprf, Rc(ctx->opcode) != 0); > \ > } > > @@ -1859,10 +1864,10 @@ GEN_HANDLER(f##name, op1, op2, 0xFF, 0x001F07C0, > type) \ > GEN_EXCP_NO_FP(ctx); > \ > return; > \ > } \ > - gen_op_load_fpr_FT0(rB(ctx->opcode)); > \ > + tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rB(ctx->opcode)]); > \ > gen_reset_fpstatus(); > \ > gen_op_f##name(); > \ > - gen_op_store_FT0_fpr(rD(ctx->opcode)); > \ > + tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]); > \ > gen_compute_fprf(set_fprf, Rc(ctx->opcode) != 0); > \ > } > > @@ -1902,10 +1907,10 @@ GEN_HANDLER(fsqrt, 0x3F, 0x16, 0xFF, 0x001F07C0, > PPC_FLOAT_FSQRT) > GEN_EXCP_NO_FP(ctx); > return; > } > - gen_op_load_fpr_FT0(rB(ctx->opcode)); > + tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rB(ctx->opcode)]); > gen_reset_fpstatus(); > gen_op_fsqrt(); > - gen_op_store_FT0_fpr(rD(ctx->opcode)); > + tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]); > gen_compute_fprf(1, Rc(ctx->opcode) != 0); > } > > @@ -1915,11 +1920,11 @@ GEN_HANDLER(fsqrts, 0x3B, 0x16, 0xFF, > 0x001F07C0, PPC_FLOAT_FSQRT) > GEN_EXCP_NO_FP(ctx); > return; > } > - gen_op_load_fpr_FT0(rB(ctx->opcode)); > + tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rB(ctx->opcode)]); > gen_reset_fpstatus(); > gen_op_fsqrt(); > gen_op_frsp(); > - gen_op_store_FT0_fpr(rD(ctx->opcode)); > + tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]); > gen_compute_fprf(1, Rc(ctx->opcode) != 0); > } > > @@ -1966,8 +1971,8 @@ GEN_HANDLER(fcmpo, 0x3F, 0x00, 0x01, 0x00600001, > PPC_FLOAT) > GEN_EXCP_NO_FP(ctx); > return; > } > - gen_op_load_fpr_FT0(rA(ctx->opcode)); > - gen_op_load_fpr_FT1(rB(ctx->opcode)); > + tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rA(ctx->opcode)]); > + tcg_gen_mov_i64(cpu_FT[1], cpu_fpr[rB(ctx->opcode)]); > gen_reset_fpstatus(); > gen_op_fcmpo(); > gen_op_store_T0_crf(crfD(ctx->opcode)); > @@ -1981,8 +1986,8 @@ GEN_HANDLER(fcmpu, 0x3F, 0x00, 0x00, 0x00600001, > PPC_FLOAT) > GEN_EXCP_NO_FP(ctx); > return; > } > - gen_op_load_fpr_FT0(rA(ctx->opcode)); > - gen_op_load_fpr_FT1(rB(ctx->opcode)); > + tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rA(ctx->opcode)]); > + tcg_gen_mov_i64(cpu_FT[1], cpu_fpr[rB(ctx->opcode)]); > gen_reset_fpstatus(); > gen_op_fcmpu(); > gen_op_store_T0_crf(crfD(ctx->opcode)); > @@ -2002,8 +2007,8 @@ GEN_HANDLER(fmr, 0x3F, 0x08, 0x02, 0x001F0000, > PPC_FLOAT) > GEN_EXCP_NO_FP(ctx); > return; > } > - gen_op_load_fpr_FT0(rB(ctx->opcode)); > - gen_op_store_FT0_fpr(rD(ctx->opcode)); > + tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rB(ctx->opcode)]); > + tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]); > gen_compute_fprf(0, Rc(ctx->opcode) != 0); > } > > @@ -2041,7 +2046,7 @@ GEN_HANDLER(mffs, 0x3F, 0x07, 0x12, 0x001FF800, > PPC_FLOAT) > gen_optimize_fprf(); > gen_reset_fpstatus(); > gen_op_load_fpscr_FT0(); > - gen_op_store_FT0_fpr(rD(ctx->opcode)); > + tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]); > gen_compute_fprf(0, Rc(ctx->opcode) != 0); > } > > @@ -2096,7 +2101,7 @@ GEN_HANDLER(mtfsf, 0x3F, 0x07, 0x16, 0x02010000, > PPC_FLOAT) > return; > } > gen_optimize_fprf(); > - gen_op_load_fpr_FT0(rB(ctx->opcode)); > + tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rB(ctx->opcode)]); > gen_reset_fpstatus(); > gen_op_store_fpscr(FM(ctx->opcode)); > if (unlikely(Rc(ctx->opcode) != 0)) { > @@ -2716,7 +2721,7 @@ GEN_HANDLER(l##width, opc, 0xFF, 0xFF, 0x00000000, > type) \ > } \ > gen_addr_imm_index(ctx, 0); > \ > op_ldst(l##width); > \ > - gen_op_store_FT0_fpr(rD(ctx->opcode)); > \ > + tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]); > \ > } > > #define GEN_LDUF(width, opc, type) > \ > @@ -2732,7 +2737,7 @@ GEN_HANDLER(l##width##u, opc, 0xFF, 0xFF, > 0x00000000, type) \ > } \ > gen_addr_imm_index(ctx, 0); > \ > op_ldst(l##width); > \ > - gen_op_store_FT0_fpr(rD(ctx->opcode)); > \ > + tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]); > \ > tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]); > \ > } > > @@ -2749,7 +2754,7 @@ GEN_HANDLER(l##width##ux, 0x1F, 0x17, opc, > 0x00000001, type) \ > } \ > gen_addr_reg_index(ctx); > \ > op_ldst(l##width); > \ > - gen_op_store_FT0_fpr(rD(ctx->opcode)); > \ > + tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]); > \ > tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]); > \ > } > > @@ -2762,7 +2767,7 @@ GEN_HANDLER(l##width##x, 0x1F, opc2, opc3, > 0x00000001, type) \ > } \ > gen_addr_reg_index(ctx); > \ > op_ldst(l##width); > \ > - gen_op_store_FT0_fpr(rD(ctx->opcode)); > \ > + tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]); > \ > } > > #define GEN_LDFS(width, op, type) > \ > @@ -2786,7 +2791,7 @@ GEN_HANDLER(st##width, opc, 0xFF, 0xFF, > 0x00000000, type) \ > return; > \ > } \ > gen_addr_imm_index(ctx, 0); > \ > - gen_op_load_fpr_FT0(rS(ctx->opcode)); > \ > + tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rS(ctx->opcode)]); > \ > op_ldst(st##width); > \ > } > > @@ -2802,7 +2807,7 @@ GEN_HANDLER(st##width##u, opc, 0xFF, 0xFF, > 0x00000000, type) \ > return; > \ > } \ > gen_addr_imm_index(ctx, 0); > \ > - gen_op_load_fpr_FT0(rS(ctx->opcode)); > \ > + tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rS(ctx->opcode)]); > \ > op_ldst(st##width); > \ > tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]); > \ > } > @@ -2819,7 +2824,7 @@ GEN_HANDLER(st##width##ux, 0x1F, 0x17, opc, > 0x00000001, type) \ > return; > \ > } \ > gen_addr_reg_index(ctx); > \ > - gen_op_load_fpr_FT0(rS(ctx->opcode)); > \ > + tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rS(ctx->opcode)]); > \ > op_ldst(st##width); > \ > tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]); > \ > } > @@ -2832,7 +2837,7 @@ GEN_HANDLER(st##width##x, 0x1F, opc2, opc3, > 0x00000001, type) \ > return; > \ > } \ > gen_addr_reg_index(ctx); > \ > - gen_op_load_fpr_FT0(rS(ctx->opcode)); > \ > + tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rS(ctx->opcode)]); > \ > op_ldst(st##width); > \ > } > > @@ -4522,8 +4527,8 @@ GEN_HANDLER(lfq, 0x38, 0xFF, 0xFF, 0x00000003, > PPC_POWER2) > gen_update_nip(ctx, ctx->nip - 4); > gen_addr_imm_index(ctx, 0); > op_POWER2_lfq(); > - gen_op_store_FT0_fpr(rD(ctx->opcode)); > - gen_op_store_FT1_fpr(rD(ctx->opcode) + 1); > + tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]); > + tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode) + 1], cpu_FT[1]); > } > > /* lfqu */ > @@ -4535,8 +4540,8 @@ GEN_HANDLER(lfqu, 0x39, 0xFF, 0xFF, 0x00000003, > PPC_POWER2) > gen_update_nip(ctx, ctx->nip - 4); > gen_addr_imm_index(ctx, 0); > op_POWER2_lfq(); > - gen_op_store_FT0_fpr(rD(ctx->opcode)); > - gen_op_store_FT1_fpr(rD(ctx->opcode) + 1); > + tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]); > + tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode) + 1], cpu_FT[1]); > if (ra != 0) > tcg_gen_mov_tl(cpu_gpr[ra], cpu_T[0]); > } > @@ -4550,8 +4555,8 @@ GEN_HANDLER(lfqux, 0x1F, 0x17, 0x19, 0x00000001, > PPC_POWER2) > gen_update_nip(ctx, ctx->nip - 4); > gen_addr_reg_index(ctx); > op_POWER2_lfq(); > - gen_op_store_FT0_fpr(rD(ctx->opcode)); > - gen_op_store_FT1_fpr(rD(ctx->opcode) + 1); > + tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]); > + tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode) + 1], cpu_FT[1]); > if (ra != 0) > tcg_gen_mov_tl(cpu_gpr[ra], cpu_T[0]); > } > @@ -4563,8 +4568,8 @@ GEN_HANDLER(lfqx, 0x1F, 0x17, 0x18, 0x00000001, > PPC_POWER2) > gen_update_nip(ctx, ctx->nip - 4); > gen_addr_reg_index(ctx); > op_POWER2_lfq(); > - gen_op_store_FT0_fpr(rD(ctx->opcode)); > - gen_op_store_FT1_fpr(rD(ctx->opcode) + 1); > + tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]); > + tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode) + 1], cpu_FT[1]); > } > > /* stfq */ > @@ -4573,8 +4578,8 @@ GEN_HANDLER(stfq, 0x3C, 0xFF, 0xFF, 0x00000003, > PPC_POWER2) > /* NIP cannot be restored if the memory exception comes from an > helper */ > gen_update_nip(ctx, ctx->nip - 4); > gen_addr_imm_index(ctx, 0); > - gen_op_load_fpr_FT0(rS(ctx->opcode)); > - gen_op_load_fpr_FT1(rS(ctx->opcode) + 1); > + tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rS(ctx->opcode)]); > + tcg_gen_mov_i64(cpu_FT[1], cpu_fpr[rS(ctx->opcode) + 1]); > op_POWER2_stfq(); > } > > @@ -4586,8 +4591,8 @@ GEN_HANDLER(stfqu, 0x3D, 0xFF, 0xFF, 0x00000003, > PPC_POWER2) > /* NIP cannot be restored if the memory exception comes from an > helper */ > gen_update_nip(ctx, ctx->nip - 4); > gen_addr_imm_index(ctx, 0); > - gen_op_load_fpr_FT0(rS(ctx->opcode)); > - gen_op_load_fpr_FT1(rS(ctx->opcode) + 1); > + tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rS(ctx->opcode)]); > + tcg_gen_mov_i64(cpu_FT[1], cpu_fpr[rS(ctx->opcode) + 1]); > op_POWER2_stfq(); > if (ra != 0) > tcg_gen_mov_tl(cpu_gpr[ra], cpu_T[0]); > @@ -4601,8 +4606,8 @@ GEN_HANDLER(stfqux, 0x1F, 0x17, 0x1D, 0x00000001, > PPC_POWER2) > /* NIP cannot be restored if the memory exception comes from an > helper */ > gen_update_nip(ctx, ctx->nip - 4); > gen_addr_reg_index(ctx); > - gen_op_load_fpr_FT0(rS(ctx->opcode)); > - gen_op_load_fpr_FT1(rS(ctx->opcode) + 1); > + tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rS(ctx->opcode)]); > + tcg_gen_mov_i64(cpu_FT[1], cpu_fpr[rS(ctx->opcode) + 1]); > op_POWER2_stfq(); > if (ra != 0) > tcg_gen_mov_tl(cpu_gpr[ra], cpu_T[0]); > @@ -4614,8 +4619,8 @@ GEN_HANDLER(stfqx, 0x1F, 0x17, 0x1C, 0x00000001, > PPC_POWER2) > /* NIP cannot be restored if the memory exception comes from an > helper */ > gen_update_nip(ctx, ctx->nip - 4); > gen_addr_reg_index(ctx); > - gen_op_load_fpr_FT0(rS(ctx->opcode)); > - gen_op_load_fpr_FT1(rS(ctx->opcode) + 1); > + tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rS(ctx->opcode)]); > + tcg_gen_mov_i64(cpu_FT[1], cpu_fpr[rS(ctx->opcode) + 1]); > op_POWER2_stfq(); > } > > -- > 1.5.5.1 > > -- .''`. Aurelien Jarno | GPG: 1024D/F1BCDB73 : :' : Debian developer | Electrical Engineer `. `' aurel32@debian.org | aurelien@aurel32.net `- people.debian.org/~aurel32 | www.aurel32.net ^ permalink raw reply [flat|nested] 42+ messages in thread
* [Qemu-devel] [PATCH 8/x] ppc: Convert op_set_FT0 to TCG 2008-09-04 14:39 ` Aurélien Jarno @ 2008-09-04 17:59 ` Andreas Färber 2008-09-04 20:36 ` Aurélien Jarno 0 siblings, 1 reply; 42+ messages in thread From: Andreas Färber @ 2008-09-04 17:59 UTC (permalink / raw) To: qemu-devel; +Cc: Aurélien Jarno [-- Attachment #1: Type: text/plain, Size: 1515 bytes --] Replace op_set_FT0 with tcg_gen_movi_i64. Signed-off-by: Andreas Faerber <andreas.faerber@web.de> --- Here's a small one since we now seem to be both working on ppc. I'm not sure if this is correct since the dyngen op set the upper half to zero. Do we need an explicit cast to 32 bits for the immediate argument to assure they will be zero? Or was that just to avoid garbage with dyngen? Andreas target-ppc/op.c | 10 ---------- target-ppc/translate.c | 2 +- 2 files changed, 1 insertions(+), 11 deletions(-) diff --git a/target-ppc/op.c b/target-ppc/op.c index a31b41f..81329e3 100644 --- a/target-ppc/op.c +++ b/target-ppc/op.c @@ -424,16 +424,6 @@ void OPPROTO op_load_fpscr_FT0 (void) RETURN(); } -void OPPROTO op_set_FT0 (void) -{ - CPU_DoubleU u; - - u.l.upper = 0; - u.l.lower = PARAM1; - FT0 = u.d; - RETURN(); -} - void OPPROTO op_load_fpscr_T0 (void) { T0 = (env->fpscr >> PARAM1) & 0xF; diff --git a/target-ppc/translate.c b/target-ppc/translate.c index 9dd2506..5139ae6 100644 --- a/target-ppc/translate.c +++ b/target-ppc/translate.c @@ -2090,7 +2090,7 @@ GEN_HANDLER(mtfsfi, 0x3F, 0x06, 0x04, 0x006f0800, PPC_FLOAT) bf = crbD(ctx->opcode) >> 2; sh = 7 - bf; gen_optimize_fprf(); - gen_op_set_FT0(FPIMM(ctx->opcode) << (4 * sh)); + tcg_gen_movi_i64(cpu_FT[0], FPIMM(ctx->opcode) << (4 * sh)); gen_reset_fpstatus(); gen_op_store_fpscr(1 << sh); if (unlikely(Rc(ctx->opcode) != 0)) { -- 1.5.5.1 [-- Attachment #2: op_set_FT0.patch --] [-- Type: application/octet-stream, Size: 1366 bytes --] From 72b09a4fc1ae21d6de0d742e7ff8145d8e8876f2 Mon Sep 17 00:00:00 2001 From: =?utf-8?q?Andreas=20F=C3=A4rber?= <andreas.faerber@web.de> Date: Thu, 4 Sep 2008 19:47:58 +0200 Subject: [PATCH] ppc: Convert op_set_FT0 to TCG --- target-ppc/op.c | 10 ---------- target-ppc/translate.c | 2 +- 2 files changed, 1 insertions(+), 11 deletions(-) diff --git a/target-ppc/op.c b/target-ppc/op.c index a31b41f..81329e3 100644 --- a/target-ppc/op.c +++ b/target-ppc/op.c @@ -424,16 +424,6 @@ void OPPROTO op_load_fpscr_FT0 (void) RETURN(); } -void OPPROTO op_set_FT0 (void) -{ - CPU_DoubleU u; - - u.l.upper = 0; - u.l.lower = PARAM1; - FT0 = u.d; - RETURN(); -} - void OPPROTO op_load_fpscr_T0 (void) { T0 = (env->fpscr >> PARAM1) & 0xF; diff --git a/target-ppc/translate.c b/target-ppc/translate.c index 9dd2506..5139ae6 100644 --- a/target-ppc/translate.c +++ b/target-ppc/translate.c @@ -2090,7 +2090,7 @@ GEN_HANDLER(mtfsfi, 0x3F, 0x06, 0x04, 0x006f0800, PPC_FLOAT) bf = crbD(ctx->opcode) >> 2; sh = 7 - bf; gen_optimize_fprf(); - gen_op_set_FT0(FPIMM(ctx->opcode) << (4 * sh)); + tcg_gen_movi_i64(cpu_FT[0], FPIMM(ctx->opcode) << (4 * sh)); gen_reset_fpstatus(); gen_op_store_fpscr(1 << sh); if (unlikely(Rc(ctx->opcode) != 0)) { -- 1.5.5.1 [-- Attachment #3: Type: text/plain, Size: 1 bytes --] ^ permalink raw reply related [flat|nested] 42+ messages in thread
* Re: [Qemu-devel] [PATCH 8/x] ppc: Convert op_set_FT0 to TCG 2008-09-04 17:59 ` [Qemu-devel] [PATCH 8/x] ppc: Convert op_set_FT0 " Andreas Färber @ 2008-09-04 20:36 ` Aurélien Jarno 2008-09-04 22:53 ` [Qemu-devel] [PATCH 9/x] ppc: Convert op_add, op_addi " Andreas Färber 2008-09-04 23:46 ` [Qemu-devel] [PATCH 10/x] ppc: Convert op_subf " Andreas Färber 0 siblings, 2 replies; 42+ messages in thread From: Aurélien Jarno @ 2008-09-04 20:36 UTC (permalink / raw) To: Andreas Färber; +Cc: qemu-devel On Thu, Sep 04, 2008 at 07:59:37PM +0200, Andreas Färber wrote: > Replace op_set_FT0 with tcg_gen_movi_i64. > > Signed-off-by: Andreas Faerber <andreas.faerber@web.de> > > --- > Here's a small one since we now seem to be both working on ppc. > > I'm not sure if this is correct since the dyngen op set the upper half > to zero. Do we need an explicit cast to 32 bits for the immediate > argument to assure they will be zero? Or was that just to avoid garbage > with dyngen? No we don't. If you like at the instruction decoding, or at the PowerPC manual, you will see that the resulting number is always representable with a 32-bit variable. In dyngen, I guess it was to avoid passing both PARAM1 and PARAM2. Patch applied. > > Andreas > > target-ppc/op.c | 10 ---------- > target-ppc/translate.c | 2 +- > 2 files changed, 1 insertions(+), 11 deletions(-) > > diff --git a/target-ppc/op.c b/target-ppc/op.c > index a31b41f..81329e3 100644 > --- a/target-ppc/op.c > +++ b/target-ppc/op.c > @@ -424,16 +424,6 @@ void OPPROTO op_load_fpscr_FT0 (void) > RETURN(); > } > > -void OPPROTO op_set_FT0 (void) > -{ > - CPU_DoubleU u; > - > - u.l.upper = 0; > - u.l.lower = PARAM1; > - FT0 = u.d; > - RETURN(); > -} > - > void OPPROTO op_load_fpscr_T0 (void) > { > T0 = (env->fpscr >> PARAM1) & 0xF; > diff --git a/target-ppc/translate.c b/target-ppc/translate.c > index 9dd2506..5139ae6 100644 > --- a/target-ppc/translate.c > +++ b/target-ppc/translate.c > @@ -2090,7 +2090,7 @@ GEN_HANDLER(mtfsfi, 0x3F, 0x06, 0x04, 0x006f0800, > PPC_FLOAT) > bf = crbD(ctx->opcode) >> 2; > sh = 7 - bf; > gen_optimize_fprf(); > - gen_op_set_FT0(FPIMM(ctx->opcode) << (4 * sh)); > + tcg_gen_movi_i64(cpu_FT[0], FPIMM(ctx->opcode) << (4 * sh)); > gen_reset_fpstatus(); > gen_op_store_fpscr(1 << sh); > if (unlikely(Rc(ctx->opcode) != 0)) { > -- > 1.5.5.1 > > -- .''`. Aurelien Jarno | GPG: 1024D/F1BCDB73 : :' : Debian developer | Electrical Engineer `. `' aurel32@debian.org | aurelien@aurel32.net `- people.debian.org/~aurel32 | www.aurel32.net ^ permalink raw reply [flat|nested] 42+ messages in thread
* [Qemu-devel] [PATCH 9/x] ppc: Convert op_add, op_addi to TCG 2008-09-04 20:36 ` Aurélien Jarno @ 2008-09-04 22:53 ` Andreas Färber 2008-09-05 14:18 ` Aurélien Jarno 2008-09-04 23:46 ` [Qemu-devel] [PATCH 10/x] ppc: Convert op_subf " Andreas Färber 1 sibling, 1 reply; 42+ messages in thread From: Andreas Färber @ 2008-09-04 22:53 UTC (permalink / raw) To: qemu-devel; +Cc: Aurélien Jarno [-- Attachment #1: Type: text/plain, Size: 6118 bytes --] Replace op_add with tcg_gen_add_tl and op_addi with tcg_gen_addi_tl. Signed-off-by: Andreas Faerber <andreas.faerber@web.de> --- target-ppc/op.c | 13 ------------- target-ppc/translate.c | 34 +++++++++++++++++++--------------- 2 files changed, 19 insertions(+), 28 deletions(-) diff --git a/target-ppc/op.c b/target-ppc/op.c index 5451fd4..4ee411b 100644 --- a/target-ppc/op.c +++ b/target-ppc/op.c @@ -602,12 +602,6 @@ void OPPROTO op_dec_ctr (void) /*** Integer arithmetic ***/ /* add */ -void OPPROTO op_add (void) -{ - T0 += T1; - RETURN(); -} - void OPPROTO op_check_addo (void) { xer_ov = (((uint32_t)T2 ^ (uint32_t)T1 ^ UINT32_MAX) & @@ -664,13 +658,6 @@ void OPPROTO op_adde_64 (void) } #endif -/* add immediate */ -void OPPROTO op_addi (void) -{ - T0 += (int32_t)PARAM1; - RETURN(); -} - /* add to minus one extended */ void OPPROTO op_add_me (void) { diff --git a/target-ppc/translate.c b/target-ppc/translate.c index d952276..f505be1 100644 --- a/target-ppc/translate.c +++ b/target-ppc/translate.c @@ -827,10 +827,14 @@ __GEN_INT_ARITH1_O_64(name##o, opc1, opc2, opc3 | 0x10, type) #endif /* add add. addo addo. */ +static always_inline void gen_op_add (void) +{ + tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]); +} static always_inline void gen_op_addo (void) { tcg_gen_mov_tl(cpu_T[2], cpu_T[0]); - gen_op_add(); + tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]); gen_op_check_addo(); } #if defined(TARGET_PPC64) @@ -838,7 +842,7 @@ static always_inline void gen_op_addo (void) static always_inline void gen_op_addo_64 (void) { tcg_gen_mov_tl(cpu_T[2], cpu_T[0]); - gen_op_add(); + tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]); gen_op_check_addo_64(); } #endif @@ -847,13 +851,13 @@ GEN_INT_ARITH2_64 (add, 0x1F, 0x0A, 0x08, PPC_INTEGER); static always_inline void gen_op_addc (void) { tcg_gen_mov_tl(cpu_T[2], cpu_T[0]); - gen_op_add(); + tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]); gen_op_check_addc(); } static always_inline void gen_op_addco (void) { tcg_gen_mov_tl(cpu_T[2], cpu_T[0]); - gen_op_add(); + tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]); gen_op_check_addc(); gen_op_check_addo(); } @@ -861,13 +865,13 @@ static always_inline void gen_op_addco (void) static always_inline void gen_op_addc_64 (void) { tcg_gen_mov_tl(cpu_T[2], cpu_T[0]); - gen_op_add(); + tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]); gen_op_check_addc_64(); } static always_inline void gen_op_addco_64 (void) { tcg_gen_mov_tl(cpu_T[2], cpu_T[0]); - gen_op_add(); + tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]); gen_op_check_addc_64(); gen_op_check_addo_64(); } @@ -1022,7 +1026,7 @@ GEN_HANDLER(addi, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) } else { tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); if (likely(simm != 0)) - gen_op_addi(simm); + tcg_gen_addi_tl(cpu_T[0], cpu_T[0], simm); } tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]); } @@ -1034,7 +1038,7 @@ GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); if (likely(simm != 0)) { tcg_gen_mov_tl(cpu_T[2], cpu_T[0]); - gen_op_addi(simm); + tcg_gen_addi_tl(cpu_T[0], cpu_T[0], simm); #if defined(TARGET_PPC64) if (ctx->sf_mode) gen_op_check_addc_64(); @@ -1054,7 +1058,7 @@ GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); if (likely(simm != 0)) { tcg_gen_mov_tl(cpu_T[2], cpu_T[0]); - gen_op_addi(simm); + tcg_gen_addi_tl(cpu_T[0], cpu_T[0], simm); #if defined(TARGET_PPC64) if (ctx->sf_mode) gen_op_check_addc_64(); @@ -1078,7 +1082,7 @@ GEN_HANDLER(addis, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) } else { tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); if (likely(simm != 0)) - gen_op_addi(simm << 16); + tcg_gen_addi_tl(cpu_T[0], cpu_T[0], simm << 16); } tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]); } @@ -2118,7 +2122,7 @@ static always_inline void gen_addr_imm_index (DisasContext *ctx, } else { tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); if (likely(simm != 0)) - gen_op_addi(simm); + tcg_gen_addi_tl(cpu_T[0], cpu_T[0], simm); } #ifdef DEBUG_MEMORY_ACCESSES gen_op_print_mem_EA(); @@ -2132,7 +2136,7 @@ static always_inline void gen_addr_reg_index (DisasContext *ctx) } else { tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); - gen_op_add(); + tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]); } #ifdef DEBUG_MEMORY_ACCESSES gen_op_print_mem_EA(); @@ -2331,7 +2335,7 @@ GEN_HANDLER(lq, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX) gen_addr_imm_index(ctx, 0x0F); op_ldst(ld); tcg_gen_mov_tl(cpu_gpr[rd], cpu_T[1]); - gen_op_addi(8); + tcg_gen_addi_tl(cpu_T[0], cpu_T[0], 8); op_ldst(ld); tcg_gen_mov_tl(cpu_gpr[rd + 1], cpu_T[1]); #endif @@ -2427,7 +2431,7 @@ GEN_HANDLER(std, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B) gen_addr_imm_index(ctx, 0x03); tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rs]); op_ldst(std); - gen_op_addi(8); + tcg_gen_addi_tl(cpu_T[0], cpu_T[0], 8); tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rs + 1]); op_ldst(std); #endif @@ -5346,7 +5350,7 @@ static always_inline void gen_addr_spe_imm_index (DisasContext *ctx, int sh) } else { tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); if (likely(simm != 0)) - gen_op_addi(simm << sh); + tcg_gen_addi_tl(cpu_T[0], cpu_T[0], simm << sh); } } -- 1.5.5.1 [-- Attachment #2: op_add.patch --] [-- Type: application/octet-stream, Size: 6282 bytes --] From 14836a73a1ab10ecf795f1cbecac7a72e7e30e43 Mon Sep 17 00:00:00 2001 From: =?utf-8?q?Andreas=20F=C3=A4rber?= <andreas.faerber@web.de> Date: Fri, 5 Sep 2008 00:18:03 +0200 Subject: [PATCH] ppc: Convert op_add, op_addi to TCG --- target-ppc/op.c | 13 ------------- target-ppc/translate.c | 34 +++++++++++++++++++--------------- 2 files changed, 19 insertions(+), 28 deletions(-) diff --git a/target-ppc/op.c b/target-ppc/op.c index 5451fd4..4ee411b 100644 --- a/target-ppc/op.c +++ b/target-ppc/op.c @@ -602,12 +602,6 @@ void OPPROTO op_dec_ctr (void) /*** Integer arithmetic ***/ /* add */ -void OPPROTO op_add (void) -{ - T0 += T1; - RETURN(); -} - void OPPROTO op_check_addo (void) { xer_ov = (((uint32_t)T2 ^ (uint32_t)T1 ^ UINT32_MAX) & @@ -664,13 +658,6 @@ void OPPROTO op_adde_64 (void) } #endif -/* add immediate */ -void OPPROTO op_addi (void) -{ - T0 += (int32_t)PARAM1; - RETURN(); -} - /* add to minus one extended */ void OPPROTO op_add_me (void) { diff --git a/target-ppc/translate.c b/target-ppc/translate.c index d952276..f505be1 100644 --- a/target-ppc/translate.c +++ b/target-ppc/translate.c @@ -827,10 +827,14 @@ __GEN_INT_ARITH1_O_64(name##o, opc1, opc2, opc3 | 0x10, type) #endif /* add add. addo addo. */ +static always_inline void gen_op_add (void) +{ + tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]); +} static always_inline void gen_op_addo (void) { tcg_gen_mov_tl(cpu_T[2], cpu_T[0]); - gen_op_add(); + tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]); gen_op_check_addo(); } #if defined(TARGET_PPC64) @@ -838,7 +842,7 @@ static always_inline void gen_op_addo (void) static always_inline void gen_op_addo_64 (void) { tcg_gen_mov_tl(cpu_T[2], cpu_T[0]); - gen_op_add(); + tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]); gen_op_check_addo_64(); } #endif @@ -847,13 +851,13 @@ GEN_INT_ARITH2_64 (add, 0x1F, 0x0A, 0x08, PPC_INTEGER); static always_inline void gen_op_addc (void) { tcg_gen_mov_tl(cpu_T[2], cpu_T[0]); - gen_op_add(); + tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]); gen_op_check_addc(); } static always_inline void gen_op_addco (void) { tcg_gen_mov_tl(cpu_T[2], cpu_T[0]); - gen_op_add(); + tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]); gen_op_check_addc(); gen_op_check_addo(); } @@ -861,13 +865,13 @@ static always_inline void gen_op_addco (void) static always_inline void gen_op_addc_64 (void) { tcg_gen_mov_tl(cpu_T[2], cpu_T[0]); - gen_op_add(); + tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]); gen_op_check_addc_64(); } static always_inline void gen_op_addco_64 (void) { tcg_gen_mov_tl(cpu_T[2], cpu_T[0]); - gen_op_add(); + tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]); gen_op_check_addc_64(); gen_op_check_addo_64(); } @@ -1022,7 +1026,7 @@ GEN_HANDLER(addi, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) } else { tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); if (likely(simm != 0)) - gen_op_addi(simm); + tcg_gen_addi_tl(cpu_T[0], cpu_T[0], simm); } tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]); } @@ -1034,7 +1038,7 @@ GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); if (likely(simm != 0)) { tcg_gen_mov_tl(cpu_T[2], cpu_T[0]); - gen_op_addi(simm); + tcg_gen_addi_tl(cpu_T[0], cpu_T[0], simm); #if defined(TARGET_PPC64) if (ctx->sf_mode) gen_op_check_addc_64(); @@ -1054,7 +1058,7 @@ GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); if (likely(simm != 0)) { tcg_gen_mov_tl(cpu_T[2], cpu_T[0]); - gen_op_addi(simm); + tcg_gen_addi_tl(cpu_T[0], cpu_T[0], simm); #if defined(TARGET_PPC64) if (ctx->sf_mode) gen_op_check_addc_64(); @@ -1078,7 +1082,7 @@ GEN_HANDLER(addis, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) } else { tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); if (likely(simm != 0)) - gen_op_addi(simm << 16); + tcg_gen_addi_tl(cpu_T[0], cpu_T[0], simm << 16); } tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]); } @@ -2118,7 +2122,7 @@ static always_inline void gen_addr_imm_index (DisasContext *ctx, } else { tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); if (likely(simm != 0)) - gen_op_addi(simm); + tcg_gen_addi_tl(cpu_T[0], cpu_T[0], simm); } #ifdef DEBUG_MEMORY_ACCESSES gen_op_print_mem_EA(); @@ -2132,7 +2136,7 @@ static always_inline void gen_addr_reg_index (DisasContext *ctx) } else { tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); - gen_op_add(); + tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]); } #ifdef DEBUG_MEMORY_ACCESSES gen_op_print_mem_EA(); @@ -2331,7 +2335,7 @@ GEN_HANDLER(lq, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX) gen_addr_imm_index(ctx, 0x0F); op_ldst(ld); tcg_gen_mov_tl(cpu_gpr[rd], cpu_T[1]); - gen_op_addi(8); + tcg_gen_addi_tl(cpu_T[0], cpu_T[0], 8); op_ldst(ld); tcg_gen_mov_tl(cpu_gpr[rd + 1], cpu_T[1]); #endif @@ -2427,7 +2431,7 @@ GEN_HANDLER(std, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B) gen_addr_imm_index(ctx, 0x03); tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rs]); op_ldst(std); - gen_op_addi(8); + tcg_gen_addi_tl(cpu_T[0], cpu_T[0], 8); tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rs + 1]); op_ldst(std); #endif @@ -5346,7 +5350,7 @@ static always_inline void gen_addr_spe_imm_index (DisasContext *ctx, int sh) } else { tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); if (likely(simm != 0)) - gen_op_addi(simm << sh); + tcg_gen_addi_tl(cpu_T[0], cpu_T[0], simm << sh); } } -- 1.5.5.1 ^ permalink raw reply related [flat|nested] 42+ messages in thread
* Re: [Qemu-devel] [PATCH 9/x] ppc: Convert op_add, op_addi to TCG 2008-09-04 22:53 ` [Qemu-devel] [PATCH 9/x] ppc: Convert op_add, op_addi " Andreas Färber @ 2008-09-05 14:18 ` Aurélien Jarno 2008-09-05 17:17 ` Andreas Färber 0 siblings, 1 reply; 42+ messages in thread From: Aurélien Jarno @ 2008-09-05 14:18 UTC (permalink / raw) To: qemu-devel On Fri, Sep 05, 2008 at 12:53:56AM +0200, Andreas Färber wrote: > Replace op_add with tcg_gen_add_tl and op_addi with tcg_gen_addi_tl. > > Signed-off-by: Andreas Faerber <andreas.faerber@web.de> Applied thanks, but see my comment below. > --- > target-ppc/op.c | 13 ------------- > target-ppc/translate.c | 34 +++++++++++++++++++--------------- > 2 files changed, 19 insertions(+), 28 deletions(-) > > diff --git a/target-ppc/op.c b/target-ppc/op.c > index 5451fd4..4ee411b 100644 > --- a/target-ppc/op.c > +++ b/target-ppc/op.c > @@ -602,12 +602,6 @@ void OPPROTO op_dec_ctr (void) > > /*** Integer arithmetic > ***/ > /* add */ > -void OPPROTO op_add (void) > -{ > - T0 += T1; > - RETURN(); > -} > - > void OPPROTO op_check_addo (void) > { > xer_ov = (((uint32_t)T2 ^ (uint32_t)T1 ^ UINT32_MAX) & > @@ -664,13 +658,6 @@ void OPPROTO op_adde_64 (void) > } > #endif > > -/* add immediate */ > -void OPPROTO op_addi (void) > -{ > - T0 += (int32_t)PARAM1; > - RETURN(); > -} > - > /* add to minus one extended */ > void OPPROTO op_add_me (void) > { > diff --git a/target-ppc/translate.c b/target-ppc/translate.c > index d952276..f505be1 100644 > --- a/target-ppc/translate.c > +++ b/target-ppc/translate.c > @@ -827,10 +827,14 @@ __GEN_INT_ARITH1_O_64(name##o, opc1, opc2, opc3 | > 0x10, type) > #endif > > /* add add. addo addo. */ > +static always_inline void gen_op_add (void) > +{ > + tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]); > +} At some point, we will have to change this kind of function, otherwise it will be really difficult to get rid of T0, T1 and T2. > static always_inline void gen_op_addo (void) > { > tcg_gen_mov_tl(cpu_T[2], cpu_T[0]); > - gen_op_add(); > + tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]); > gen_op_check_addo(); > } > #if defined(TARGET_PPC64) > @@ -838,7 +842,7 @@ static always_inline void gen_op_addo (void) > static always_inline void gen_op_addo_64 (void) > { > tcg_gen_mov_tl(cpu_T[2], cpu_T[0]); > - gen_op_add(); > + tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]); > gen_op_check_addo_64(); > } > #endif > @@ -847,13 +851,13 @@ GEN_INT_ARITH2_64 (add, 0x1F, 0x0A, 0x08, > PPC_INTEGER); > static always_inline void gen_op_addc (void) > { > tcg_gen_mov_tl(cpu_T[2], cpu_T[0]); > - gen_op_add(); > + tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]); > gen_op_check_addc(); > } > static always_inline void gen_op_addco (void) > { > tcg_gen_mov_tl(cpu_T[2], cpu_T[0]); > - gen_op_add(); > + tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]); > gen_op_check_addc(); > gen_op_check_addo(); > } > @@ -861,13 +865,13 @@ static always_inline void gen_op_addco (void) > static always_inline void gen_op_addc_64 (void) > { > tcg_gen_mov_tl(cpu_T[2], cpu_T[0]); > - gen_op_add(); > + tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]); > gen_op_check_addc_64(); > } > static always_inline void gen_op_addco_64 (void) > { > tcg_gen_mov_tl(cpu_T[2], cpu_T[0]); > - gen_op_add(); > + tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]); > gen_op_check_addc_64(); > gen_op_check_addo_64(); > } > @@ -1022,7 +1026,7 @@ GEN_HANDLER(addi, 0x0E, 0xFF, 0xFF, 0x00000000, > PPC_INTEGER) > } else { > tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); > if (likely(simm != 0)) > - gen_op_addi(simm); > + tcg_gen_addi_tl(cpu_T[0], cpu_T[0], simm); > } > tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]); > } > @@ -1034,7 +1038,7 @@ GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, > PPC_INTEGER) > tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); > if (likely(simm != 0)) { > tcg_gen_mov_tl(cpu_T[2], cpu_T[0]); > - gen_op_addi(simm); > + tcg_gen_addi_tl(cpu_T[0], cpu_T[0], simm); > #if defined(TARGET_PPC64) > if (ctx->sf_mode) > gen_op_check_addc_64(); > @@ -1054,7 +1058,7 @@ GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, > 0x00000000, PPC_INTEGER) > tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); > if (likely(simm != 0)) { > tcg_gen_mov_tl(cpu_T[2], cpu_T[0]); > - gen_op_addi(simm); > + tcg_gen_addi_tl(cpu_T[0], cpu_T[0], simm); > #if defined(TARGET_PPC64) > if (ctx->sf_mode) > gen_op_check_addc_64(); > @@ -1078,7 +1082,7 @@ GEN_HANDLER(addis, 0x0F, 0xFF, 0xFF, 0x00000000, > PPC_INTEGER) > } else { > tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); > if (likely(simm != 0)) > - gen_op_addi(simm << 16); > + tcg_gen_addi_tl(cpu_T[0], cpu_T[0], simm << 16); > } > tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]); > } > @@ -2118,7 +2122,7 @@ static always_inline void gen_addr_imm_index > (DisasContext *ctx, > } else { > tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); > if (likely(simm != 0)) > - gen_op_addi(simm); > + tcg_gen_addi_tl(cpu_T[0], cpu_T[0], simm); > } > #ifdef DEBUG_MEMORY_ACCESSES > gen_op_print_mem_EA(); > @@ -2132,7 +2136,7 @@ static always_inline void gen_addr_reg_index > (DisasContext *ctx) > } else { > tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); > tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); > - gen_op_add(); > + tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]); > } > #ifdef DEBUG_MEMORY_ACCESSES > gen_op_print_mem_EA(); > @@ -2331,7 +2335,7 @@ GEN_HANDLER(lq, 0x38, 0xFF, 0xFF, 0x00000000, > PPC_64BX) > gen_addr_imm_index(ctx, 0x0F); > op_ldst(ld); > tcg_gen_mov_tl(cpu_gpr[rd], cpu_T[1]); > - gen_op_addi(8); > + tcg_gen_addi_tl(cpu_T[0], cpu_T[0], 8); > op_ldst(ld); > tcg_gen_mov_tl(cpu_gpr[rd + 1], cpu_T[1]); > #endif > @@ -2427,7 +2431,7 @@ GEN_HANDLER(std, 0x3E, 0xFF, 0xFF, 0x00000000, > PPC_64B) > gen_addr_imm_index(ctx, 0x03); > tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rs]); > op_ldst(std); > - gen_op_addi(8); > + tcg_gen_addi_tl(cpu_T[0], cpu_T[0], 8); > tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rs + 1]); > op_ldst(std); > #endif > @@ -5346,7 +5350,7 @@ static always_inline void gen_addr_spe_imm_index > (DisasContext *ctx, int sh) > } else { > tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); > if (likely(simm != 0)) > - gen_op_addi(simm << sh); > + tcg_gen_addi_tl(cpu_T[0], cpu_T[0], simm << sh); > } > } > > -- > 1.5.5.1 > -- .''`. Aurelien Jarno | GPG: 1024D/F1BCDB73 : :' : Debian developer | Electrical Engineer `. `' aurel32@debian.org | aurelien@aurel32.net `- people.debian.org/~aurel32 | www.aurel32.net ^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [Qemu-devel] [PATCH 9/x] ppc: Convert op_add, op_addi to TCG 2008-09-05 14:18 ` Aurélien Jarno @ 2008-09-05 17:17 ` Andreas Färber 2008-09-05 17:49 ` Aurelien Jarno 0 siblings, 1 reply; 42+ messages in thread From: Andreas Färber @ 2008-09-05 17:17 UTC (permalink / raw) To: qemu-devel Am 05.09.2008 um 16:18 schrieb Aurélien Jarno: >> --- a/target-ppc/translate.c >> +++ b/target-ppc/translate.c >> @@ -827,10 +827,14 @@ __GEN_INT_ARITH1_O_64(name##o, opc1, opc2, >> opc3 | >> 0x10, type) >> #endif >> >> /* add add. addo addo. */ >> +static always_inline void gen_op_add (void) >> +{ >> + tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]); >> +} > > At some point, we will have to change this kind of function, otherwise > it will be really difficult to get rid of T0, T1 and T2. Right, same for subf. But for now, a function of this name is still required here for the add instruction due to the GEN_INT_ARITH2 (or similar) macro slightly below, which appears to set up these functions as handlers for the family of instruction opcodes iiuc. To change those macros, the whole family (or even more instructions) will need to be converted first. For me, the use of global TCG variables should permit it to run on Mac OS X Leopard with GCC 4.0.1 at some point, so even if it doesn't allow optimizations right away, it has some mid-term benefits. For the other occurrences of gen_op_add I already inlined it for future optimizations but didn't spot opportunities to do that yet. I will be mostly offline starting this weekend but would likely continue working on ppc. If anyone else plans to work on it, it would be nice to coordinate that in advance to avoid conflicting patches. Andreas ^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [Qemu-devel] [PATCH 9/x] ppc: Convert op_add, op_addi to TCG 2008-09-05 17:17 ` Andreas Färber @ 2008-09-05 17:49 ` Aurelien Jarno 0 siblings, 0 replies; 42+ messages in thread From: Aurelien Jarno @ 2008-09-05 17:49 UTC (permalink / raw) To: qemu-devel On Fri, Sep 05, 2008 at 07:17:10PM +0200, Andreas Färber wrote: > > Am 05.09.2008 um 16:18 schrieb Aurélien Jarno: > >>> --- a/target-ppc/translate.c >>> +++ b/target-ppc/translate.c >>> @@ -827,10 +827,14 @@ __GEN_INT_ARITH1_O_64(name##o, opc1, opc2, >>> opc3 | >>> 0x10, type) >>> #endif >>> >>> /* add add. addo addo. */ >>> +static always_inline void gen_op_add (void) >>> +{ >>> + tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]); >>> +} >> >> At some point, we will have to change this kind of function, otherwise >> it will be really difficult to get rid of T0, T1 and T2. > > Right, same for subf. But for now, a function of this name is still > required here for the add instruction due to the GEN_INT_ARITH2 (or > similar) macro slightly below, which appears to set up these functions > as handlers for the family of instruction opcodes iiuc. To change those > macros, the whole family (or even more instructions) will need to be > converted first. > > For me, the use of global TCG variables should permit it to run on Mac > OS X Leopard with GCC 4.0.1 at some point, so even if it doesn't allow > optimizations right away, it has some mid-term benefits. For the other > occurrences of gen_op_add I already inlined it for future optimizations > but didn't spot opportunities to do that yet. > > I will be mostly offline starting this weekend but would likely continue > working on ppc. If anyone else plans to work on it, it would be nice to > coordinate that in advance to avoid conflicting patches. I plan to work on memory loads/stores during the week-end. Note that I'll be offline on Sunday. -- .''`. Aurelien Jarno | GPG: 1024D/F1BCDB73 : :' : Debian developer | Electrical Engineer `. `' aurel32@debian.org | aurelien@aurel32.net `- people.debian.org/~aurel32 | www.aurel32.net ^ permalink raw reply [flat|nested] 42+ messages in thread
* [Qemu-devel] [PATCH 10/x] ppc: Convert op_subf to TCG 2008-09-04 20:36 ` Aurélien Jarno 2008-09-04 22:53 ` [Qemu-devel] [PATCH 9/x] ppc: Convert op_add, op_addi " Andreas Färber @ 2008-09-04 23:46 ` Andreas Färber 2008-09-05 14:18 ` Aurélien Jarno 1 sibling, 1 reply; 42+ messages in thread From: Andreas Färber @ 2008-09-04 23:46 UTC (permalink / raw) To: qemu-devel; +Cc: Aurélien Jarno [-- Attachment #1: Type: text/plain, Size: 2508 bytes --] Replace op_subf with tcg_gen_sub_tl. Signed-off-by: Andreas Faerber <andreas.faerber@web.de> --- target-ppc/op.c | 7 ------- target-ppc/translate.c | 16 ++++++++++------ 2 files changed, 10 insertions(+), 13 deletions(-) diff --git a/target-ppc/op.c b/target-ppc/op.c index 4ee411b..01b944b 100644 --- a/target-ppc/op.c +++ b/target-ppc/op.c @@ -881,13 +881,6 @@ void OPPROTO op_nego_64 (void) } #endif -/* subtract from */ -void OPPROTO op_subf (void) -{ - T0 = T1 - T0; - RETURN(); -} - /* subtract from carrying */ void OPPROTO op_check_subfc (void) { diff --git a/target-ppc/translate.c b/target-ppc/translate.c index f505be1..6561304 100644 --- a/target-ppc/translate.c +++ b/target-ppc/translate.c @@ -950,10 +950,14 @@ GEN_INT_ARITH2 (mullw, 0x1F, 0x0B, 0x07, PPC_INTEGER); /* neg neg. nego nego. */ GEN_INT_ARITH1_64 (neg, 0x1F, 0x08, 0x03, PPC_INTEGER); /* subf subf. subfo subfo. */ +static always_inline void gen_op_subf (void) +{ + tcg_gen_sub_tl(cpu_T[0], cpu_T[1], cpu_T[0]); +} static always_inline void gen_op_subfo (void) { tcg_gen_not_tl(cpu_T[2], cpu_T[0]); - gen_op_subf(); + tcg_gen_sub_tl(cpu_T[0], cpu_T[1], cpu_T[0]); gen_op_check_addo(); } #if defined(TARGET_PPC64) @@ -961,7 +965,7 @@ static always_inline void gen_op_subfo (void) static always_inline void gen_op_subfo_64 (void) { tcg_gen_not_i64(cpu_T[2], cpu_T[0]); - gen_op_subf(); + tcg_gen_sub_tl(cpu_T[0], cpu_T[1], cpu_T[0]); gen_op_check_addo_64(); } #endif @@ -969,26 +973,26 @@ GEN_INT_ARITH2_64 (subf, 0x1F, 0x08, 0x01, PPC_INTEGER); /* subfc subfc. subfco subfco. */ static always_inline void gen_op_subfc (void) { - gen_op_subf(); + tcg_gen_sub_tl(cpu_T[0], cpu_T[1], cpu_T[0]); gen_op_check_subfc(); } static always_inline void gen_op_subfco (void) { tcg_gen_not_tl(cpu_T[2], cpu_T[0]); - gen_op_subf(); + tcg_gen_sub_tl(cpu_T[0], cpu_T[1], cpu_T[0]); gen_op_check_subfc(); gen_op_check_addo(); } #if defined(TARGET_PPC64) static always_inline void gen_op_subfc_64 (void) { - gen_op_subf(); + tcg_gen_sub_tl(cpu_T[0], cpu_T[1], cpu_T[0]); gen_op_check_subfc_64(); } static always_inline void gen_op_subfco_64 (void) { tcg_gen_not_i64(cpu_T[2], cpu_T[0]); - gen_op_subf(); + tcg_gen_sub_tl(cpu_T[0], cpu_T[1], cpu_T[0]); gen_op_check_subfc_64(); gen_op_check_addo_64(); } -- 1.5.5.1 [-- Attachment #2: op_subf.patch --] [-- Type: application/octet-stream, Size: 2675 bytes --] From 09d5cd4f669b8fcaba52a02fdf1034c5f8bccce3 Mon Sep 17 00:00:00 2001 From: =?utf-8?q?Andreas=20F=C3=A4rber?= <andreas.faerber@web.de> Date: Fri, 5 Sep 2008 01:19:19 +0200 Subject: [PATCH] ppc: Convert op_subf to TCG --- target-ppc/op.c | 7 ------- target-ppc/translate.c | 16 ++++++++++------ 2 files changed, 10 insertions(+), 13 deletions(-) diff --git a/target-ppc/op.c b/target-ppc/op.c index 4ee411b..01b944b 100644 --- a/target-ppc/op.c +++ b/target-ppc/op.c @@ -881,13 +881,6 @@ void OPPROTO op_nego_64 (void) } #endif -/* subtract from */ -void OPPROTO op_subf (void) -{ - T0 = T1 - T0; - RETURN(); -} - /* subtract from carrying */ void OPPROTO op_check_subfc (void) { diff --git a/target-ppc/translate.c b/target-ppc/translate.c index f505be1..6561304 100644 --- a/target-ppc/translate.c +++ b/target-ppc/translate.c @@ -950,10 +950,14 @@ GEN_INT_ARITH2 (mullw, 0x1F, 0x0B, 0x07, PPC_INTEGER); /* neg neg. nego nego. */ GEN_INT_ARITH1_64 (neg, 0x1F, 0x08, 0x03, PPC_INTEGER); /* subf subf. subfo subfo. */ +static always_inline void gen_op_subf (void) +{ + tcg_gen_sub_tl(cpu_T[0], cpu_T[1], cpu_T[0]); +} static always_inline void gen_op_subfo (void) { tcg_gen_not_tl(cpu_T[2], cpu_T[0]); - gen_op_subf(); + tcg_gen_sub_tl(cpu_T[0], cpu_T[1], cpu_T[0]); gen_op_check_addo(); } #if defined(TARGET_PPC64) @@ -961,7 +965,7 @@ static always_inline void gen_op_subfo (void) static always_inline void gen_op_subfo_64 (void) { tcg_gen_not_i64(cpu_T[2], cpu_T[0]); - gen_op_subf(); + tcg_gen_sub_tl(cpu_T[0], cpu_T[1], cpu_T[0]); gen_op_check_addo_64(); } #endif @@ -969,26 +973,26 @@ GEN_INT_ARITH2_64 (subf, 0x1F, 0x08, 0x01, PPC_INTEGER); /* subfc subfc. subfco subfco. */ static always_inline void gen_op_subfc (void) { - gen_op_subf(); + tcg_gen_sub_tl(cpu_T[0], cpu_T[1], cpu_T[0]); gen_op_check_subfc(); } static always_inline void gen_op_subfco (void) { tcg_gen_not_tl(cpu_T[2], cpu_T[0]); - gen_op_subf(); + tcg_gen_sub_tl(cpu_T[0], cpu_T[1], cpu_T[0]); gen_op_check_subfc(); gen_op_check_addo(); } #if defined(TARGET_PPC64) static always_inline void gen_op_subfc_64 (void) { - gen_op_subf(); + tcg_gen_sub_tl(cpu_T[0], cpu_T[1], cpu_T[0]); gen_op_check_subfc_64(); } static always_inline void gen_op_subfco_64 (void) { tcg_gen_not_i64(cpu_T[2], cpu_T[0]); - gen_op_subf(); + tcg_gen_sub_tl(cpu_T[0], cpu_T[1], cpu_T[0]); gen_op_check_subfc_64(); gen_op_check_addo_64(); } -- 1.5.5.1 ^ permalink raw reply related [flat|nested] 42+ messages in thread
* Re: [Qemu-devel] [PATCH 10/x] ppc: Convert op_subf to TCG 2008-09-04 23:46 ` [Qemu-devel] [PATCH 10/x] ppc: Convert op_subf " Andreas Färber @ 2008-09-05 14:18 ` Aurélien Jarno 0 siblings, 0 replies; 42+ messages in thread From: Aurélien Jarno @ 2008-09-05 14:18 UTC (permalink / raw) To: qemu-devel On Fri, Sep 05, 2008 at 01:46:42AM +0200, Andreas Färber wrote: > Replace op_subf with tcg_gen_sub_tl. > > Signed-off-by: Andreas Faerber <andreas.faerber@web.de> Applied thanks. > --- > target-ppc/op.c | 7 ------- > target-ppc/translate.c | 16 ++++++++++------ > 2 files changed, 10 insertions(+), 13 deletions(-) > > diff --git a/target-ppc/op.c b/target-ppc/op.c > index 4ee411b..01b944b 100644 > --- a/target-ppc/op.c > +++ b/target-ppc/op.c > @@ -881,13 +881,6 @@ void OPPROTO op_nego_64 (void) > } > #endif > > -/* subtract from */ > -void OPPROTO op_subf (void) > -{ > - T0 = T1 - T0; > - RETURN(); > -} > - > /* subtract from carrying */ > void OPPROTO op_check_subfc (void) > { > diff --git a/target-ppc/translate.c b/target-ppc/translate.c > index f505be1..6561304 100644 > --- a/target-ppc/translate.c > +++ b/target-ppc/translate.c > @@ -950,10 +950,14 @@ GEN_INT_ARITH2 (mullw, 0x1F, 0x0B, 0x07, > PPC_INTEGER); > /* neg neg. nego nego. */ > GEN_INT_ARITH1_64 (neg, 0x1F, 0x08, 0x03, PPC_INTEGER); > /* subf subf. subfo subfo. */ > +static always_inline void gen_op_subf (void) > +{ > + tcg_gen_sub_tl(cpu_T[0], cpu_T[1], cpu_T[0]); > +} > static always_inline void gen_op_subfo (void) > { > tcg_gen_not_tl(cpu_T[2], cpu_T[0]); > - gen_op_subf(); > + tcg_gen_sub_tl(cpu_T[0], cpu_T[1], cpu_T[0]); > gen_op_check_addo(); > } > #if defined(TARGET_PPC64) > @@ -961,7 +965,7 @@ static always_inline void gen_op_subfo (void) > static always_inline void gen_op_subfo_64 (void) > { > tcg_gen_not_i64(cpu_T[2], cpu_T[0]); > - gen_op_subf(); > + tcg_gen_sub_tl(cpu_T[0], cpu_T[1], cpu_T[0]); > gen_op_check_addo_64(); > } > #endif > @@ -969,26 +973,26 @@ GEN_INT_ARITH2_64 (subf, 0x1F, 0x08, 0x01, > PPC_INTEGER); > /* subfc subfc. subfco subfco. */ > static always_inline void gen_op_subfc (void) > { > - gen_op_subf(); > + tcg_gen_sub_tl(cpu_T[0], cpu_T[1], cpu_T[0]); > gen_op_check_subfc(); > } > static always_inline void gen_op_subfco (void) > { > tcg_gen_not_tl(cpu_T[2], cpu_T[0]); > - gen_op_subf(); > + tcg_gen_sub_tl(cpu_T[0], cpu_T[1], cpu_T[0]); > gen_op_check_subfc(); > gen_op_check_addo(); > } > #if defined(TARGET_PPC64) > static always_inline void gen_op_subfc_64 (void) > { > - gen_op_subf(); > + tcg_gen_sub_tl(cpu_T[0], cpu_T[1], cpu_T[0]); > gen_op_check_subfc_64(); > } > static always_inline void gen_op_subfco_64 (void) > { > tcg_gen_not_i64(cpu_T[2], cpu_T[0]); > - gen_op_subf(); > + tcg_gen_sub_tl(cpu_T[0], cpu_T[1], cpu_T[0]); > gen_op_check_subfc_64(); > gen_op_check_addo_64(); > } > -- > 1.5.5.1 > -- .''`. Aurelien Jarno | GPG: 1024D/F1BCDB73 : :' : Debian developer | Electrical Engineer `. `' aurel32@debian.org | aurelien@aurel32.net `- people.debian.org/~aurel32 | www.aurel32.net ^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [Qemu-devel] [PATCH 6/x] ppc: Convert Altivec register moves to TCG 2008-09-04 12:24 ` [Qemu-devel] [PATCH 6/x] ppc: Convert Altivec register " Andreas Färber 2008-09-04 14:08 ` [Qemu-devel] [PATCH 7/x] ppc: Convert FPR " Andreas Färber @ 2008-09-04 14:39 ` Aurélien Jarno 1 sibling, 0 replies; 42+ messages in thread From: Aurélien Jarno @ 2008-09-04 14:39 UTC (permalink / raw) To: qemu-devel On Thu, Sep 04, 2008 at 02:24:17PM +0200, Andreas Färber wrote: > Replace op_{load,store}_avr with helpers gen_{load,store}_avr. > Introduce two sets of i64 TCG variables, cpu_avr{h,l}[0..31], and > cpu_AVR{h,l}[0..2]. > > Signed-off-by: Andreas Faerber <andreas.faerber@web.de> > > --- > In the future this might be improved with a > tcg_mem_alloc_new(TCG_TYPE_I128, ...) and corresponding move op on the > TCG side of things. But for now, handling it in the target cuts down > op_template.h to floating point and condition register moves. Applied, thanks. > Andreas > > target-ppc/op_template.h | 39 ----------------------------------- > target-ppc/translate.c | 50 +++++++++++++++++++++++++++++++++ > +------------ > 2 files changed, 37 insertions(+), 52 deletions(-) > > diff --git a/target-ppc/op_template.h b/target-ppc/op_template.h > index 8c65e49..64e38a9 100644 > --- a/target-ppc/op_template.h > +++ b/target-ppc/op_template.h > @@ -18,45 +18,6 @@ > * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 > USA > */ > > -/* Altivec registers moves */ > -void OPPROTO glue(op_load_avr_A0_avr, REG) (void) > -{ > - AVR0 = env->avr[REG]; > - RETURN(); > -} > - > -void OPPROTO glue(op_load_avr_A1_avr, REG) (void) > -{ > - AVR1 = env->avr[REG]; > - RETURN(); > -} > - > -void OPPROTO glue(op_load_avr_A2_avr, REG) (void) > -{ > - AVR2 = env->avr[REG]; > - RETURN(); > -} > - > -void OPPROTO glue(op_store_A0_avr_avr, REG) (void) > -{ > - env->avr[REG] = AVR0; > - RETURN(); > -} > - > -void OPPROTO glue(op_store_A1_avr_avr, REG) (void) > -{ > - env->avr[REG] = AVR1; > - RETURN(); > -} > - > -#if 0 // unused > -void OPPROTO glue(op_store_A2_avr_avr, REG) (void) > -{ > - env->avr[REG] = AVR2; > - RETURN(); > -} > -#endif > - > #if REG <= 7 > /* Condition register moves */ > void OPPROTO glue(op_load_crf_T0_crf, REG) (void) > diff --git a/target-ppc/translate.c b/target-ppc/translate.c > index ea51716..0674376 100644 > --- a/target-ppc/translate.c > +++ b/target-ppc/translate.c > @@ -46,15 +46,16 @@ > > /* global register indexes */ > static TCGv cpu_env; > -static char cpu_reg_names[10*3 + 22*4 > +static char cpu_reg_names[10*3 + 22*4 /* GPR */ > #if !defined(TARGET_PPC64) > - + 10*4 + 22*5 > + + 10*4 + 22*5 /* SPE GPRh */ > #endif > -]; > + + 2*(10*6 + 22*7) /* AVRh, AVRl */]; > static TCGv cpu_gpr[32]; > #if !defined(TARGET_PPC64) > static TCGv cpu_gprh[32]; > #endif > +static TCGv cpu_avrh[32], cpu_avrl[32]; > > /* dyngen register indexes */ > static TCGv cpu_T[3]; > @@ -63,6 +64,7 @@ static TCGv cpu_T[3]; > #else > static TCGv cpu_T64[3]; > #endif > +static TCGv cpu_AVRh[3], cpu_AVRl[3]; > > #include "gen-icount.h" > > @@ -99,6 +101,18 @@ void ppc_translate_init(void) > TCG_AREG0, offsetof(CPUState, > t2_64), > "T2_64"); > #endif > + cpu_AVRh[0] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0, > + offsetof(CPUState, avr0.u64[0]), > "AVR0H"); > + cpu_AVRl[0] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0, > + offsetof(CPUState, avr0.u64[1]), > "AVR0L"); > + cpu_AVRh[1] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0, > + offsetof(CPUState, avr1.u64[0]), > "AVR1H"); > + cpu_AVRl[1] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0, > + offsetof(CPUState, avr1.u64[1]), > "AVR1L"); > + cpu_AVRh[2] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0, > + offsetof(CPUState, avr2.u64[0]), > "AVR2H"); > + cpu_AVRl[2] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0, > + offsetof(CPUState, avr2.u64[1]), > "AVR2L"); > > p = cpu_reg_names; > for (i = 0; i < 32; i++) { > @@ -112,6 +126,15 @@ void ppc_translate_init(void) > offsetof(CPUState, gprh[i]), > p); > p += (i < 10) ? 4 : 5; > #endif > + > + sprintf(p, "avr%dH", i); > + cpu_avrh[i] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0, > + offsetof(CPUState, > avr[i].u64[0]), p); > + p += (i < 10) ? 6 : 7; > + sprintf(p, "avr%dL", i); > + cpu_avrl[i] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0, > + offsetof(CPUState, > avr[i].u64[1]), p); > + p += (i < 10) ? 6 : 7; > } > > /* register helpers */ > @@ -5241,15 +5264,16 @@ GEN_HANDLER2(icbt_440, "icbt", 0x1F, 0x16, 0x00, > 0x03E00001, PPC_BOOKE) > > /*** Altivec vector extension > ***/ > /* Altivec registers moves */ > -GEN32(gen_op_load_avr_A0, gen_op_load_avr_A0_avr); > -GEN32(gen_op_load_avr_A1, gen_op_load_avr_A1_avr); > -GEN32(gen_op_load_avr_A2, gen_op_load_avr_A2_avr); > > -GEN32(gen_op_store_A0_avr, gen_op_store_A0_avr_avr); > -GEN32(gen_op_store_A1_avr, gen_op_store_A1_avr_avr); > -#if 0 // unused > -GEN32(gen_op_store_A2_avr, gen_op_store_A2_avr_avr); > -#endif > +static always_inline void gen_load_avr(int t, int reg) { > + tcg_gen_mov_i64(cpu_AVRh[t], cpu_avrh[reg]); > + tcg_gen_mov_i64(cpu_AVRl[t], cpu_avrl[reg]); > +} > + > +static always_inline void gen_store_avr(int reg, int t) { > + tcg_gen_mov_i64(cpu_avrh[reg], cpu_AVRh[t]); > + tcg_gen_mov_i64(cpu_avrl[reg], cpu_AVRl[t]); > +} > > #define op_vr_ldst(name) (*gen_op_##name[ctx->mem_idx])() > #define OP_VR_LD_TABLE(name) > \ > @@ -5270,7 +5294,7 @@ GEN_HANDLER(l##name, 0x1F, opc2, opc3, 0x00000001, > PPC_ALTIVEC) \ > } \ > gen_addr_reg_index(ctx); > \ > op_vr_ldst(vr_l##name); > \ > - gen_op_store_A0_avr(rD(ctx->opcode)); > \ > + gen_store_avr(rD(ctx->opcode), 0); > \ > } > > #define GEN_VR_STX(name, opc2, opc3) > \ > @@ -5281,7 +5305,7 @@ GEN_HANDLER(st##name, 0x1F, opc2, opc3, > 0x00000001, PPC_ALTIVEC) \ > return; > \ > } \ > gen_addr_reg_index(ctx); > \ > - gen_op_load_avr_A0(rS(ctx->opcode)); > \ > + gen_load_avr(0, rS(ctx->opcode)); > \ > op_vr_ldst(vr_st##name); > \ > } > > -- > 1.5.5.1 > -- .''`. Aurelien Jarno | GPG: 1024D/F1BCDB73 : :' : Debian developer | Electrical Engineer `. `' aurel32@debian.org | aurelien@aurel32.net `- people.debian.org/~aurel32 | www.aurel32.net ^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [Qemu-devel] [PATCH 5/x] ppc: Convert op_load_gpr_{T0, T1, T2} to TCG 2008-09-03 19:00 ` Andreas Färber 2008-09-03 19:12 ` Blue Swirl @ 2008-09-07 14:22 ` Paul Brook 1 sibling, 0 replies; 42+ messages in thread From: Paul Brook @ 2008-09-07 14:22 UTC (permalink / raw) To: qemu-devel; +Cc: Andreas Färber > > Can't you use extu_i32_i64 followed by shift and then or? I think you > > should not use TCGV_HIGH outside tcg directory, it's an implementation > > detail. > > Thanks for the suggestion! You mean like this? > > static always_inline void gen_load_gpr64(TCGv t, int reg) { > #if defined(TARGET_PPC64) > tcg_gen_mov_i64(t, cpu_gpr[reg]); > #else > tcg_gen_extu_i32_i64(t, cpu_gprh[reg]); > tcg_gen_shli_i64(t, t, 32); > TCGv tmp = tcg_temp_local_new(TCG_TYPE_I64); > tcg_gen_extu_i32_i64(tmp, cpu_gpr[reg]); > tcg_gen_or_i64(t, t, tmp); > tcg_temp_free(tmp); > #endif > } It's probably worth making a separate helper function for concatenating two 32-bit operands into a 64-bit operand so that it can be implemented natively. I doubt whether the TCG code is smart enough to DTRT there. Paul ^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [Qemu-devel] [PATCH 5/x] ppc: Convert op_load_gpr_{T0, T1, T2} to TCG 2008-09-03 10:41 ` Andreas Färber 2008-09-03 11:28 ` Thiemo Seufer @ 2008-09-03 12:41 ` Aurélien Jarno 2008-09-03 12:58 ` Andreas Färber 1 sibling, 1 reply; 42+ messages in thread From: Aurélien Jarno @ 2008-09-03 12:41 UTC (permalink / raw) To: Andreas Färber; +Cc: qemu-devel On Wed, Sep 03, 2008 at 12:41:01PM +0200, Andreas Färber wrote: > > Am 03.09.2008 um 07:07 schrieb Aurelien Jarno: > > >On Wed, Sep 03, 2008 at 02:39:52AM +0200, Andreas Färber wrote: > >> > >>Am 03.09.2008 um 01:20 schrieb Aurelien Jarno: > >> > >>> > >>>>+ for (i = 0; i < 32; i++) { > >>>>+ cpu_gpr[i] = tcg_global_mem_new(TCG_TYPE_TL, TCG_AREG0, > >>>>+ offsetof(CPUState, > >>>>gpr[i]), > >>>>+ gprnames[i]); > >>> > >>>This is most probably wrong given the definition of ppc_gpr_t in > >>>cpu.h: > >>>- 64 bits on 64-bit targets > >>>- 32 bits on 32-bit targets and 32-bit hosts > >>>- *64 bits* on 32-bit targets and 64-bit hosts > >>> > >>>I think it is a bit weird, and I think the best is to modify cpu.h > >>>in > >>>order to have ppc_gpr_t matching the target bitness. > >> > >>This might be related to the 64-on-32 issue I just posted about. I > >>don't > >>remember seeing code that makes use of this sophisticated definition > >>though, for non-ppc64 it apparently uses a set of 32-bit gpr and gprh > >>variables. Let's not change ppc_gpr_t for now. > > > >Well that's different, your previous post is about T_* registers, I am > >speaking about the GPR registers. And either ppc_gpr_t or the init > >code > >of cpu_gpr[i] has to be changed, otherwise you will break existing > >targets. > > I'm quite sure it is related - the issue is that GPR / T TCGv size > does not always correspond to tl, and the only problem is the 32-bit > target with 64-bit host. > > Would there be a problem with using i64 in the 32-on-64 case? That is, > would it hurt to do i32 TCG operations on i64 variables on a 64-bit > host? If not, we could keep tl for the regular instructions and use > i64 for ppc64/ppc-on-64 and 2x i32 on ppc-on-32. That sounds more > efficient than reverting the ppc_gpr_t optimization and always using > 2x i32 independent of the host bitness. We'll need an inlined helper > for these any way. This optimization has been done with dyngen in mind, we surely don't want to keep it with TCG. I currently have plenty of time, but almost no network (travelling), so I'll work on implementing a solution, and commit the result most probably tomorrow morning. -- .''`. Aurelien Jarno | GPG: 1024D/F1BCDB73 : :' : Debian developer | Electrical Engineer `. `' aurel32@debian.org | aurelien@aurel32.net `- people.debian.org/~aurel32 | www.aurel32.net ^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [Qemu-devel] [PATCH 5/x] ppc: Convert op_load_gpr_{T0, T1, T2} to TCG 2008-09-03 12:41 ` Aurélien Jarno @ 2008-09-03 12:58 ` Andreas Färber 2008-09-03 13:00 ` Aurélien Jarno ` (2 more replies) 0 siblings, 3 replies; 42+ messages in thread From: Andreas Färber @ 2008-09-03 12:58 UTC (permalink / raw) To: Aurélien Jarno; +Cc: qemu-devel Aurélien, Am 03.09.2008 um 14:41 schrieb Aurélien Jarno: > This optimization has been done with dyngen in mind, we surely don't > want to keep it with TCG. > > I currently have plenty of time, but almost no network (travelling), > so > I'll work on implementing a solution, and commit the result most > probably > tomorrow morning. I already have a solution cooking for cpu_T64 and SPE, including improved TCGv setup. It'll be no problem for me to incorporate your and Thiemo's comments in my revised patch. SPE will be rarely used anyway I guess, so I think it's relatively "safe" for me to remove the dyngen optimization and simplify ppc_gpr_t during this transition. Since you requested larger patches, I started to merge gpr64 into it and was planning to convert the stores as well in one go. It doesn't sound too promising if we both make changes at the same places now... Andreas ^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [Qemu-devel] [PATCH 5/x] ppc: Convert op_load_gpr_{T0, T1, T2} to TCG 2008-09-03 12:58 ` Andreas Färber @ 2008-09-03 13:00 ` Aurélien Jarno 2008-09-03 13:23 ` Thiemo Seufer 2008-09-03 16:04 ` Andreas Färber 2 siblings, 0 replies; 42+ messages in thread From: Aurélien Jarno @ 2008-09-03 13:00 UTC (permalink / raw) To: Andreas Färber; +Cc: qemu-devel On Wed, Sep 03, 2008 at 02:58:30PM +0200, Andreas Färber wrote: > Aurélien, > > Am 03.09.2008 um 14:41 schrieb Aurélien Jarno: > > >This optimization has been done with dyngen in mind, we surely don't > >want to keep it with TCG. > > > >I currently have plenty of time, but almost no network (travelling), > >so > >I'll work on implementing a solution, and commit the result most > >probably > >tomorrow morning. > > I already have a solution cooking for cpu_T64 and SPE, including > improved TCGv setup. It'll be no problem for me to incorporate your > and Thiemo's comments in my revised patch. > > SPE will be rarely used anyway I guess, so I think it's relatively > "safe" for me to remove the dyngen optimization and simplify ppc_gpr_t > during this transition. Since you requested larger patches, I started > to merge gpr64 into it and was planning to convert the stores as well > in one go. It doesn't sound too promising if we both make changes at > the same places now... > I see, I'll work on alpha then. -- .''`. Aurelien Jarno | GPG: 1024D/F1BCDB73 : :' : Debian developer | Electrical Engineer `. `' aurel32@debian.org | aurelien@aurel32.net `- people.debian.org/~aurel32 | www.aurel32.net ^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [Qemu-devel] [PATCH 5/x] ppc: Convert op_load_gpr_{T0, T1, T2} to TCG 2008-09-03 12:58 ` Andreas Färber 2008-09-03 13:00 ` Aurélien Jarno @ 2008-09-03 13:23 ` Thiemo Seufer 2008-09-03 13:45 ` Tristan Gingold 2008-09-03 16:04 ` Andreas Färber 2 siblings, 1 reply; 42+ messages in thread From: Thiemo Seufer @ 2008-09-03 13:23 UTC (permalink / raw) To: Andreas Färber; +Cc: qemu-devel, Aurélien Jarno Andreas Färber wrote: > Aurélien, > > Am 03.09.2008 um 14:41 schrieb Aurélien Jarno: > >> This optimization has been done with dyngen in mind, we surely don't >> want to keep it with TCG. >> >> I currently have plenty of time, but almost no network (travelling), >> so >> I'll work on implementing a solution, and commit the result most >> probably >> tomorrow morning. > > I already have a solution cooking for cpu_T64 and SPE, including > improved TCGv setup. It'll be no problem for me to incorporate your and > Thiemo's comments in my revised patch. > > SPE will be rarely used anyway I guess, JFTR, there are Freescale MPC85xx boards which use the SPE floating point support (and thus have a different ABI than normal Linux PPC). I'm currently working on a Debian port for it and tried to use Qemu's system emulation, however I didn't manage to get it to work in the limited time available. So I'm less concerned with SPE performance and more with getting usable SPE support at all. :-) Thiemo ^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [Qemu-devel] [PATCH 5/x] ppc: Convert op_load_gpr_{T0, T1, T2} to TCG 2008-09-03 13:23 ` Thiemo Seufer @ 2008-09-03 13:45 ` Tristan Gingold 0 siblings, 0 replies; 42+ messages in thread From: Tristan Gingold @ 2008-09-03 13:45 UTC (permalink / raw) To: qemu-devel; +Cc: Andreas Färber, Aurélien Jarno > I'm currently working on a Debian port for it and tried to use Qemu's > system emulation, however I didn't manage to get it to work in the > limited time available. > > So I'm less concerned with SPE performance and more with getting > usable SPE support at all. :-) From my experience, the SPE instruction support is quiet complete. However no SPE cpus are supported (no support for MMU for example). ^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [Qemu-devel] [PATCH 5/x] ppc: Convert op_load_gpr_{T0, T1, T2} to TCG 2008-09-03 12:58 ` Andreas Färber 2008-09-03 13:00 ` Aurélien Jarno 2008-09-03 13:23 ` Thiemo Seufer @ 2008-09-03 16:04 ` Andreas Färber 2 siblings, 0 replies; 42+ messages in thread From: Andreas Färber @ 2008-09-03 16:04 UTC (permalink / raw) To: qemu-devel; +Cc: Aurélien Jarno Am 03.09.2008 um 14:58 schrieb Andreas Färber: > Am 03.09.2008 um 14:41 schrieb Aurélien Jarno: > >> This optimization has been done with dyngen in mind, we surely don't >> want to keep it with TCG. >> >> I currently have plenty of time, but almost no network >> (travelling), so >> I'll work on implementing a solution, and commit the result most >> probably >> tomorrow morning. > > I already have a solution cooking for cpu_T64 and SPE, including > improved TCGv setup. It'll be no problem for me to incorporate your > and Thiemo's comments in my revised patch. Here's a draft of what I've come up with so far: - Based on your comments, make the GPRs always 32-bit for ppc and 64- bit for ppc64. - Introduce cpu_T64[0..2], for ppc. (required a change in cpu.h for 64- bit host) - Introduce cpu_gprh[0..31] in addition to cpu_gpr[0..31], for ppc only. - Use sprintf for cpu_gpr, cpu_gprh names. diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h index 834c08d..c7291ed 100644 --- a/target-ppc/cpu.h +++ b/target-ppc/cpu.h @@ -33,17 +33,7 @@ typedef uint64_t ppc_gpr_t; #else /* defined (TARGET_PPC64) */ /* PowerPC 32 definitions */ -#if (HOST_LONG_BITS >= 64) -/* When using 64 bits temporary registers, - * we can use 64 bits GPR with no extra cost - * It's even an optimization as this will prevent - * the compiler to do unuseful masking in the micro-ops. - */ -typedef uint64_t ppc_gpr_t; -#else /* (HOST_LONG_BITS >= 64) */ typedef uint32_t ppc_gpr_t; -#endif /* (HOST_LONG_BITS >= 64) */ - #define TARGET_LONG_BITS 32 #if defined(TARGET_PPCEMB) @@ -541,7 +531,7 @@ struct CPUPPCState { /* First are the most commonly used resources * during translated code execution */ -#if (HOST_LONG_BITS == 32) +#if (TARGET_LONG_BITS > HOST_LONG_BITS) || !defined(TARGET_PPC64) /* temporary fixed-point registers * used to emulate 64 bits registers on 32 bits hosts */ diff --git a/target-ppc/translate.c b/target-ppc/translate.c index 9068936..c8ecfe2 100644 --- a/target-ppc/translate.c +++ b/target-ppc/translate.c @@ -44,15 +44,37 @@ / *****************************************************************************/ /* Code translation helpers */ -static TCGv cpu_env, cpu_T[3]; +/* global register indexes */ +static TCGv cpu_env; +static char cpu_reg_names[10*3 + 22*4 +#if !defined(TARGET_PPC64) + + 10*4 + 22*5 +#endif +]; +static TCGv cpu_gpr[32]; +#if !defined(TARGET_PPC64) +static TCGv cpu_gprh[32]; +#endif + +/* dyngen register indexes */ +static TCGv cpu_T[3]; +#if defined(TARGET_PPC64) +#define cpu_T64 cpu_T +#else +static TCGv cpu_T64[3]; +#endif #include "gen-icount.h" void ppc_translate_init(void) { + int i; + char* p; static int done_init = 0; + if (done_init) return; + cpu_env = tcg_global_reg_new(TCG_TYPE_PTR, TCG_AREG0, "env"); #if TARGET_LONG_BITS > HOST_LONG_BITS cpu_T[0] = tcg_global_mem_new(TCG_TYPE_TL, @@ -66,6 +88,31 @@ void ppc_translate_init(void) cpu_T[1] = tcg_global_reg_new(TCG_TYPE_TL, TCG_AREG2, "T1"); cpu_T[2] = tcg_global_reg_new(TCG_TYPE_TL, TCG_AREG3, "T2"); #endif +#if !defined(TARGET_PPC64) + cpu_T64[0] = tcg_global_mem_new(TCG_TYPE_I64, + TCG_AREG0, offsetof(CPUState, t0), + "T0_64"); + cpu_T64[1] = tcg_global_mem_new(TCG_TYPE_I64, + TCG_AREG0, offsetof(CPUState, t1), + "T1_64"); + cpu_T64[2] = tcg_global_mem_new(TCG_TYPE_I64, + TCG_AREG0, offsetof(CPUState, t2), + "T2_64"); +#endif + + p = cpu_reg_names; + for (i = 0; i < 32; i++) { + sprintf(p, "r%d", i); + cpu_gpr[i] = tcg_global_mem_new(TCG_TYPE_TL, + TCG_AREG0, offsetof(CPUState, gpr[i]), p); + p += (i < 10) ? 3 : 4; +#if !defined(TARGET_PPC64) + sprintf(p, "r%dH", i); + cpu_gprh[i] = tcg_global_mem_new(TCG_TYPE_I32, + TCG_AREG0, offsetof(CPUState, gprh[i]), p); + p += (i < 10) ? 4 : 5; +#endif + } /* register helpers */ #undef DEF_HELPER <snip> > SPE will be rarely used anyway I guess, so I think it's relatively > "safe" for me to remove the dyngen optimization and simplify > ppc_gpr_t during this transition. What I meant was that the ppc_gpr_t change still lets ppc-softmmu and ppc-linux-user compile, and to my understanding none of these use SPE by default at runtime. I did not want to comment on whether they are fully implemented in QEMU or widely used in external code somewhere. As long as SPE compiles and isn't irrevocably damaged, we're good I think. We'll have to go through and remove the cpu_T stuff later and can optimize SPE with, e.g., local i64 temporaries then. Andreas ^ permalink raw reply related [flat|nested] 42+ messages in thread
* Re: [Qemu-devel] [PATCH 4/x] [ppc] Convert op_moven_T2_T0 to TCG 2008-09-02 16:57 ` [Qemu-devel] [PATCH 4/x] [ppc] Convert op_moven_T2_T0 " Andreas Färber 2008-09-02 22:22 ` [Qemu-devel] [PATCH 5/x] ppc: Convert op_load_gpr_{T0,T1,T2} " Andreas Färber @ 2008-09-02 23:27 ` Aurélien Jarno 1 sibling, 0 replies; 42+ messages in thread From: Aurélien Jarno @ 2008-09-02 23:27 UTC (permalink / raw) To: qemu-devel On Tue, Sep 02, 2008 at 06:57:20PM +0200, Andreas Färber wrote: > Hello, > > Attached patch replaces op_moven_T2_T0 with tcg_gen_not_{tl,i64}. > > Signed-off-by: Andreas Faerber <andreas.faerber@web.de> > > i64 was used for ppc64, so that I assume it is equivalent to tl. No test > setup to check. Applied, thanks. > Andreas > > > diff --git a/target-ppc/op.c b/target-ppc/op.c > index 3ee326d..e663e60 100644 > --- a/target-ppc/op.c > +++ b/target-ppc/op.c > @@ -136,13 +136,6 @@ void OPPROTO op_set_Rc0 (void) > RETURN(); > } > > -/* Constants load */ > -void OPPROTO op_moven_T2_T0 (void) > -{ > - T2 = ~T0; > - RETURN(); > -} > - > /* Generate exceptions */ > void OPPROTO op_raise_exception_err (void) > { > diff --git a/target-ppc/translate.c b/target-ppc/translate.c > index fe1de7e..9068936 100644 > --- a/target-ppc/translate.c > +++ b/target-ppc/translate.c > @@ -914,7 +914,7 @@ GEN_INT_ARITH1_64 (neg, 0x1F, 0x08, 0x03, > PPC_INTEGER); > /* subf subf. subfo subfo. */ > static always_inline void gen_op_subfo (void) > { > - gen_op_moven_T2_T0(); > + tcg_gen_not_tl(cpu_T[2], cpu_T[0]); > gen_op_subf(); > gen_op_check_addo(); > } > @@ -922,7 +922,7 @@ static always_inline void gen_op_subfo (void) > #define gen_op_subf_64 gen_op_subf > static always_inline void gen_op_subfo_64 (void) > { > - gen_op_moven_T2_T0(); > + tcg_gen_not_i64(cpu_T[2], cpu_T[0]); > gen_op_subf(); > gen_op_check_addo_64(); > } > @@ -936,7 +936,7 @@ static always_inline void gen_op_subfc (void) > } > static always_inline void gen_op_subfco (void) > { > - gen_op_moven_T2_T0(); > + tcg_gen_not_tl(cpu_T[2], cpu_T[0]); > gen_op_subf(); > gen_op_check_subfc(); > gen_op_check_addo(); > @@ -949,7 +949,7 @@ static always_inline void gen_op_subfc_64 (void) > } > static always_inline void gen_op_subfco_64 (void) > { > - gen_op_moven_T2_T0(); > + tcg_gen_not_i64(cpu_T[2], cpu_T[0]); > gen_op_subf(); > gen_op_check_subfc_64(); > gen_op_check_addo_64(); > @@ -959,7 +959,7 @@ GEN_INT_ARITH2_64 (subfc, 0x1F, 0x08, 0x00, > PPC_INTEGER); > /* subfe subfe. subfeo subfeo. */ > static always_inline void gen_op_subfeo (void) > { > - gen_op_moven_T2_T0(); > + tcg_gen_not_tl(cpu_T[2], cpu_T[0]); > gen_op_subfe(); > gen_op_check_addo(); > } > @@ -967,7 +967,7 @@ static always_inline void gen_op_subfeo (void) > #define gen_op_subfe_64 gen_op_subfe > static always_inline void gen_op_subfeo_64 (void) > { > - gen_op_moven_T2_T0(); > + tcg_gen_not_i64(cpu_T[2], cpu_T[0]); > gen_op_subfe_64(); > gen_op_check_addo_64(); > } > > > -- .''`. Aurelien Jarno | GPG: 1024D/F1BCDB73 : :' : Debian developer | Electrical Engineer `. `' aurel32@debian.org | aurelien@aurel32.net `- people.debian.org/~aurel32 | www.aurel32.net ^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [Qemu-devel] [PATCH] [ppc] Convert op_reset_T0, op_set_{T0, T1} to TCG 2008-09-02 14:32 ` [Qemu-devel] [PATCH] [ppc] Convert op_reset_T0, op_set_{T0, T1} " Andreas Färber 2008-09-02 15:39 ` [Qemu-devel] [PATCH] [ppc] Convert op_move_{T1,T2}_T0 " Andreas Färber @ 2008-09-02 15:58 ` Aurelien Jarno 2008-09-02 16:44 ` [Qemu-devel] [PATCH 2/x v2] " Andreas Färber 1 sibling, 1 reply; 42+ messages in thread From: Aurelien Jarno @ 2008-09-02 15:58 UTC (permalink / raw) To: qemu-devel; +Cc: Andreas Faerber On Tue, Sep 02, 2008 at 04:32:11PM +0200, Andreas Färber wrote: > Hello, > > The attached patch replaces op_reset_T0, op_set_T0 and op_set_T1 with > tcg_gen_movi_{tl,i32}. Given that cpu_T* are TL registers, the use of tcg_gen_movi_i32() is not correct here. tcg_gen_movi_tl() should use instead. If the value really have to be casted to 32-bit, this as to be done in the argument. > op_set_T0_64 and op_set_T1_64 were apparently unused, and op_set_T2 was > already marked as unused. The patch removes them together with the > converted ops. > > Signed-off-by: Andreas Faerber <andreas.faerber@web.de> > > Andreas > > > diff --git a/target-ppc/op.c b/target-ppc/op.c > index 972b8bc..022d424 100644 > --- a/target-ppc/op.c > +++ b/target-ppc/op.c > @@ -137,48 +137,6 @@ void OPPROTO op_set_Rc0 (void) > } > > /* Constants load */ > -void OPPROTO op_reset_T0 (void) > -{ > - T0 = 0; > - RETURN(); > -} > - > -void OPPROTO op_set_T0 (void) > -{ > - T0 = (uint32_t)PARAM1; > - RETURN(); > -} > - > -#if defined(TARGET_PPC64) > -void OPPROTO op_set_T0_64 (void) > -{ > - T0 = ((uint64_t)PARAM1 << 32) | (uint64_t)PARAM2; > - RETURN(); > -} > -#endif > - > -void OPPROTO op_set_T1 (void) > -{ > - T1 = (uint32_t)PARAM1; > - RETURN(); > -} > - > -#if defined(TARGET_PPC64) > -void OPPROTO op_set_T1_64 (void) > -{ > - T1 = ((uint64_t)PARAM1 << 32) | (uint64_t)PARAM2; > - RETURN(); > -} > -#endif > - > -#if 0 // unused > -void OPPROTO op_set_T2 (void) > -{ > - T2 = (uint32_t)PARAM1; > - RETURN(); > -} > -#endif > - > void OPPROTO op_move_T1_T0 (void) > { > T1 = T0; > diff --git a/target-ppc/translate.c b/target-ppc/translate.c > index 205993a..2c83056 100644 > --- a/target-ppc/translate.c > +++ b/target-ppc/translate.c > @@ -1292,7 +1292,7 @@ GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, > PPC_INTEGER) > gen_op_load_gpr_T1(rB(ctx->opcode)); > gen_op_xor(); > } else { > - gen_op_reset_T0(); > + tcg_gen_movi_tl(cpu_T[0], 0); > } > gen_op_store_T0_gpr(rA(ctx->opcode)); > if (unlikely(Rc(ctx->opcode) != 0)) > @@ -2108,7 +2108,7 @@ static always_inline void gen_addr_reg_index > (DisasContext *ctx) > static always_inline void gen_addr_register (DisasContext *ctx) > { > if (rA(ctx->opcode) == 0) { > - gen_op_reset_T0(); > + tcg_gen_movi_tl(cpu_T[0], 0); > } else { > gen_op_load_gpr_T0(rA(ctx->opcode)); > } > @@ -2518,7 +2518,7 @@ GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, > PPC_STRING) > /* NIP cannot be restored if the memory exception comes from an > helper */ > gen_update_nip(ctx, ctx->nip - 4); > gen_addr_register(ctx); > - gen_op_set_T1(nb); > + tcg_gen_movi_i32(cpu_T[1], nb); > op_ldsts(lswi, start); > } > > @@ -2548,7 +2548,7 @@ GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, > PPC_STRING) > gen_addr_register(ctx); > if (nb == 0) > nb = 32; > - gen_op_set_T1(nb); > + tcg_gen_movi_i32(cpu_T[1], nb); > op_ldsts(stsw, rS(ctx->opcode)); > } > > @@ -3612,7 +3612,7 @@ GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, > PPC_SEGMENT) > GEN_EXCP_PRIVREG(ctx); > return; > } > - gen_op_set_T1(SR(ctx->opcode)); > + tcg_gen_movi_i32(cpu_T[1], SR(ctx->opcode)); > gen_op_load_sr(); > gen_op_store_T0_gpr(rD(ctx->opcode)); > #endif > @@ -3646,7 +3646,7 @@ GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, > PPC_SEGMENT) > return; > } > gen_op_load_gpr_T0(rS(ctx->opcode)); > - gen_op_set_T1(SR(ctx->opcode)); > + tcg_gen_movi_i32(cpu_T[1], SR(ctx->opcode)); > gen_op_store_sr(); > #endif > } > @@ -3680,7 +3680,7 @@ GEN_HANDLER2(mfsr_64b, "mfsr", 0x1F, 0x13, 0x12, > 0x0010F801, PPC_SEGMENT_64B) > GEN_EXCP_PRIVREG(ctx); > return; > } > - gen_op_set_T1(SR(ctx->opcode)); > + tcg_gen_movi_i32(cpu_T[1], SR(ctx->opcode)); > gen_op_load_slb(); > gen_op_store_T0_gpr(rD(ctx->opcode)); > #endif > @@ -3715,7 +3715,7 @@ GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, > 0x0010F801, PPC_SEGMENT_64B) > return; > } > gen_op_load_gpr_T0(rS(ctx->opcode)); > - gen_op_set_T1(SR(ctx->opcode)); > + tcg_gen_movi_i32(cpu_T[1], SR(ctx->opcode)); > gen_op_store_slb(); > #endif > } > @@ -3952,7 +3952,7 @@ GEN_HANDLER(dozo, 0x1F, 0x08, 0x18, 0x00000000, > PPC_POWER_BR) > GEN_HANDLER(dozi, 0x09, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR) > { > gen_op_load_gpr_T0(rA(ctx->opcode)); > - gen_op_set_T1(SIMM(ctx->opcode)); > + tcg_gen_movi_i32(cpu_T[1], SIMM(ctx->opcode)); > gen_op_POWER_doz(); > gen_op_store_T0_gpr(rD(ctx->opcode)); > } > @@ -4117,7 +4117,7 @@ GEN_HANDLER(sleq, 0x1F, 0x19, 0x06, 0x00000000, > PPC_POWER_BR) > GEN_HANDLER(sliq, 0x1F, 0x18, 0x05, 0x00000000, PPC_POWER_BR) > { > gen_op_load_gpr_T0(rS(ctx->opcode)); > - gen_op_set_T1(SH(ctx->opcode)); > + tcg_gen_movi_i32(cpu_T[1], SH(ctx->opcode)); > gen_op_POWER_sle(); > gen_op_store_T0_gpr(rA(ctx->opcode)); > if (unlikely(Rc(ctx->opcode) != 0)) > @@ -4128,7 +4128,7 @@ GEN_HANDLER(sliq, 0x1F, 0x18, 0x05, 0x00000000, > PPC_POWER_BR) > GEN_HANDLER(slliq, 0x1F, 0x18, 0x07, 0x00000000, PPC_POWER_BR) > { > gen_op_load_gpr_T0(rS(ctx->opcode)); > - gen_op_set_T1(SH(ctx->opcode)); > + tcg_gen_movi_i32(cpu_T[1], SH(ctx->opcode)); > gen_op_POWER_sleq(); > gen_op_store_T0_gpr(rA(ctx->opcode)); > if (unlikely(Rc(ctx->opcode) != 0)) > @@ -4161,7 +4161,7 @@ GEN_HANDLER(slq, 0x1F, 0x18, 0x04, 0x00000000, > PPC_POWER_BR) > GEN_HANDLER(sraiq, 0x1F, 0x18, 0x1D, 0x00000000, PPC_POWER_BR) > { > gen_op_load_gpr_T0(rS(ctx->opcode)); > - gen_op_set_T1(SH(ctx->opcode)); > + tcg_gen_movi_i32(cpu_T[1], SH(ctx->opcode)); > gen_op_POWER_sraq(); > gen_op_store_T0_gpr(rA(ctx->opcode)); > if (unlikely(Rc(ctx->opcode) != 0)) > @@ -4216,7 +4216,7 @@ GEN_HANDLER(sreq, 0x1F, 0x19, 0x16, 0x00000000, > PPC_POWER_BR) > GEN_HANDLER(sriq, 0x1F, 0x18, 0x15, 0x00000000, PPC_POWER_BR) > { > gen_op_load_gpr_T0(rS(ctx->opcode)); > - gen_op_set_T1(SH(ctx->opcode)); > + tcg_gen_movi_i32(cpu_T[1], SH(ctx->opcode)); > gen_op_POWER_srq(); > gen_op_store_T0_gpr(rA(ctx->opcode)); > if (unlikely(Rc(ctx->opcode) != 0)) > @@ -4228,7 +4228,7 @@ GEN_HANDLER(srliq, 0x1F, 0x18, 0x17, 0x00000000, > PPC_POWER_BR) > { > gen_op_load_gpr_T0(rS(ctx->opcode)); > gen_op_load_gpr_T1(rB(ctx->opcode)); > - gen_op_set_T1(SH(ctx->opcode)); > + tcg_gen_movi_i32(cpu_T[1], SH(ctx->opcode)); > gen_op_POWER_srlq(); > gen_op_store_T0_gpr(rA(ctx->opcode)); > if (unlikely(Rc(ctx->opcode) != 0)) > @@ -4776,7 +4776,7 @@ GEN_HANDLER(mfdcr, 0x1F, 0x03, 0x0A, 0x00000001, > PPC_DCR) > GEN_EXCP_PRIVREG(ctx); > return; > } > - gen_op_set_T0(dcrn); > + tcg_gen_movi_i32(cpu_T[0], dcrn); > gen_op_load_dcr(); > gen_op_store_T0_gpr(rD(ctx->opcode)); > #endif > @@ -4794,7 +4794,7 @@ GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, > PPC_DCR) > GEN_EXCP_PRIVREG(ctx); > return; > } > - gen_op_set_T0(dcrn); > + tcg_gen_movi_i32(cpu_T[0], dcrn); > gen_op_load_gpr_T1(rS(ctx->opcode)); > gen_op_store_dcr(); > #endif > @@ -5158,7 +5158,7 @@ GEN_HANDLER(wrteei, 0x1F, 0x03, 0x05, 0x000EFC01, > PPC_WRTEE) > GEN_EXCP_PRIVOPC(ctx); > return; > } > - gen_op_set_T0(ctx->opcode & 0x00010000); > + tcg_gen_movi_i32(cpu_T[0], ctx->opcode & 0x00010000); > gen_op_wrte(); > /* Stop translation to have a chance to raise an exception > * if we just set msr_ee to 1 > > > -- .''`. Aurelien Jarno | GPG: 1024D/F1BCDB73 : :' : Debian developer | Electrical Engineer `. `' aurel32@debian.org | aurelien@aurel32.net `- people.debian.org/~aurel32 | www.aurel32.net ^ permalink raw reply [flat|nested] 42+ messages in thread
* [Qemu-devel] [PATCH 2/x v2] [ppc] Convert op_reset_T0, op_set_{T0, T1} to TCG 2008-09-02 15:58 ` [Qemu-devel] [PATCH] [ppc] Convert op_reset_T0, op_set_{T0, T1} " Aurelien Jarno @ 2008-09-02 16:44 ` Andreas Färber 2008-09-02 23:28 ` Aurélien Jarno 0 siblings, 1 reply; 42+ messages in thread From: Andreas Färber @ 2008-09-02 16:44 UTC (permalink / raw) To: qemu-devel, Aurélien Jarno [-- Attachment #1: Type: text/plain, Size: 592 bytes --] Am 02.09.2008 um 17:58 schrieb Aurelien Jarno: > On Tue, Sep 02, 2008 at 04:32:11PM +0200, Andreas Färber wrote: >> Hello, >> >> The attached patch replaces op_reset_T0, op_set_T0 and op_set_T1 with >> tcg_gen_movi_{tl,i32}. > > Given that cpu_T* are TL registers, the use of tcg_gen_movi_i32() is > not > correct here. tcg_gen_movi_tl() should use instead. If the value > really > have to be casted to 32-bit, this as to be done in the argument. Done. (There appeared to be no need for casting.) Signed-off-by: Andreas Faerber <andreas.faerber@web.de> Andreas [-- Attachment #2: op_reset-set-v2.diff --] [-- Type: application/octet-stream, Size: 6612 bytes --] diff --git a/target-ppc/op.c b/target-ppc/op.c index 972b8bc..022d424 100644 --- a/target-ppc/op.c +++ b/target-ppc/op.c @@ -137,48 +137,6 @@ void OPPROTO op_set_Rc0 (void) } /* Constants load */ -void OPPROTO op_reset_T0 (void) -{ - T0 = 0; - RETURN(); -} - -void OPPROTO op_set_T0 (void) -{ - T0 = (uint32_t)PARAM1; - RETURN(); -} - -#if defined(TARGET_PPC64) -void OPPROTO op_set_T0_64 (void) -{ - T0 = ((uint64_t)PARAM1 << 32) | (uint64_t)PARAM2; - RETURN(); -} -#endif - -void OPPROTO op_set_T1 (void) -{ - T1 = (uint32_t)PARAM1; - RETURN(); -} - -#if defined(TARGET_PPC64) -void OPPROTO op_set_T1_64 (void) -{ - T1 = ((uint64_t)PARAM1 << 32) | (uint64_t)PARAM2; - RETURN(); -} -#endif - -#if 0 // unused -void OPPROTO op_set_T2 (void) -{ - T2 = (uint32_t)PARAM1; - RETURN(); -} -#endif - void OPPROTO op_move_T1_T0 (void) { T1 = T0; diff --git a/target-ppc/translate.c b/target-ppc/translate.c index 205993a..3f6abc7 100644 --- a/target-ppc/translate.c +++ b/target-ppc/translate.c @@ -1292,7 +1292,7 @@ GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER) gen_op_load_gpr_T1(rB(ctx->opcode)); gen_op_xor(); } else { - gen_op_reset_T0(); + tcg_gen_movi_tl(cpu_T[0], 0); } gen_op_store_T0_gpr(rA(ctx->opcode)); if (unlikely(Rc(ctx->opcode) != 0)) @@ -2108,7 +2108,7 @@ static always_inline void gen_addr_reg_index (DisasContext *ctx) static always_inline void gen_addr_register (DisasContext *ctx) { if (rA(ctx->opcode) == 0) { - gen_op_reset_T0(); + tcg_gen_movi_tl(cpu_T[0], 0); } else { gen_op_load_gpr_T0(rA(ctx->opcode)); } @@ -2518,7 +2518,7 @@ GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING) /* NIP cannot be restored if the memory exception comes from an helper */ gen_update_nip(ctx, ctx->nip - 4); gen_addr_register(ctx); - gen_op_set_T1(nb); + tcg_gen_movi_tl(cpu_T[1], nb); op_ldsts(lswi, start); } @@ -2548,7 +2548,7 @@ GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING) gen_addr_register(ctx); if (nb == 0) nb = 32; - gen_op_set_T1(nb); + tcg_gen_movi_tl(cpu_T[1], nb); op_ldsts(stsw, rS(ctx->opcode)); } @@ -3612,7 +3612,7 @@ GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT) GEN_EXCP_PRIVREG(ctx); return; } - gen_op_set_T1(SR(ctx->opcode)); + tcg_gen_movi_tl(cpu_T[1], SR(ctx->opcode)); gen_op_load_sr(); gen_op_store_T0_gpr(rD(ctx->opcode)); #endif @@ -3646,7 +3646,7 @@ GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT) return; } gen_op_load_gpr_T0(rS(ctx->opcode)); - gen_op_set_T1(SR(ctx->opcode)); + tcg_gen_movi_tl(cpu_T[1], SR(ctx->opcode)); gen_op_store_sr(); #endif } @@ -3680,7 +3680,7 @@ GEN_HANDLER2(mfsr_64b, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B) GEN_EXCP_PRIVREG(ctx); return; } - gen_op_set_T1(SR(ctx->opcode)); + tcg_gen_movi_tl(cpu_T[1], SR(ctx->opcode)); gen_op_load_slb(); gen_op_store_T0_gpr(rD(ctx->opcode)); #endif @@ -3715,7 +3715,7 @@ GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B) return; } gen_op_load_gpr_T0(rS(ctx->opcode)); - gen_op_set_T1(SR(ctx->opcode)); + tcg_gen_movi_tl(cpu_T[1], SR(ctx->opcode)); gen_op_store_slb(); #endif } @@ -3952,7 +3952,7 @@ GEN_HANDLER(dozo, 0x1F, 0x08, 0x18, 0x00000000, PPC_POWER_BR) GEN_HANDLER(dozi, 0x09, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR) { gen_op_load_gpr_T0(rA(ctx->opcode)); - gen_op_set_T1(SIMM(ctx->opcode)); + tcg_gen_movi_tl(cpu_T[1], SIMM(ctx->opcode)); gen_op_POWER_doz(); gen_op_store_T0_gpr(rD(ctx->opcode)); } @@ -4117,7 +4117,7 @@ GEN_HANDLER(sleq, 0x1F, 0x19, 0x06, 0x00000000, PPC_POWER_BR) GEN_HANDLER(sliq, 0x1F, 0x18, 0x05, 0x00000000, PPC_POWER_BR) { gen_op_load_gpr_T0(rS(ctx->opcode)); - gen_op_set_T1(SH(ctx->opcode)); + tcg_gen_movi_tl(cpu_T[1], SH(ctx->opcode)); gen_op_POWER_sle(); gen_op_store_T0_gpr(rA(ctx->opcode)); if (unlikely(Rc(ctx->opcode) != 0)) @@ -4128,7 +4128,7 @@ GEN_HANDLER(sliq, 0x1F, 0x18, 0x05, 0x00000000, PPC_POWER_BR) GEN_HANDLER(slliq, 0x1F, 0x18, 0x07, 0x00000000, PPC_POWER_BR) { gen_op_load_gpr_T0(rS(ctx->opcode)); - gen_op_set_T1(SH(ctx->opcode)); + tcg_gen_movi_tl(cpu_T[1], SH(ctx->opcode)); gen_op_POWER_sleq(); gen_op_store_T0_gpr(rA(ctx->opcode)); if (unlikely(Rc(ctx->opcode) != 0)) @@ -4161,7 +4161,7 @@ GEN_HANDLER(slq, 0x1F, 0x18, 0x04, 0x00000000, PPC_POWER_BR) GEN_HANDLER(sraiq, 0x1F, 0x18, 0x1D, 0x00000000, PPC_POWER_BR) { gen_op_load_gpr_T0(rS(ctx->opcode)); - gen_op_set_T1(SH(ctx->opcode)); + tcg_gen_movi_tl(cpu_T[1], SH(ctx->opcode)); gen_op_POWER_sraq(); gen_op_store_T0_gpr(rA(ctx->opcode)); if (unlikely(Rc(ctx->opcode) != 0)) @@ -4216,7 +4216,7 @@ GEN_HANDLER(sreq, 0x1F, 0x19, 0x16, 0x00000000, PPC_POWER_BR) GEN_HANDLER(sriq, 0x1F, 0x18, 0x15, 0x00000000, PPC_POWER_BR) { gen_op_load_gpr_T0(rS(ctx->opcode)); - gen_op_set_T1(SH(ctx->opcode)); + tcg_gen_movi_tl(cpu_T[1], SH(ctx->opcode)); gen_op_POWER_srq(); gen_op_store_T0_gpr(rA(ctx->opcode)); if (unlikely(Rc(ctx->opcode) != 0)) @@ -4228,7 +4228,7 @@ GEN_HANDLER(srliq, 0x1F, 0x18, 0x17, 0x00000000, PPC_POWER_BR) { gen_op_load_gpr_T0(rS(ctx->opcode)); gen_op_load_gpr_T1(rB(ctx->opcode)); - gen_op_set_T1(SH(ctx->opcode)); + tcg_gen_movi_tl(cpu_T[1], SH(ctx->opcode)); gen_op_POWER_srlq(); gen_op_store_T0_gpr(rA(ctx->opcode)); if (unlikely(Rc(ctx->opcode) != 0)) @@ -4776,7 +4776,7 @@ GEN_HANDLER(mfdcr, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR) GEN_EXCP_PRIVREG(ctx); return; } - gen_op_set_T0(dcrn); + tcg_gen_movi_tl(cpu_T[0], dcrn); gen_op_load_dcr(); gen_op_store_T0_gpr(rD(ctx->opcode)); #endif @@ -4794,7 +4794,7 @@ GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR) GEN_EXCP_PRIVREG(ctx); return; } - gen_op_set_T0(dcrn); + tcg_gen_movi_tl(cpu_T[0], dcrn); gen_op_load_gpr_T1(rS(ctx->opcode)); gen_op_store_dcr(); #endif @@ -5158,7 +5158,7 @@ GEN_HANDLER(wrteei, 0x1F, 0x03, 0x05, 0x000EFC01, PPC_WRTEE) GEN_EXCP_PRIVOPC(ctx); return; } - gen_op_set_T0(ctx->opcode & 0x00010000); + tcg_gen_movi_tl(cpu_T[0], ctx->opcode & 0x00010000); gen_op_wrte(); /* Stop translation to have a chance to raise an exception * if we just set msr_ee to 1 [-- Attachment #3: Type: text/plain, Size: 1 bytes --] ^ permalink raw reply related [flat|nested] 42+ messages in thread
* Re: [Qemu-devel] [PATCH 2/x v2] [ppc] Convert op_reset_T0, op_set_{T0, T1} to TCG 2008-09-02 16:44 ` [Qemu-devel] [PATCH 2/x v2] " Andreas Färber @ 2008-09-02 23:28 ` Aurélien Jarno 0 siblings, 0 replies; 42+ messages in thread From: Aurélien Jarno @ 2008-09-02 23:28 UTC (permalink / raw) To: qemu-devel On Tue, Sep 02, 2008 at 06:44:59PM +0200, Andreas Färber wrote: > > Am 02.09.2008 um 17:58 schrieb Aurelien Jarno: > >> On Tue, Sep 02, 2008 at 04:32:11PM +0200, Andreas Färber wrote: >>> Hello, >>> >>> The attached patch replaces op_reset_T0, op_set_T0 and op_set_T1 with >>> tcg_gen_movi_{tl,i32}. >> >> Given that cpu_T* are TL registers, the use of tcg_gen_movi_i32() is >> not >> correct here. tcg_gen_movi_tl() should use instead. If the value >> really >> have to be casted to 32-bit, this as to be done in the argument. > > Done. (There appeared to be no need for casting.) Applied, thanks. > > Signed-off-by: Andreas Faerber <andreas.faerber@web.de> > > Andreas > > -- .''`. Aurelien Jarno | GPG: 1024D/F1BCDB73 : :' : Debian developer | Electrical Engineer `. `' aurel32@debian.org | aurelien@aurel32.net `- people.debian.org/~aurel32 | www.aurel32.net ^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [Qemu-devel] [PATCH] [ppc] Convert gen_set_{T0,T1} to TCG 2008-09-02 13:36 [Qemu-devel] [PATCH] [ppc] Convert gen_set_{T0,T1} to TCG Andreas Färber 2008-09-02 14:32 ` [Qemu-devel] [PATCH] [ppc] Convert op_reset_T0, op_set_{T0, T1} " Andreas Färber @ 2008-09-02 16:18 ` Aurelien Jarno 1 sibling, 0 replies; 42+ messages in thread From: Aurelien Jarno @ 2008-09-02 16:18 UTC (permalink / raw) To: qemu-devel On Tue, Sep 02, 2008 at 03:36:17PM +0200, Andreas Färber wrote: > Hello, > > The attached patch replaces gen_set_T0 and gen_set_T1 with > tcg_gen_movi_tl. > > Signed-off-by: Andreas Faerber <andreas.faerber@web.de> > > It compiles, boots Rob's PReP kernel and runs linux-user-test-0.3's ls, > on Linux/amd64. Any further instructions to test? Applied, thanks. > Andreas > > diff --git a/target-ppc/translate.c b/target-ppc/translate.c > index bde538a..205993a 100644 > --- a/target-ppc/translate.c > +++ b/target-ppc/translate.c > @@ -80,26 +80,6 @@ static uint16_t *gen_fprf_buf[OPC_BUF_SIZE]; > static uint16_t **gen_fprf_ptr; > #endif > > -static always_inline void gen_set_T0 (target_ulong val) > -{ > -#if defined(TARGET_PPC64) > - if (val >> 32) > - gen_op_set_T0_64(val >> 32, val); > - else > -#endif > - gen_op_set_T0(val); > -} > - > -static always_inline void gen_set_T1 (target_ulong val) > -{ > -#if defined(TARGET_PPC64) > - if (val >> 32) > - gen_op_set_T1_64(val >> 32, val); > - else > -#endif > - gen_op_set_T1(val); > -} > - > #define GEN8(func, NAME) > \ > static GenOpFunc *NAME ## _table [8] = { > \ > NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3, > \ > @@ -1004,7 +984,7 @@ GEN_HANDLER(addi, 0x0E, 0xFF, 0xFF, 0x00000000, > PPC_INTEGER) > > if (rA(ctx->opcode) == 0) { > /* li case */ > - gen_set_T0(simm); > + tcg_gen_movi_tl(cpu_T[0], simm); > } else { > gen_op_load_gpr_T0(rA(ctx->opcode)); > if (likely(simm != 0)) > @@ -1060,7 +1040,7 @@ GEN_HANDLER(addis, 0x0F, 0xFF, 0xFF, 0x00000000, > PPC_INTEGER) > > if (rA(ctx->opcode) == 0) { > /* lis case */ > - gen_set_T0(simm << 16); > + tcg_gen_movi_tl(cpu_T[0], simm << 16); > } else { > gen_op_load_gpr_T0(rA(ctx->opcode)); > if (likely(simm != 0)) > @@ -1161,7 +1141,7 @@ GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, > PPC_ISEL) > uint32_t mask; > > if (rA(ctx->opcode) == 0) { > - gen_set_T0(0); > + tcg_gen_movi_tl(cpu_T[0], 0); > } else { > gen_op_load_gpr_T1(rA(ctx->opcode)); > } > @@ -2100,7 +2080,7 @@ static always_inline void gen_addr_imm_index > (DisasContext *ctx, > > simm &= ~maskl; > if (rA(ctx->opcode) == 0) { > - gen_set_T0(simm); > + tcg_gen_movi_tl(cpu_T[0], simm); > } else { > gen_op_load_gpr_T0(rA(ctx->opcode)); > if (likely(simm != 0)) > @@ -2823,7 +2803,7 @@ static always_inline void gen_goto_tb > (DisasContext *ctx, int n, > if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK) && > likely(!ctx->singlestep_enabled)) { > tcg_gen_goto_tb(n); > - gen_set_T1(dest); > + tcg_gen_movi_tl(cpu_T[1], dest); > #if defined(TARGET_PPC64) > if (ctx->sf_mode) > gen_op_b_T1_64(); > @@ -2832,7 +2812,7 @@ static always_inline void gen_goto_tb > (DisasContext *ctx, int n, > gen_op_b_T1(); > tcg_gen_exit_tb((long)tb + n); > } else { > - gen_set_T1(dest); > + tcg_gen_movi_tl(cpu_T[1], dest); > #if defined(TARGET_PPC64) > if (ctx->sf_mode) > gen_op_b_T1_64(); > @@ -3185,7 +3165,7 @@ GEN_HANDLER(tw, 0x1F, 0x04, 0x00, 0x00000001, > PPC_FLOW) > GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW) > { > gen_op_load_gpr_T0(rA(ctx->opcode)); > - gen_set_T1(SIMM(ctx->opcode)); > + tcg_gen_movi_tl(cpu_T[1], SIMM(ctx->opcode)); > /* Update the nip since this might generate a trap exception */ > gen_update_nip(ctx, ctx->nip); > gen_op_tw(TO(ctx->opcode)); > @@ -3206,7 +3186,7 @@ GEN_HANDLER(td, 0x1F, 0x04, 0x02, 0x00000001, > PPC_64B) > GEN_HANDLER(tdi, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B) > { > gen_op_load_gpr_T0(rA(ctx->opcode)); > - gen_set_T1(SIMM(ctx->opcode)); > + tcg_gen_movi_tl(cpu_T[1], SIMM(ctx->opcode)); > /* Update the nip since this might generate a trap exception */ > gen_update_nip(ctx, ctx->nip); > gen_op_td(TO(ctx->opcode)); > @@ -5335,7 +5315,7 @@ static always_inline void gen_addr_spe_imm_index > (DisasContext *ctx, int sh) > target_long simm = rB(ctx->opcode); > > if (rA(ctx->opcode) == 0) { > - gen_set_T0(simm << sh); > + tcg_gen_movi_tl(cpu_T[0], simm << sh); > } else { > gen_op_load_gpr_T0(rA(ctx->opcode)); > if (likely(simm != 0)) > > > -- .''`. Aurelien Jarno | GPG: 1024D/F1BCDB73 : :' : Debian developer | Electrical Engineer `. `' aurel32@debian.org | aurelien@aurel32.net `- people.debian.org/~aurel32 | www.aurel32.net ^ permalink raw reply [flat|nested] 42+ messages in thread
end of thread, other threads:[~2008-09-07 14:22 UTC | newest]
Thread overview: 42+ messages (download: mbox.gz follow: Atom feed
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2008-09-02 13:36 [Qemu-devel] [PATCH] [ppc] Convert gen_set_{T0,T1} to TCG Andreas Färber
2008-09-02 14:32 ` [Qemu-devel] [PATCH] [ppc] Convert op_reset_T0, op_set_{T0, T1} " Andreas Färber
2008-09-02 15:39 ` [Qemu-devel] [PATCH] [ppc] Convert op_move_{T1,T2}_T0 " Andreas Färber
2008-09-02 16:19 ` Aurelien Jarno
2008-09-02 16:57 ` [Qemu-devel] [PATCH 4/x] [ppc] Convert op_moven_T2_T0 " Andreas Färber
2008-09-02 22:22 ` [Qemu-devel] [PATCH 5/x] ppc: Convert op_load_gpr_{T0,T1,T2} " Andreas Färber
2008-09-02 23:20 ` Aurelien Jarno
2008-09-03 0:39 ` [Qemu-devel] [PATCH 5/x] ppc: Convert op_load_gpr_{T0, T1, T2} " Andreas Färber
2008-09-03 5:07 ` Aurelien Jarno
2008-09-03 10:41 ` Andreas Färber
2008-09-03 11:28 ` Thiemo Seufer
2008-09-03 18:07 ` Andreas Färber
2008-09-03 18:26 ` Blue Swirl
2008-09-03 19:00 ` Andreas Färber
2008-09-03 19:12 ` Blue Swirl
2008-09-03 20:04 ` [Qemu-devel] [PATCH 5/x v2] ppc: Convert GPR moves " Andreas Färber
2008-09-04 5:25 ` Aurelien Jarno
2008-09-04 10:21 ` Andreas Färber
2008-09-04 12:24 ` [Qemu-devel] [PATCH 6/x] ppc: Convert Altivec register " Andreas Färber
2008-09-04 14:08 ` [Qemu-devel] [PATCH 7/x] ppc: Convert FPR " Andreas Färber
2008-09-04 14:39 ` Aurélien Jarno
2008-09-04 17:59 ` [Qemu-devel] [PATCH 8/x] ppc: Convert op_set_FT0 " Andreas Färber
2008-09-04 20:36 ` Aurélien Jarno
2008-09-04 22:53 ` [Qemu-devel] [PATCH 9/x] ppc: Convert op_add, op_addi " Andreas Färber
2008-09-05 14:18 ` Aurélien Jarno
2008-09-05 17:17 ` Andreas Färber
2008-09-05 17:49 ` Aurelien Jarno
2008-09-04 23:46 ` [Qemu-devel] [PATCH 10/x] ppc: Convert op_subf " Andreas Färber
2008-09-05 14:18 ` Aurélien Jarno
2008-09-04 14:39 ` [Qemu-devel] [PATCH 6/x] ppc: Convert Altivec register moves " Aurélien Jarno
2008-09-07 14:22 ` [Qemu-devel] [PATCH 5/x] ppc: Convert op_load_gpr_{T0, T1, T2} " Paul Brook
2008-09-03 12:41 ` Aurélien Jarno
2008-09-03 12:58 ` Andreas Färber
2008-09-03 13:00 ` Aurélien Jarno
2008-09-03 13:23 ` Thiemo Seufer
2008-09-03 13:45 ` Tristan Gingold
2008-09-03 16:04 ` Andreas Färber
2008-09-02 23:27 ` [Qemu-devel] [PATCH 4/x] [ppc] Convert op_moven_T2_T0 " Aurélien Jarno
2008-09-02 15:58 ` [Qemu-devel] [PATCH] [ppc] Convert op_reset_T0, op_set_{T0, T1} " Aurelien Jarno
2008-09-02 16:44 ` [Qemu-devel] [PATCH 2/x v2] " Andreas Färber
2008-09-02 23:28 ` Aurélien Jarno
2008-09-02 16:18 ` [Qemu-devel] [PATCH] [ppc] Convert gen_set_{T0,T1} " Aurelien Jarno
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