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Date: Wed, 3 Sep 2008 13:37:44 +0200
From: Thiemo Seufer <ths@networkno.de>
Subject: Re: [Qemu-devel] TCG: 64-bit temporaries on 32-bit target?
Message-ID: <20080903113744.GD17474@networkno.de>
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To: Andreas =?iso-8859-1?Q?F=E4rber?= <andreas.faerber@web.de>
Cc: qemu-devel@nongnu.org

Andreas F=E4rber wrote:
> Hello,
>
> On PowerPC there appear to be some "SPE" instructions that operate on =20
> 64-bit registers while the rest of the target is 32-bit. In dyngen code,=
=20
> they can easily use T0_64 then.
>
> In TCG however, cpu_T[0] is tl=3D=3Di32 for ppc, only for ppc64 would =20
> cpu_T[0] work due to tl=3D=3Di64. At the same time I was told I can't use=
 =20
> tcg_gen_movi_i32 for tl cpu_T[n], so it seems we can't just =20
> unconditionally use i64 for cpu_T[0..2] either?
>
> This issue prevents dyngen op_load_gpr_{T0,T1} from being removed =20
> because ppc64 gen_op_load_gpr64_{T0,T1} reuses them.
>
> Any suggestions appreciated!

A similiar problem exists for MIPS32 with 64-bit FPU, I introduced
e.g T64_0 and T64_1 and added explicit conversions to 32-bit registers/
register pairs where necessary.


Thiemo