[Qemu-devel] TCG: 64-bit temporaries on 32-bit target?

[Qemu-devel] TCG: 64-bit temporaries on 32-bit target?

[Andreas Färber]

Hello,

On PowerPC there appear to be some "SPE" instructions that operate on  
64-bit registers while the rest of the target is 32-bit. In dyngen  
code, they can easily use T0_64 then.

In TCG however, cpu_T[0] is tl==i32 for ppc, only for ppc64 would  
cpu_T[0] work due to tl==i64. At the same time I was told I can't use  
tcg_gen_movi_i32 for tl cpu_T[n], so it seems we can't just  
unconditionally use i64 for cpu_T[0..2] either?

This issue prevents dyngen op_load_gpr_{T0,T1} from being removed  
because ppc64 gen_op_load_gpr64_{T0,T1} reuses them.

Any suggestions appreciated!

Andreas

Re: [Qemu-devel] TCG: 64-bit temporaries on 32-bit target?

[Aurelien Jarno]

On Wed, Sep 03, 2008 at 02:00:38AM +0200, Andreas Färber wrote:
> Hello,
>
> On PowerPC there appear to be some "SPE" instructions that operate on  
> 64-bit registers while the rest of the target is 32-bit. In dyngen code, 
> they can easily use T0_64 then.
>
> In TCG however, cpu_T[0] is tl==i32 for ppc, only for ppc64 would  
> cpu_T[0] work due to tl==i64. At the same time I was told I can't use  
> tcg_gen_movi_i32 for tl cpu_T[n], so it seems we can't just  
> unconditionally use i64 for cpu_T[0..2] either?

That solution would be a performance regression anyway.

> This issue prevents dyngen op_load_gpr_{T0,T1} from being removed  
> because ppc64 gen_op_load_gpr64_{T0,T1} reuses them.
>

The same solution than dyngen should work, that is defining cpu_T64[0]
and cpu_T64[1], either as i64 on the 32-bit target, or are an alias
(#define) of cpu_T[0] and cpu_T[1] on the 64-bit target.

Then you can use _i64 TCG instructions.

Always defining cpu_T64[0] and cpu_T64_[1] as i64 and independantly than
cpu_T[0] and cpu_T[1] should also work, as anyway those variables 
should disappear when optimising the TCG code.

-- 
  .''`.  Aurelien Jarno	            | GPG: 1024D/F1BCDB73
 : :' :  Debian developer           | Electrical Engineer
 `. `'   aurel32@debian.org         | aurelien@aurel32.net
   `-    people.debian.org/~aurel32 | www.aurel32.net

Re: [Qemu-devel] TCG: 64-bit temporaries on 32-bit target?

[Thiemo Seufer]

Andreas Färber wrote:
> Hello,
>
> On PowerPC there appear to be some "SPE" instructions that operate on  
> 64-bit registers while the rest of the target is 32-bit. In dyngen code, 
> they can easily use T0_64 then.
>
> In TCG however, cpu_T[0] is tl==i32 for ppc, only for ppc64 would  
> cpu_T[0] work due to tl==i64. At the same time I was told I can't use  
> tcg_gen_movi_i32 for tl cpu_T[n], so it seems we can't just  
> unconditionally use i64 for cpu_T[0..2] either?
>
> This issue prevents dyngen op_load_gpr_{T0,T1} from being removed  
> because ppc64 gen_op_load_gpr64_{T0,T1} reuses them.
>
> Any suggestions appreciated!

A similiar problem exists for MIPS32 with 64-bit FPU, I introduced
e.g T64_0 and T64_1 and added explicit conversions to 32-bit registers/
register pairs where necessary.


Thiemo