From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1Kar5L-0000Ki-TN for qemu-devel@nongnu.org; Wed, 03 Sep 2008 08:03:43 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1Kar5K-0000Jx-PY for qemu-devel@nongnu.org; Wed, 03 Sep 2008 08:03:43 -0400 Received: from [199.232.76.173] (port=49309 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1Kar5K-0000Jc-J8 for qemu-devel@nongnu.org; Wed, 03 Sep 2008 08:03:42 -0400 Received: from ns6.enix.org ([193.19.211.1]:33429 helo=the-doors.enix.org) by monty-python.gnu.org with esmtp (Exim 4.60) (envelope-from ) id 1Kar5K-00070v-N4 for qemu-devel@nongnu.org; Wed, 03 Sep 2008 08:03:42 -0400 Date: Wed, 3 Sep 2008 14:03:37 +0200 From: Thomas Petazzoni Subject: Re: [Qemu-devel] MIPS kernel hanging when loaded through U-Boot in qemu Message-ID: <20080903140337.78afd030@surf> In-Reply-To: <20080903105447.GA17474@networkno.de> References: <20080828110042.1d27e8bb@surf> <20080903092511.4918f2d6@surf> <20080903105447.GA17474@networkno.de> Mime-Version: 1.0 Content-Type: multipart/signed; boundary="Sig_/2FKrx50kXTTK_Byjm+dDXwL"; protocol="application/pgp-signature"; micalg=PGP-SHA1 Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Thiemo Seufer Cc: qemu-devel@nongnu.org --Sig_/2FKrx50kXTTK_Byjm+dDXwL Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Le Wed, 3 Sep 2008 12:54:47 +0200, Thiemo Seufer a =C3=A9crit : > 'Interrupt' at this point should be the normal timer interrupt, > "syscall" are the execve() calls which start kernel threads. On > classic mips, both types of exceptions use the general exception > vector at 0x80000180. What's strange about these "syscall" interrupts is that we don't see them in the kernel-only boot (http://toulibre.org/~thomas/qemu/qemu-interrupt-log-kernel-only). Are you sure that the syscall interrupt is used to run do_fork() inside the kernel ? I'm not so sure. > The difference here is that the timer interrupt goes to 0x80000200, > this is controlled by the IV bit in the Cause register. This feature > isn't available on all CPUs. In the kernel the relevant check to test > for it is cpu_has_divec. I figure U-Boot and the Kernel disagree > on the setting. Hehe, it seems that you're correct. In U-Boot board/qemu-mips/lowlevel_init.S, we have: /* * Step 7) Establish Cause * (set IV bit) */ li t1, 0x00800000 mtc0 t1, CP0_CAUSE In the kernel include/asm-mips/mach-qemu/cpu-feature-overrides.h, we have: #define cpu_has_divec 0 > Qemu always allows to set this Cause bit, independent of the CPU type. > So I figure we have two bugs: > - The kernel should try to clear the IV bit if it doesn't intend to > use it > - Qemu should ignore attempts to set the IV bit when emulating CPUs > without divec. Probably :-) Thomas --=20 Thomas Petazzoni, thomas.petazzoni@enix.org, http://thomas.enix.org Jabber, thomas.petazzoni@jabber.dk Toulibre, http://www.toulibre.org - APRIL, http://www.april.org Fingerprint : 0BE1 4CF3 CEA4 AC9D CC6E 1624 F653 CB30 98D3 F7A7 --Sig_/2FKrx50kXTTK_Byjm+dDXwL Content-Type: application/pgp-signature; name=signature.asc Content-Disposition: attachment; filename=signature.asc -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.6 (GNU/Linux) iD8DBQFIvn0c9lPLMJjT96cRAh1sAJ9iEsr1LfXqtMdaEdRneBCBe6Z6QgCeJvw7 S4HbdiszWZIjpglz+q3miTg= =6kbs -----END PGP SIGNATURE----- --Sig_/2FKrx50kXTTK_Byjm+dDXwL--