* [Qemu-devel] [PATCH 1/2] ppc: Convert ctr, lr moves to TCG
@ 2008-09-14 11:06 Andreas Färber
2008-09-14 11:23 ` [Qemu-devel] [PATCH 2/2] ppc: Convert op_andi " Andreas Färber
2008-09-14 18:30 ` [Qemu-devel] [PATCH 1/2] ppc: Convert ctr, lr moves " Aurelien Jarno
0 siblings, 2 replies; 10+ messages in thread
From: Andreas Färber @ 2008-09-14 11:06 UTC (permalink / raw)
To: qemu-devel
[-- Attachment #1: Type: text/plain, Size: 2797 bytes --]
Introduce TCG variables cpu_{ctr,lr} and replace
op_{load,store}_{lr,ctr} with tcg_gen_mov_tl.
Signed-off-by: Andreas Faerber <andreas.faerber@web.de>
---
Hello,
A quick inbox search for ppc did not reveal new patches, so I hope
these two still apply.
Andreas
target-ppc/op.c | 24 ------------------------
target-ppc/translate.c | 8 ++++++++
target-ppc/translate_init.c | 8 ++++----
3 files changed, 12 insertions(+), 28 deletions(-)
diff --git a/target-ppc/op.c b/target-ppc/op.c
index 01b944b..95ab8b9 100644
--- a/target-ppc/op.c
+++ b/target-ppc/op.c
@@ -233,30 +233,6 @@ void OPPROTO op_mask_spr (void)
RETURN();
}
-void OPPROTO op_load_lr (void)
-{
- T0 = env->lr;
- RETURN();
-}
-
-void OPPROTO op_store_lr (void)
-{
- env->lr = T0;
- RETURN();
-}
-
-void OPPROTO op_load_ctr (void)
-{
- T0 = env->ctr;
- RETURN();
-}
-
-void OPPROTO op_store_ctr (void)
-{
- env->ctr = T0;
- RETURN();
-}
-
void OPPROTO op_load_tbl (void)
{
T0 = cpu_ppc_load_tbl(env);
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 6561304..cc1f836 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -61,6 +61,8 @@ static TCGv cpu_fpr[32];
static TCGv cpu_avrh[32], cpu_avrl[32];
static TCGv cpu_crf[8];
static TCGv cpu_nip;
+static TCGv cpu_ctr;
+static TCGv cpu_lr;
/* dyngen register indexes */
static TCGv cpu_T[3];
@@ -168,6 +170,12 @@ void ppc_translate_init(void)
cpu_nip = tcg_global_mem_new(TCG_TYPE_TL, TCG_AREG0,
offsetof(CPUState, nip), "nip");
+ cpu_ctr = tcg_global_mem_new(TCG_TYPE_TL, TCG_AREG0,
+ offsetof(CPUState, ctr), "ctr");
+
+ cpu_lr = tcg_global_mem_new(TCG_TYPE_TL, TCG_AREG0,
+ offsetof(CPUState, lr), "lr");
+
/* register helpers */
#undef DEF_HELPER
#define DEF_HELPER(ret, name, params) tcg_register_helper(name,
#name);
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index 9393e3b..3e103dd 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -110,23 +110,23 @@ static void spr_write_xer (void *opaque, int sprn)
/* LR */
static void spr_read_lr (void *opaque, int sprn)
{
- gen_op_load_lr();
+ tcg_gen_mov_tl(cpu_T[0], cpu_lr);
}
static void spr_write_lr (void *opaque, int sprn)
{
- gen_op_store_lr();
+ tcg_gen_mov_tl(cpu_lr, cpu_T[0]);
}
/* CTR */
static void spr_read_ctr (void *opaque, int sprn)
{
- gen_op_load_ctr();
+ tcg_gen_mov_tl(cpu_T[0], cpu_ctr);
}
static void spr_write_ctr (void *opaque, int sprn)
{
- gen_op_store_ctr();
+ tcg_gen_mov_tl(cpu_ctr, cpu_T[0]);
}
/* User read access to SPR */
--
1.5.5.1
[-- Attachment #2: 0007-ppc-Convert-ctr-lr-moves-to-TCG.patch --]
[-- Type: application/octet-stream, Size: 2830 bytes --]
From bb2b875528b9150b1f8e6d53ee7dce4a4357ba20 Mon Sep 17 00:00:00 2001
From: =?utf-8?q?Andreas=20F=C3=A4rber?= <andreas.faerber@web.de>
Date: Wed, 10 Sep 2008 19:53:18 +0200
Subject: [PATCH] ppc: Convert ctr, lr moves to TCG
---
target-ppc/op.c | 24 ------------------------
target-ppc/translate.c | 8 ++++++++
target-ppc/translate_init.c | 8 ++++----
3 files changed, 12 insertions(+), 28 deletions(-)
diff --git a/target-ppc/op.c b/target-ppc/op.c
index 01b944b..95ab8b9 100644
--- a/target-ppc/op.c
+++ b/target-ppc/op.c
@@ -233,30 +233,6 @@ void OPPROTO op_mask_spr (void)
RETURN();
}
-void OPPROTO op_load_lr (void)
-{
- T0 = env->lr;
- RETURN();
-}
-
-void OPPROTO op_store_lr (void)
-{
- env->lr = T0;
- RETURN();
-}
-
-void OPPROTO op_load_ctr (void)
-{
- T0 = env->ctr;
- RETURN();
-}
-
-void OPPROTO op_store_ctr (void)
-{
- env->ctr = T0;
- RETURN();
-}
-
void OPPROTO op_load_tbl (void)
{
T0 = cpu_ppc_load_tbl(env);
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 6561304..cc1f836 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -61,6 +61,8 @@ static TCGv cpu_fpr[32];
static TCGv cpu_avrh[32], cpu_avrl[32];
static TCGv cpu_crf[8];
static TCGv cpu_nip;
+static TCGv cpu_ctr;
+static TCGv cpu_lr;
/* dyngen register indexes */
static TCGv cpu_T[3];
@@ -168,6 +170,12 @@ void ppc_translate_init(void)
cpu_nip = tcg_global_mem_new(TCG_TYPE_TL, TCG_AREG0,
offsetof(CPUState, nip), "nip");
+ cpu_ctr = tcg_global_mem_new(TCG_TYPE_TL, TCG_AREG0,
+ offsetof(CPUState, ctr), "ctr");
+
+ cpu_lr = tcg_global_mem_new(TCG_TYPE_TL, TCG_AREG0,
+ offsetof(CPUState, lr), "lr");
+
/* register helpers */
#undef DEF_HELPER
#define DEF_HELPER(ret, name, params) tcg_register_helper(name, #name);
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index 9393e3b..3e103dd 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -110,23 +110,23 @@ static void spr_write_xer (void *opaque, int sprn)
/* LR */
static void spr_read_lr (void *opaque, int sprn)
{
- gen_op_load_lr();
+ tcg_gen_mov_tl(cpu_T[0], cpu_lr);
}
static void spr_write_lr (void *opaque, int sprn)
{
- gen_op_store_lr();
+ tcg_gen_mov_tl(cpu_lr, cpu_T[0]);
}
/* CTR */
static void spr_read_ctr (void *opaque, int sprn)
{
- gen_op_load_ctr();
+ tcg_gen_mov_tl(cpu_T[0], cpu_ctr);
}
static void spr_write_ctr (void *opaque, int sprn)
{
- gen_op_store_ctr();
+ tcg_gen_mov_tl(cpu_ctr, cpu_T[0]);
}
/* User read access to SPR */
--
1.5.5.1
^ permalink raw reply related [flat|nested] 10+ messages in thread
* Re: [Qemu-devel] [PATCH 2/2] ppc: Convert op_andi to TCG
2008-09-14 11:06 [Qemu-devel] [PATCH 1/2] ppc: Convert ctr, lr moves to TCG Andreas Färber
@ 2008-09-14 11:23 ` Andreas Färber
2008-09-14 11:35 ` Blue Swirl
2008-09-14 18:34 ` Aurelien Jarno
2008-09-14 18:30 ` [Qemu-devel] [PATCH 1/2] ppc: Convert ctr, lr moves " Aurelien Jarno
1 sibling, 2 replies; 10+ messages in thread
From: Andreas Färber @ 2008-09-14 11:23 UTC (permalink / raw)
To: qemu-devel; +Cc: Aurelien Jarno
[-- Attachment #1: Type: text/plain, Size: 6002 bytes --]
Replace op_andi_... with tcg_gen_andi_tl.
Signed-off-by: Andreas Faerber <andreas.faerber@web.de>
---
This patch reveals a problem with the crf conversion to i32:
As you can see we now have a mix of _tl and _i32 for cpu_T[].
I would suggest to convert cpu_crf to tl to avoid problems
(it was converted from i8 to i32 previously).
target-ppc/op.c | 27 ---------------------------
target-ppc/translate.c | 38 +++++++++++---------------------------
2 files changed, 11 insertions(+), 54 deletions(-)
diff --git a/target-ppc/op.c b/target-ppc/op.c
index 95ab8b9..6416659 100644
--- a/target-ppc/op.c
+++ b/target-ppc/op.c
@@ -1153,33 +1153,6 @@ void OPPROTO op_andc (void)
RETURN();
}
-/* andi. */
-void OPPROTO op_andi_T0 (void)
-{
- T0 &= (uint32_t)PARAM1;
- RETURN();
-}
-
-void OPPROTO op_andi_T1 (void)
-{
- T1 &= (uint32_t)PARAM1;
- RETURN();
-}
-
-#if defined(TARGET_PPC64)
-void OPPROTO op_andi_T0_64 (void)
-{
- T0 &= ((uint64_t)PARAM1 << 32) | (uint64_t)PARAM2;
- RETURN();
-}
-
-void OPPROTO op_andi_T1_64 (void)
-{
- T1 &= ((uint64_t)PARAM1 << 32) | (uint64_t)PARAM2;
- RETURN();
-}
-#endif
-
/* count leading zero */
void OPPROTO op_cntlzw (void)
{
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index cc1f836..56bdef2 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -1235,7 +1235,7 @@ GEN_LOGICAL2(andc, 0x01, PPC_INTEGER);
GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000,
PPC_INTEGER)
{
tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
- gen_op_andi_T0(UIMM(ctx->opcode));
+ tcg_gen_andi_tl(cpu_T[0], cpu_T[0], UIMM(ctx->opcode));
tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
gen_set_Rc0(ctx);
}
@@ -1243,7 +1243,7 @@ GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF,
0x00000000, PPC_INTEGER)
GEN_HANDLER2(andis_, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000,
PPC_INTEGER)
{
tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
- gen_op_andi_T0(UIMM(ctx->opcode) << 16);
+ tcg_gen_andi_tl(cpu_T[0], cpu_T[0], UIMM(ctx->opcode) << 16);
tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
gen_set_Rc0(ctx);
}
@@ -1458,8 +1458,8 @@ GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF,
0x00000000, PPC_INTEGER)
me += 32;
#endif
mask = MASK(mb, me);
- gen_op_andi_T0(mask);
- gen_op_andi_T1(~mask);
+ tcg_gen_andi_tl(cpu_T[0], cpu_T[0], mask);
+ tcg_gen_andi_tl(cpu_T[1], cpu_T[1], ~mask);
gen_op_or();
do_store:
tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
@@ -1498,7 +1498,7 @@ GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF,
0x00000000, PPC_INTEGER)
mb += 32;
me += 32;
#endif
- gen_op_andi_T0(MASK(mb, me));
+ tcg_gen_andi_tl(cpu_T[0], cpu_T[0], MASK(mb, me));
do_store:
tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
if (unlikely(Rc(ctx->opcode) != 0))
@@ -1519,7 +1519,7 @@ GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000,
PPC_INTEGER)
mb += 32;
me += 32;
#endif
- gen_op_andi_T0(MASK(mb, me));
+ tcg_gen_andi_tl(cpu_T[0], cpu_T[0], MASK(mb, me));
}
tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
if (unlikely(Rc(ctx->opcode) != 0))
@@ -1558,22 +1558,6 @@ GEN_HANDLER2(name##3, stringify(name), opc1,
opc2 | 0x11, 0xFF, 0x00000000, \
gen_##name(ctx, 1,
1); \
}
-static always_inline void gen_andi_T0_64 (DisasContext *ctx, uint64_t
mask)
-{
- if (mask >> 32)
- gen_op_andi_T0_64(mask >> 32, mask & 0xFFFFFFFF);
- else
- gen_op_andi_T0(mask);
-}
-
-static always_inline void gen_andi_T1_64 (DisasContext *ctx, uint64_t
mask)
-{
- if (mask >> 32)
- gen_op_andi_T1_64(mask >> 32, mask & 0xFFFFFFFF);
- else
- gen_op_andi_T1(mask);
-}
-
static always_inline void gen_rldinm (DisasContext *ctx, uint32_t mb,
uint32_t me, uint32_t sh)
{
@@ -1597,7 +1581,7 @@ static always_inline void gen_rldinm
(DisasContext *ctx, uint32_t mb,
}
gen_op_rotli64_T0(sh);
do_mask:
- gen_andi_T0_64(ctx, MASK(mb, me));
+ tcg_gen_andi_tl(cpu_T[0], cpu_T[0], MASK(mb, me));
do_store:
tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
if (unlikely(Rc(ctx->opcode) != 0))
@@ -1641,7 +1625,7 @@ static always_inline void gen_rldnm
(DisasContext *ctx, uint32_t mb,
tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
gen_op_rotl64_T0_T1();
if (unlikely(mb != 0 || me != 63)) {
- gen_andi_T0_64(ctx, MASK(mb, me));
+ tcg_gen_andi_tl(cpu_T[0], cpu_T[0], MASK(mb, me));
}
tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
if (unlikely(Rc(ctx->opcode) != 0))
@@ -1689,8 +1673,8 @@ static always_inline void gen_rldimi
(DisasContext *ctx, int mbn, int shn)
gen_op_rotli64_T0(sh);
do_mask:
mask = MASK(mb, me);
- gen_andi_T0_64(ctx, mask);
- gen_andi_T1_64(ctx, ~mask);
+ tcg_gen_andi_tl(cpu_T[0], cpu_T[0], mask);
+ tcg_gen_andi_tl(cpu_T[1], cpu_T[1], ~mask);
gen_op_or();
do_store:
tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
@@ -3107,7 +3091,7 @@ GEN_HANDLER(cr##op, 0x13, 0x01, opc, 0x00000001,
PPC_INTEGER) \
gen_op_sli_T1(-
sh); \
gen_op_
##op(); \
bitmask = 1 << (3 - (crbD(ctx->opcode) &
0x03)); \
-
gen_op_andi_T0
(bitmask); \
+ tcg_gen_andi_tl(cpu_T[0], cpu_T[0],
bitmask); \
tcg_gen_andi_i32(cpu_T[1], cpu_crf[crbD(ctx->opcode) >> 2],
~bitmask); \
gen_op_or
(); \
tcg_gen_andi_i32(cpu_crf[crbD(ctx->opcode) >> 2], cpu_T[0],
0xf); \
--
1.5.5.1
[-- Attachment #2: 0008-ppc-Convert-op_addi-to-TCG.patch --]
[-- Type: application/octet-stream, Size: 5933 bytes --]
From 05db8360d4ec1fa7890bcf8dbe37a278fbc837c9 Mon Sep 17 00:00:00 2001
From: =?utf-8?q?Andreas=20F=C3=A4rber?= <andreas.faerber@web.de>
Date: Wed, 10 Sep 2008 20:00:08 +0200
Subject: [PATCH] ppc: Convert op_addi to TCG
---
target-ppc/op.c | 27 ---------------------------
target-ppc/translate.c | 38 +++++++++++---------------------------
2 files changed, 11 insertions(+), 54 deletions(-)
diff --git a/target-ppc/op.c b/target-ppc/op.c
index 95ab8b9..6416659 100644
--- a/target-ppc/op.c
+++ b/target-ppc/op.c
@@ -1153,33 +1153,6 @@ void OPPROTO op_andc (void)
RETURN();
}
-/* andi. */
-void OPPROTO op_andi_T0 (void)
-{
- T0 &= (uint32_t)PARAM1;
- RETURN();
-}
-
-void OPPROTO op_andi_T1 (void)
-{
- T1 &= (uint32_t)PARAM1;
- RETURN();
-}
-
-#if defined(TARGET_PPC64)
-void OPPROTO op_andi_T0_64 (void)
-{
- T0 &= ((uint64_t)PARAM1 << 32) | (uint64_t)PARAM2;
- RETURN();
-}
-
-void OPPROTO op_andi_T1_64 (void)
-{
- T1 &= ((uint64_t)PARAM1 << 32) | (uint64_t)PARAM2;
- RETURN();
-}
-#endif
-
/* count leading zero */
void OPPROTO op_cntlzw (void)
{
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index cc1f836..56bdef2 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -1235,7 +1235,7 @@ GEN_LOGICAL2(andc, 0x01, PPC_INTEGER);
GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
{
tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
- gen_op_andi_T0(UIMM(ctx->opcode));
+ tcg_gen_andi_tl(cpu_T[0], cpu_T[0], UIMM(ctx->opcode));
tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
gen_set_Rc0(ctx);
}
@@ -1243,7 +1243,7 @@ GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
GEN_HANDLER2(andis_, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
{
tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
- gen_op_andi_T0(UIMM(ctx->opcode) << 16);
+ tcg_gen_andi_tl(cpu_T[0], cpu_T[0], UIMM(ctx->opcode) << 16);
tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
gen_set_Rc0(ctx);
}
@@ -1458,8 +1458,8 @@ GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
me += 32;
#endif
mask = MASK(mb, me);
- gen_op_andi_T0(mask);
- gen_op_andi_T1(~mask);
+ tcg_gen_andi_tl(cpu_T[0], cpu_T[0], mask);
+ tcg_gen_andi_tl(cpu_T[1], cpu_T[1], ~mask);
gen_op_or();
do_store:
tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
@@ -1498,7 +1498,7 @@ GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
mb += 32;
me += 32;
#endif
- gen_op_andi_T0(MASK(mb, me));
+ tcg_gen_andi_tl(cpu_T[0], cpu_T[0], MASK(mb, me));
do_store:
tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
if (unlikely(Rc(ctx->opcode) != 0))
@@ -1519,7 +1519,7 @@ GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
mb += 32;
me += 32;
#endif
- gen_op_andi_T0(MASK(mb, me));
+ tcg_gen_andi_tl(cpu_T[0], cpu_T[0], MASK(mb, me));
}
tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
if (unlikely(Rc(ctx->opcode) != 0))
@@ -1558,22 +1558,6 @@ GEN_HANDLER2(name##3, stringify(name), opc1, opc2 | 0x11, 0xFF, 0x00000000, \
gen_##name(ctx, 1, 1); \
}
-static always_inline void gen_andi_T0_64 (DisasContext *ctx, uint64_t mask)
-{
- if (mask >> 32)
- gen_op_andi_T0_64(mask >> 32, mask & 0xFFFFFFFF);
- else
- gen_op_andi_T0(mask);
-}
-
-static always_inline void gen_andi_T1_64 (DisasContext *ctx, uint64_t mask)
-{
- if (mask >> 32)
- gen_op_andi_T1_64(mask >> 32, mask & 0xFFFFFFFF);
- else
- gen_op_andi_T1(mask);
-}
-
static always_inline void gen_rldinm (DisasContext *ctx, uint32_t mb,
uint32_t me, uint32_t sh)
{
@@ -1597,7 +1581,7 @@ static always_inline void gen_rldinm (DisasContext *ctx, uint32_t mb,
}
gen_op_rotli64_T0(sh);
do_mask:
- gen_andi_T0_64(ctx, MASK(mb, me));
+ tcg_gen_andi_tl(cpu_T[0], cpu_T[0], MASK(mb, me));
do_store:
tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
if (unlikely(Rc(ctx->opcode) != 0))
@@ -1641,7 +1625,7 @@ static always_inline void gen_rldnm (DisasContext *ctx, uint32_t mb,
tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
gen_op_rotl64_T0_T1();
if (unlikely(mb != 0 || me != 63)) {
- gen_andi_T0_64(ctx, MASK(mb, me));
+ tcg_gen_andi_tl(cpu_T[0], cpu_T[0], MASK(mb, me));
}
tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
if (unlikely(Rc(ctx->opcode) != 0))
@@ -1689,8 +1673,8 @@ static always_inline void gen_rldimi (DisasContext *ctx, int mbn, int shn)
gen_op_rotli64_T0(sh);
do_mask:
mask = MASK(mb, me);
- gen_andi_T0_64(ctx, mask);
- gen_andi_T1_64(ctx, ~mask);
+ tcg_gen_andi_tl(cpu_T[0], cpu_T[0], mask);
+ tcg_gen_andi_tl(cpu_T[1], cpu_T[1], ~mask);
gen_op_or();
do_store:
tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
@@ -3107,7 +3091,7 @@ GEN_HANDLER(cr##op, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER) \
gen_op_sli_T1(-sh); \
gen_op_##op(); \
bitmask = 1 << (3 - (crbD(ctx->opcode) & 0x03)); \
- gen_op_andi_T0(bitmask); \
+ tcg_gen_andi_tl(cpu_T[0], cpu_T[0], bitmask); \
tcg_gen_andi_i32(cpu_T[1], cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask); \
gen_op_or(); \
tcg_gen_andi_i32(cpu_crf[crbD(ctx->opcode) >> 2], cpu_T[0], 0xf); \
--
1.5.5.1
^ permalink raw reply related [flat|nested] 10+ messages in thread
* Re: [Qemu-devel] [PATCH 2/2] ppc: Convert op_andi to TCG
2008-09-14 11:23 ` [Qemu-devel] [PATCH 2/2] ppc: Convert op_andi " Andreas Färber
@ 2008-09-14 11:35 ` Blue Swirl
2008-09-14 11:48 ` Andreas Färber
2008-09-14 18:34 ` Aurelien Jarno
1 sibling, 1 reply; 10+ messages in thread
From: Blue Swirl @ 2008-09-14 11:35 UTC (permalink / raw)
To: qemu-devel, Andreas Färber; +Cc: Aurelien Jarno
On 9/14/08, Andreas Färber <andreas.faerber@web.de> wrote:
> Replace op_andi_... with tcg_gen_andi_tl.
> GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
> {
> tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
> - gen_op_andi_T0(UIMM(ctx->opcode));
> + tcg_gen_andi_tl(cpu_T[0], cpu_T[0], UIMM(ctx->opcode));
> tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
> gen_set_Rc0(ctx);
> }
Small comment: this would be more optimally:
tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)],
cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode));
The same applies to andis.
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [Qemu-devel] [PATCH 2/2] ppc: Convert op_andi to TCG
2008-09-14 11:35 ` Blue Swirl
@ 2008-09-14 11:48 ` Andreas Färber
2008-09-14 11:53 ` Blue Swirl
0 siblings, 1 reply; 10+ messages in thread
From: Andreas Färber @ 2008-09-14 11:48 UTC (permalink / raw)
To: Blue Swirl; +Cc: qemu-devel, Aurelien Jarno
Am 14.09.2008 um 13:35 schrieb Blue Swirl:
> On 9/14/08, Andreas Färber <andreas.faerber@web.de> wrote:
>> Replace op_andi_... with tcg_gen_andi_tl.
>
>> GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000,
>> PPC_INTEGER)
>> {
>> tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
>> - gen_op_andi_T0(UIMM(ctx->opcode));
>> + tcg_gen_andi_tl(cpu_T[0], cpu_T[0], UIMM(ctx->opcode));
>> tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
>> gen_set_Rc0(ctx);
>> }
>
> Small comment: this would be more optimally:
> tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)],
> cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode));
>
> The same applies to andis.
Careful there, iirc this cannot be done before gen_set_Rc0 is converted!
Andreas
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [Qemu-devel] [PATCH 2/2] ppc: Convert op_andi to TCG
2008-09-14 11:48 ` Andreas Färber
@ 2008-09-14 11:53 ` Blue Swirl
2008-09-14 12:02 ` Andreas Färber
2008-09-14 12:03 ` Paul Brook
0 siblings, 2 replies; 10+ messages in thread
From: Blue Swirl @ 2008-09-14 11:53 UTC (permalink / raw)
To: Andreas Färber; +Cc: qemu-devel, Aurelien Jarno
On 9/14/08, Andreas Färber <andreas.faerber@web.de> wrote:
>
> Am 14.09.2008 um 13:35 schrieb Blue Swirl:
>
>
>
> > On 9/14/08, Andreas Färber <andreas.faerber@web.de> wrote:
> >
> > > Replace op_andi_... with tcg_gen_andi_tl.
> > >
> >
> >
> > > GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
> > > {
> > > tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
> > > - gen_op_andi_T0(UIMM(ctx->opcode));
> > > + tcg_gen_andi_tl(cpu_T[0], cpu_T[0], UIMM(ctx->opcode));
> > > tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
> > > gen_set_Rc0(ctx);
> > > }
> > >
> >
> > Small comment: this would be more optimally:
> > tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)],
> > cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode));
> >
> > The same applies to andis.
> >
>
> Careful there, iirc this cannot be done before gen_set_Rc0 is converted!
I didn't mean to remove gen_set_Rc0, the comment only applied to the
mov+andi+mov sequence.
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [Qemu-devel] [PATCH 2/2] ppc: Convert op_andi to TCG
2008-09-14 11:53 ` Blue Swirl
@ 2008-09-14 12:02 ` Andreas Färber
2008-09-14 12:03 ` Paul Brook
1 sibling, 0 replies; 10+ messages in thread
From: Andreas Färber @ 2008-09-14 12:02 UTC (permalink / raw)
To: Blue Swirl; +Cc: qemu-devel, Aurelien Jarno
Am 14.09.2008 um 13:53 schrieb Blue Swirl:
> On 9/14/08, Andreas Färber <andreas.faerber@web.de> wrote:
>>
>> Am 14.09.2008 um 13:35 schrieb Blue Swirl:
>>
>>
>>
>>> On 9/14/08, Andreas Färber <andreas.faerber@web.de> wrote:
>>>
>>>> Replace op_andi_... with tcg_gen_andi_tl.
>>>>
>>>
>>>
>>>> GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000,
>>>> PPC_INTEGER)
>>>> {
>>>> tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
>>>> - gen_op_andi_T0(UIMM(ctx->opcode));
>>>> + tcg_gen_andi_tl(cpu_T[0], cpu_T[0], UIMM(ctx->opcode));
>>>> tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
>>>> gen_set_Rc0(ctx);
>>>> }
>>>>
>>>
>>> Small comment: this would be more optimally:
>>> tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)],
>>> cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode));
>>>
>>> The same applies to andis.
>>>
>>
>> Careful there, iirc this cannot be done before gen_set_Rc0 is
>> converted!
>
> I didn't mean to remove gen_set_Rc0, the comment only applied to the
> mov+andi+mov sequence.
Right, but this optimization would require to move from gpr to T0
after the suggested mov+andi+mov optimization and before this
gen_set_Rc0 thing. That would still save one line, so feel free to
modify my patch or apply another one on top.
Andreas
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [Qemu-devel] [PATCH 2/2] ppc: Convert op_andi to TCG
2008-09-14 11:53 ` Blue Swirl
2008-09-14 12:02 ` Andreas Färber
@ 2008-09-14 12:03 ` Paul Brook
2008-09-14 12:13 ` Blue Swirl
1 sibling, 1 reply; 10+ messages in thread
From: Paul Brook @ 2008-09-14 12:03 UTC (permalink / raw)
To: qemu-devel; +Cc: Blue Swirl, Andreas Färber, Aurelien Jarno
> > > > tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
> > > > - gen_op_andi_T0(UIMM(ctx->opcode));
> > > > + tcg_gen_andi_tl(cpu_T[0], cpu_T[0], UIMM(ctx->opcode));
> > > > tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
> > > > gen_set_Rc0(ctx);
> > > > }
> > >
> > > Small comment: this would be more optimally:
> > > tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)],
> > > cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode));
> > >
> > > The same applies to andis.
> >
> > Careful there, iirc this cannot be done before gen_set_Rc0 is converted!
>
> I didn't mean to remove gen_set_Rc0, the comment only applied to the
> mov+andi+mov sequence.
set_Rc0 relies on T0 being set correctly be the preceding sequence.
Paul
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [Qemu-devel] [PATCH 2/2] ppc: Convert op_andi to TCG
2008-09-14 12:03 ` Paul Brook
@ 2008-09-14 12:13 ` Blue Swirl
0 siblings, 0 replies; 10+ messages in thread
From: Blue Swirl @ 2008-09-14 12:13 UTC (permalink / raw)
To: Paul Brook; +Cc: Andreas Färber, qemu-devel, Aurelien Jarno
On 9/14/08, Paul Brook <paul@codesourcery.com> wrote:
> > > > > tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
> > > > > - gen_op_andi_T0(UIMM(ctx->opcode));
> > > > > + tcg_gen_andi_tl(cpu_T[0], cpu_T[0], UIMM(ctx->opcode));
> > > > > tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
> > > > > gen_set_Rc0(ctx);
> > > > > }
> > > >
> > > > Small comment: this would be more optimally:
> > > > tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)],
> > > > cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode));
> > > >
> > > > The same applies to andis.
> > >
> > > Careful there, iirc this cannot be done before gen_set_Rc0 is converted!
> >
> > I didn't mean to remove gen_set_Rc0, the comment only applied to the
> > mov+andi+mov sequence.
>
>
> set_Rc0 relies on T0 being set correctly be the preceding sequence.
I see. I just read the patch, not the affected code, sorry for the noise.
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [Qemu-devel] [PATCH 1/2] ppc: Convert ctr, lr moves to TCG
2008-09-14 11:06 [Qemu-devel] [PATCH 1/2] ppc: Convert ctr, lr moves to TCG Andreas Färber
2008-09-14 11:23 ` [Qemu-devel] [PATCH 2/2] ppc: Convert op_andi " Andreas Färber
@ 2008-09-14 18:30 ` Aurelien Jarno
1 sibling, 0 replies; 10+ messages in thread
From: Aurelien Jarno @ 2008-09-14 18:30 UTC (permalink / raw)
To: qemu-devel
On Sun, Sep 14, 2008 at 01:06:05PM +0200, Andreas Färber wrote:
> Introduce TCG variables cpu_{ctr,lr} and replace
> op_{load,store}_{lr,ctr} with tcg_gen_mov_tl.
>
> Signed-off-by: Andreas Faerber <andreas.faerber@web.de>
Applied, thanks.
> ---
> Hello,
>
> A quick inbox search for ppc did not reveal new patches, so I hope
> these two still apply.
>
> Andreas
>
> target-ppc/op.c | 24 ------------------------
> target-ppc/translate.c | 8 ++++++++
> target-ppc/translate_init.c | 8 ++++----
> 3 files changed, 12 insertions(+), 28 deletions(-)
>
> diff --git a/target-ppc/op.c b/target-ppc/op.c
> index 01b944b..95ab8b9 100644
> --- a/target-ppc/op.c
> +++ b/target-ppc/op.c
> @@ -233,30 +233,6 @@ void OPPROTO op_mask_spr (void)
> RETURN();
> }
>
> -void OPPROTO op_load_lr (void)
> -{
> - T0 = env->lr;
> - RETURN();
> -}
> -
> -void OPPROTO op_store_lr (void)
> -{
> - env->lr = T0;
> - RETURN();
> -}
> -
> -void OPPROTO op_load_ctr (void)
> -{
> - T0 = env->ctr;
> - RETURN();
> -}
> -
> -void OPPROTO op_store_ctr (void)
> -{
> - env->ctr = T0;
> - RETURN();
> -}
> -
> void OPPROTO op_load_tbl (void)
> {
> T0 = cpu_ppc_load_tbl(env);
> diff --git a/target-ppc/translate.c b/target-ppc/translate.c
> index 6561304..cc1f836 100644
> --- a/target-ppc/translate.c
> +++ b/target-ppc/translate.c
> @@ -61,6 +61,8 @@ static TCGv cpu_fpr[32];
> static TCGv cpu_avrh[32], cpu_avrl[32];
> static TCGv cpu_crf[8];
> static TCGv cpu_nip;
> +static TCGv cpu_ctr;
> +static TCGv cpu_lr;
>
> /* dyngen register indexes */
> static TCGv cpu_T[3];
> @@ -168,6 +170,12 @@ void ppc_translate_init(void)
> cpu_nip = tcg_global_mem_new(TCG_TYPE_TL, TCG_AREG0,
> offsetof(CPUState, nip), "nip");
>
> + cpu_ctr = tcg_global_mem_new(TCG_TYPE_TL, TCG_AREG0,
> + offsetof(CPUState, ctr), "ctr");
> +
> + cpu_lr = tcg_global_mem_new(TCG_TYPE_TL, TCG_AREG0,
> + offsetof(CPUState, lr), "lr");
> +
> /* register helpers */
> #undef DEF_HELPER
> #define DEF_HELPER(ret, name, params) tcg_register_helper(name, #name);
> diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
> index 9393e3b..3e103dd 100644
> --- a/target-ppc/translate_init.c
> +++ b/target-ppc/translate_init.c
> @@ -110,23 +110,23 @@ static void spr_write_xer (void *opaque, int sprn)
> /* LR */
> static void spr_read_lr (void *opaque, int sprn)
> {
> - gen_op_load_lr();
> + tcg_gen_mov_tl(cpu_T[0], cpu_lr);
> }
>
> static void spr_write_lr (void *opaque, int sprn)
> {
> - gen_op_store_lr();
> + tcg_gen_mov_tl(cpu_lr, cpu_T[0]);
> }
>
> /* CTR */
> static void spr_read_ctr (void *opaque, int sprn)
> {
> - gen_op_load_ctr();
> + tcg_gen_mov_tl(cpu_T[0], cpu_ctr);
> }
>
> static void spr_write_ctr (void *opaque, int sprn)
> {
> - gen_op_store_ctr();
> + tcg_gen_mov_tl(cpu_ctr, cpu_T[0]);
> }
>
> /* User read access to SPR */
> --
> 1.5.5.1
>
--
.''`. Aurelien Jarno | GPG: 1024D/F1BCDB73
: :' : Debian developer | Electrical Engineer
`. `' aurel32@debian.org | aurelien@aurel32.net
`- people.debian.org/~aurel32 | www.aurel32.net
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [Qemu-devel] [PATCH 2/2] ppc: Convert op_andi to TCG
2008-09-14 11:23 ` [Qemu-devel] [PATCH 2/2] ppc: Convert op_andi " Andreas Färber
2008-09-14 11:35 ` Blue Swirl
@ 2008-09-14 18:34 ` Aurelien Jarno
1 sibling, 0 replies; 10+ messages in thread
From: Aurelien Jarno @ 2008-09-14 18:34 UTC (permalink / raw)
To: qemu-devel
On Sun, Sep 14, 2008 at 01:23:42PM +0200, Andreas Färber wrote:
> Replace op_andi_... with tcg_gen_andi_tl.
>
> Signed-off-by: Andreas Faerber <andreas.faerber@web.de>
Applied, thanks.
> ---
> This patch reveals a problem with the crf conversion to i32:
> As you can see we now have a mix of _tl and _i32 for cpu_T[].
> I would suggest to convert cpu_crf to tl to avoid problems
> (it was converted from i8 to i32 previously).
While I agree there is a problem, I disagree about the solution. cpu_T[]
registers will eventually disappear. Changing things to match them is a
bad idea. The solution is to get rid of them in functions manipulating
cpu_crf. I'll commit a patch later to fix that.
> target-ppc/op.c | 27 ---------------------------
> target-ppc/translate.c | 38 +++++++++++---------------------------
> 2 files changed, 11 insertions(+), 54 deletions(-)
>
> diff --git a/target-ppc/op.c b/target-ppc/op.c
> index 95ab8b9..6416659 100644
> --- a/target-ppc/op.c
> +++ b/target-ppc/op.c
> @@ -1153,33 +1153,6 @@ void OPPROTO op_andc (void)
> RETURN();
> }
>
> -/* andi. */
> -void OPPROTO op_andi_T0 (void)
> -{
> - T0 &= (uint32_t)PARAM1;
> - RETURN();
> -}
> -
> -void OPPROTO op_andi_T1 (void)
> -{
> - T1 &= (uint32_t)PARAM1;
> - RETURN();
> -}
> -
> -#if defined(TARGET_PPC64)
> -void OPPROTO op_andi_T0_64 (void)
> -{
> - T0 &= ((uint64_t)PARAM1 << 32) | (uint64_t)PARAM2;
> - RETURN();
> -}
> -
> -void OPPROTO op_andi_T1_64 (void)
> -{
> - T1 &= ((uint64_t)PARAM1 << 32) | (uint64_t)PARAM2;
> - RETURN();
> -}
> -#endif
> -
> /* count leading zero */
> void OPPROTO op_cntlzw (void)
> {
> diff --git a/target-ppc/translate.c b/target-ppc/translate.c
> index cc1f836..56bdef2 100644
> --- a/target-ppc/translate.c
> +++ b/target-ppc/translate.c
> @@ -1235,7 +1235,7 @@ GEN_LOGICAL2(andc, 0x01, PPC_INTEGER);
> GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
> {
> tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
> - gen_op_andi_T0(UIMM(ctx->opcode));
> + tcg_gen_andi_tl(cpu_T[0], cpu_T[0], UIMM(ctx->opcode));
> tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
> gen_set_Rc0(ctx);
> }
> @@ -1243,7 +1243,7 @@ GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF,
> 0x00000000, PPC_INTEGER)
> GEN_HANDLER2(andis_, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000,
> PPC_INTEGER)
> {
> tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
> - gen_op_andi_T0(UIMM(ctx->opcode) << 16);
> + tcg_gen_andi_tl(cpu_T[0], cpu_T[0], UIMM(ctx->opcode) << 16);
> tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
> gen_set_Rc0(ctx);
> }
> @@ -1458,8 +1458,8 @@ GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000,
> PPC_INTEGER)
> me += 32;
> #endif
> mask = MASK(mb, me);
> - gen_op_andi_T0(mask);
> - gen_op_andi_T1(~mask);
> + tcg_gen_andi_tl(cpu_T[0], cpu_T[0], mask);
> + tcg_gen_andi_tl(cpu_T[1], cpu_T[1], ~mask);
> gen_op_or();
> do_store:
> tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
> @@ -1498,7 +1498,7 @@ GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000,
> PPC_INTEGER)
> mb += 32;
> me += 32;
> #endif
> - gen_op_andi_T0(MASK(mb, me));
> + tcg_gen_andi_tl(cpu_T[0], cpu_T[0], MASK(mb, me));
> do_store:
> tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
> if (unlikely(Rc(ctx->opcode) != 0))
> @@ -1519,7 +1519,7 @@ GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000,
> PPC_INTEGER)
> mb += 32;
> me += 32;
> #endif
> - gen_op_andi_T0(MASK(mb, me));
> + tcg_gen_andi_tl(cpu_T[0], cpu_T[0], MASK(mb, me));
> }
> tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
> if (unlikely(Rc(ctx->opcode) != 0))
> @@ -1558,22 +1558,6 @@ GEN_HANDLER2(name##3, stringify(name), opc1, opc2
> | 0x11, 0xFF, 0x00000000, \
> gen_##name(ctx, 1, 1);
> \
> }
>
> -static always_inline void gen_andi_T0_64 (DisasContext *ctx, uint64_t
> mask)
> -{
> - if (mask >> 32)
> - gen_op_andi_T0_64(mask >> 32, mask & 0xFFFFFFFF);
> - else
> - gen_op_andi_T0(mask);
> -}
> -
> -static always_inline void gen_andi_T1_64 (DisasContext *ctx, uint64_t
> mask)
> -{
> - if (mask >> 32)
> - gen_op_andi_T1_64(mask >> 32, mask & 0xFFFFFFFF);
> - else
> - gen_op_andi_T1(mask);
> -}
> -
> static always_inline void gen_rldinm (DisasContext *ctx, uint32_t mb,
> uint32_t me, uint32_t sh)
> {
> @@ -1597,7 +1581,7 @@ static always_inline void gen_rldinm (DisasContext
> *ctx, uint32_t mb,
> }
> gen_op_rotli64_T0(sh);
> do_mask:
> - gen_andi_T0_64(ctx, MASK(mb, me));
> + tcg_gen_andi_tl(cpu_T[0], cpu_T[0], MASK(mb, me));
> do_store:
> tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
> if (unlikely(Rc(ctx->opcode) != 0))
> @@ -1641,7 +1625,7 @@ static always_inline void gen_rldnm (DisasContext
> *ctx, uint32_t mb,
> tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
> gen_op_rotl64_T0_T1();
> if (unlikely(mb != 0 || me != 63)) {
> - gen_andi_T0_64(ctx, MASK(mb, me));
> + tcg_gen_andi_tl(cpu_T[0], cpu_T[0], MASK(mb, me));
> }
> tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
> if (unlikely(Rc(ctx->opcode) != 0))
> @@ -1689,8 +1673,8 @@ static always_inline void gen_rldimi (DisasContext
> *ctx, int mbn, int shn)
> gen_op_rotli64_T0(sh);
> do_mask:
> mask = MASK(mb, me);
> - gen_andi_T0_64(ctx, mask);
> - gen_andi_T1_64(ctx, ~mask);
> + tcg_gen_andi_tl(cpu_T[0], cpu_T[0], mask);
> + tcg_gen_andi_tl(cpu_T[1], cpu_T[1], ~mask);
> gen_op_or();
> do_store:
> tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
> @@ -3107,7 +3091,7 @@ GEN_HANDLER(cr##op, 0x13, 0x01, opc, 0x00000001,
> PPC_INTEGER) \
> gen_op_sli_T1(-sh);
> \
> gen_op_##op();
> \
> bitmask = 1 << (3 - (crbD(ctx->opcode) & 0x03));
> \
> - gen_op_andi_T0(bitmask);
> \
> + tcg_gen_andi_tl(cpu_T[0], cpu_T[0], bitmask);
> \
> tcg_gen_andi_i32(cpu_T[1], cpu_crf[crbD(ctx->opcode) >> 2],
> ~bitmask); \
> gen_op_or();
> \
> tcg_gen_andi_i32(cpu_crf[crbD(ctx->opcode) >> 2], cpu_T[0], 0xf);
> \
> --
> 1.5.5.1
>
--
.''`. Aurelien Jarno | GPG: 1024D/F1BCDB73
: :' : Debian developer | Electrical Engineer
`. `' aurel32@debian.org | aurelien@aurel32.net
`- people.debian.org/~aurel32 | www.aurel32.net
^ permalink raw reply [flat|nested] 10+ messages in thread
end of thread, other threads:[~2008-09-14 18:34 UTC | newest]
Thread overview: 10+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2008-09-14 11:06 [Qemu-devel] [PATCH 1/2] ppc: Convert ctr, lr moves to TCG Andreas Färber
2008-09-14 11:23 ` [Qemu-devel] [PATCH 2/2] ppc: Convert op_andi " Andreas Färber
2008-09-14 11:35 ` Blue Swirl
2008-09-14 11:48 ` Andreas Färber
2008-09-14 11:53 ` Blue Swirl
2008-09-14 12:02 ` Andreas Färber
2008-09-14 12:03 ` Paul Brook
2008-09-14 12:13 ` Blue Swirl
2008-09-14 18:34 ` Aurelien Jarno
2008-09-14 18:30 ` [Qemu-devel] [PATCH 1/2] ppc: Convert ctr, lr moves " Aurelien Jarno
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