From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1KhQRU-0001yu-Vn for qemu-devel@nongnu.org; Sun, 21 Sep 2008 11:01:45 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1KhQRT-0001wf-60 for qemu-devel@nongnu.org; Sun, 21 Sep 2008 11:01:44 -0400 Received: from [199.232.76.173] (port=43195 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1KhQRT-0001wc-0A for qemu-devel@nongnu.org; Sun, 21 Sep 2008 11:01:43 -0400 Received: from mail.codesourcery.com ([65.74.133.4]:60295) by monty-python.gnu.org with esmtps (TLS-1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.60) (envelope-from ) id 1KhQRS-0006oL-1o for qemu-devel@nongnu.org; Sun, 21 Sep 2008 11:01:42 -0400 From: Paul Brook Subject: Re: [Qemu-devel] [5281] Use the new concat_i32_i64 op for std and stda Date: Sun, 21 Sep 2008 16:01:34 +0100 References: In-Reply-To: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Content-Disposition: inline Message-Id: <200809211601.35191.paul@codesourcery.com> Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Blue Swirl On Sunday 21 September 2008, Blue Swirl wrote: > + =C2=A0 =C2=A0r_low =3D tcg_temp_new(TCG_TYPE_I32); > + =C2=A0 =C2=A0tcg_gen_trunc_tl_i32(r_low, cpu_tmp0); > + =C2=A0 =C2=A0tcg_gen_trunc_tl_i32(cpu_tmp32, hi); > + =C2=A0 =C2=A0tcg_gen_concat_i32_i64(cpu_tmp64, r_low, cpu_tmp32); > + =C2=A0 =C2=A0tcg_temp_free(r_low); It's more efficient to not use concat_i32_i64 on 64-bit targets. See patch below. I'll let you decide if you want to apply or ignore it. Signed-off-by: Paul Brook Index: target-sparc/helper.h =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D =2D-- target-sparc/helper.h (revision 5280) +++ target-sparc/helper.h (working copy) @@ -44,7 +44,6 @@ DEF_HELPER(void, helper_restore, (void)) DEF_HELPER(void, helper_flush, (target_ulong addr)) DEF_HELPER(target_ulong, helper_udiv, (target_ulong a, target_ulong b)) DEF_HELPER(target_ulong, helper_sdiv, (target_ulong a, target_ulong b)) =2DDEF_HELPER(uint64_t, helper_pack64, (target_ulong high, target_ulong low= )) DEF_HELPER(void, helper_stdf, (target_ulong addr, int mem_idx)) DEF_HELPER(void, helper_lddf, (target_ulong addr, int mem_idx)) DEF_HELPER(void, helper_ldqf, (target_ulong addr, int mem_idx)) Index: target-sparc/op_helper.c =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D =2D-- target-sparc/op_helper.c (revision 5280) +++ target-sparc/op_helper.c (working copy) @@ -2281,11 +2281,6 @@ target_ulong helper_sdiv(target_ulong a, } } =20 =2Duint64_t helper_pack64(target_ulong high, target_ulong low) =2D{ =2D return ((uint64_t)high << 32) | (uint64_t)(low & 0xffffffff); =2D} =2D void helper_stdf(target_ulong addr, int mem_idx) { helper_check_align(addr, 7); Index: target-sparc/translate.c =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D =2D-- target-sparc/translate.c (revision 5280) +++ target-sparc/translate.c (working copy) @@ -1619,6 +1619,31 @@ static inline void gen_clear_float_excep tcg_gen_helper_0_0(helper_clear_float_exceptions); } =20 +/* May clobber low. */ +static void gen_pack64(TCGv dest, TCGv high, TCGv low) +{ +#ifdef TARGET_SPARC64 +#if HOST_LONG_BITS =3D=3D 64 + tcg_gen_shli_i64(dest, high, 32); + tcg_gen_ext32u_i64(low, low); + tcg_gen_or_i64(dest, dest, low); +# else + /* We could omit the truncation if we assumed that 64-bit TCG variables + can be used in 32-bit ops. Hopefully TCG will be smart enough to + eliminate the copy. */ + TCGv low32 =3D tcg_temp_new(TCG_TYPE_I32); + TCGv high32 =3D tcg_temp_new(TCG_TYPE_I32); + tcg_gen_trunc_i64_i32(low32, low); + tcg_gen_trunc_i64_i32(high32, high); + tcg_gen_concat_i32_i64(dest, low32, high32); + tcg_temp_free(high32); + tcg_temp_free(low32); +# endif +#else /* !TARGET_SPARC64 */ + tcg_gen_concat_i32_i64(dest, low, high); +#endif +} + /* asi moves */ #ifdef TARGET_SPARC64 static inline TCGv gen_get_asi(int insn, TCGv r_addr) @@ -1719,8 +1744,7 @@ static inline void gen_stda_asi(TCGv hi, =20 r_temp =3D tcg_temp_new(TCG_TYPE_TL); gen_movl_reg_TN(rd + 1, r_temp); =2D tcg_gen_helper_1_2(helper_pack64, cpu_tmp64, hi, =2D r_temp); + gen_pack64(cpu_tmp64, hi, r_temp); tcg_temp_free(r_temp); r_asi =3D gen_get_asi(insn, addr); r_size =3D tcg_const_i32(8); @@ -1821,7 +1845,7 @@ static inline void gen_stda_asi(TCGv hi, =20 r_temp =3D tcg_temp_new(TCG_TYPE_TL); gen_movl_reg_TN(rd + 1, r_temp); =2D tcg_gen_helper_1_2(helper_pack64, cpu_tmp64, hi, r_temp); + gen_pack64(cpu_tmp64, hi, r_temp); tcg_temp_free(r_temp); r_asi =3D tcg_const_i32(GET_FIELD(insn, 19, 26)); r_size =3D tcg_const_i32(8); @@ -4484,8 +4508,7 @@ static void disas_sparc_insn(DisasContex tcg_temp_free(r_const); r_low =3D tcg_temp_new(TCG_TYPE_TL); gen_movl_reg_TN(rd + 1, r_low); =2D tcg_gen_helper_1_2(helper_pack64, cpu_tmp64, cpu= _val, =2D r_low); + gen_pack64(cpu_tmp64, cpu_val, r_low); tcg_temp_free(r_low); tcg_gen_qemu_st64(cpu_tmp64, cpu_addr, dc->mem_idx= ); }