[Qemu-devel] [PATCH] sh4: mmio based CF support on r2d board.

[yoshii.takashi@gmail.com]

Hi,

This patch adds emulation for a CompactFlash on sh4/r2d board. 
I can mount/umount and some read/writes with r2d-1 kernel (no irq mode).
No heavy/formal test has not be done, though.

The device is CF, but wired to be worked as True-IDE mode, and connected
 directly to SH bus. So, this code is to supports generally mmio based IDEs
 which are supported by "pata_platform" driver in linux kernel.

I wonder where to put function prototype for mmio_ide_init().
Currently, it is in r2d.c, but I believe it can be in more common place.

Any suggestions?

Cheers,
/yoshii

diff --git a/Makefile.target b/Makefile.target
index 88e877f..3844a04 100644
--- a/Makefile.target
+++ b/Makefile.target
@@ -620,6 +620,7 @@ endif
 ifeq ($(TARGET_BASE_ARCH), sh4)
 OBJS+= shix.o r2d.o sh7750.o sh7750_regnames.o tc58128.o
 OBJS+= sh_timer.o ptimer.o sh_serial.o sh_intc.o
+OBJS+= ide.o
 endif
 ifeq ($(TARGET_BASE_ARCH), m68k)
 OBJS+= an5206.o mcf5206.o ptimer.o mcf_uart.o mcf_intc.o mcf5208.o mcf_fec.o
diff --git a/hw/ide.c b/hw/ide.c
index 1e60591..f0e1607 100644
--- a/hw/ide.c
+++ b/hw/ide.c
@@ -3439,6 +3439,95 @@ int pmac_ide_init (BlockDriverState **hd_table, qemu_irq irq)
 }
 
 /***********************************************************/
+/* MMIO based ide port
+ * This emulates IDE device connected directly to the CPU bus without
+ * dedicated ide controller, which is often seen on embedded boards.
+ */
+
+typedef struct {
+    void *dev;
+    int shift;
+} MMIOState;
+
+static uint32_t mmio_ide_read (void *opaque, target_phys_addr_t addr)
+{
+    MMIOState *s = (MMIOState*)opaque;
+    IDEState *ide = (IDEState*)s->dev;
+    addr >>= s->shift;
+    if(addr & 7)
+        return ide_ioport_read(ide, addr);
+    else
+        return ide_data_readw(ide, 0);
+}
+
+static void mmio_ide_write (void *opaque, target_phys_addr_t addr,
+	uint32_t val)
+{
+    MMIOState *s = (MMIOState*)opaque;
+    IDEState *ide = (IDEState*)s->dev;
+    addr >>= s->shift;
+    if(addr & 7)
+        ide_ioport_write(ide, addr, val);
+    else
+        ide_data_writew(ide, 0, val);
+}
+
+static CPUReadMemoryFunc *mmio_ide_reads[] = {
+    mmio_ide_read,
+    mmio_ide_read,
+    mmio_ide_read,
+};
+
+static CPUWriteMemoryFunc *mmio_ide_writes[] = {
+    mmio_ide_write,
+    mmio_ide_write,
+    mmio_ide_write,
+};
+
+static uint32_t mmio_ide_status_read (void *opaque,target_phys_addr_t addr)
+{
+    MMIOState *s= (MMIOState*)opaque;
+    IDEState *ide = (IDEState*)s->dev;
+    return ide_status_read(ide, 0);
+}
+
+static void mmio_ide_cmd_write (void *opaque, target_phys_addr_t addr,
+	uint32_t val)
+{
+    MMIOState *s = (MMIOState*)opaque;
+    IDEState *ide = (IDEState*)s->dev;
+    ide_cmd_write(ide, 0, val);
+}
+
+static CPUReadMemoryFunc *mmio_ide_status[] = {
+    mmio_ide_status_read,
+    mmio_ide_status_read,
+    mmio_ide_status_read,
+};
+
+static CPUWriteMemoryFunc *mmio_ide_cmd[] = {
+    mmio_ide_cmd_write,
+    mmio_ide_cmd_write,
+    mmio_ide_cmd_write,
+};
+
+void mmio_ide_init (int *mmio, BlockDriverState *hd0, BlockDriverState *hd1,
+	qemu_irq irq, int shift)
+{
+    MMIOState *s = qemu_mallocz(sizeof(MMIOState));
+    IDEState *ide = qemu_mallocz(sizeof(IDEState) * 2);
+    int *io;
+
+    ide_init2(ide, hd0, hd1, irq);
+
+    s->dev = ide;
+    s->shift = shift;
+
+    mmio[0] = cpu_register_io_memory(0, mmio_ide_reads, mmio_ide_writes, s);
+    mmio[1] = cpu_register_io_memory(0, mmio_ide_status, mmio_ide_cmd, s);
+}
+
+/***********************************************************/
 /* CF-ATA Microdrive */
 
 #define METADATA_SIZE	0x20
diff --git a/hw/r2d.c b/hw/r2d.c
index a7607d1..d9d43a6 100644
--- a/hw/r2d.c
+++ b/hw/r2d.c
@@ -133,6 +133,10 @@ static void r2d_init(ram_addr_t ram_size, int vga_ram_size,
 {
     CPUState *env;
     struct SH7750State *s;
+    BlockDriverState *cf;
+    int mmio[2];
+    extern void mmio_ide_init (int*, BlockDriverState*, BlockDriverState*,
+        qemu_irq, int);
 
     if (!cpu_model)
         cpu_model = "SH7751R";
@@ -148,6 +152,13 @@ static void r2d_init(ram_addr_t ram_size, int vga_ram_size,
     /* Register peripherals */
     r2d_fpga_init(0x04000000);
     s = sh7750_init(env);
+
+    /* onboard CF (True IDE mode, Primary only). */
+    cf = drives_table[drive_get_index(IF_IDE, 0, 0)].bdrv;
+    mmio_ide_init(mmio, cf, NULL, 0, 1);
+    cpu_register_physical_memory(0x14001000, 0x20, mmio[0]);
+    cpu_register_physical_memory(0x1400080c, 4, mmio[1]);
+
     /* Todo: register on board registers */
     {
       int kernel_size;