From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1KjAhs-0006Kk-53 for qemu-devel@nongnu.org; Fri, 26 Sep 2008 06:37:52 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1KjAhr-0006KL-1T for qemu-devel@nongnu.org; Fri, 26 Sep 2008 06:37:51 -0400 Received: from [199.232.76.173] (port=59076 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1KjAhq-0006KI-RC for qemu-devel@nongnu.org; Fri, 26 Sep 2008 06:37:50 -0400 Received: from pasmtpa.tele.dk ([80.160.77.114]:48816) by monty-python.gnu.org with esmtp (Exim 4.60) (envelope-from ) id 1KjAhq-0006IG-Hc for qemu-devel@nongnu.org; Fri, 26 Sep 2008 06:37:50 -0400 Received: from kernel.dk (brick.kernel.dk [93.163.65.50]) by pasmtpA.tele.dk (Postfix) with ESMTP id 27CAA80043B for ; Fri, 26 Sep 2008 12:37:47 +0200 (CEST) Date: Fri, 26 Sep 2008 12:37:40 +0200 From: Jens Axboe Subject: Re: [Qemu-devel] [5317] Core 2 Duo specification (Alexander Graf). Message-ID: <20080926103739.GX2677@kernel.dk> References: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org On Thu, Sep 25 2008, Andrzej Zaborowski wrote: > Revision: 5317 > http://svn.sv.gnu.org/viewvc/?view=rev&root=qemu&revision=5317 > Author: balrog > Date: 2008-09-25 18:11:30 +0000 (Thu, 25 Sep 2008) > > Log Message: > ----------- > Core 2 Duo specification (Alexander Graf). > > This patch adds a Core 2 Duo CPU to the available CPU types. The CPU > definition tries to resemble a real CPU as good as possible, whilst not > exposing features qemu does not implement. > The patch also includes some minor additions that Core 2 Duo CPUs have: > > - New MSR: MSR_IA32_PERF_STATUS > - CPUID up to level 5 (cache info and mwait) > > Signed-off-by: Alexander Graf > > Modified Paths: > -------------- > trunk/target-i386/cpu.h > trunk/target-i386/helper.c > trunk/target-i386/op_helper.c > > Modified: trunk/target-i386/cpu.h > =================================================================== > --- trunk/target-i386/cpu.h 2008-09-25 18:08:05 UTC (rev 5316) > +++ trunk/target-i386/cpu.h 2008-09-25 18:11:30 UTC (rev 5317) > @@ -242,6 +242,8 @@ > #define MSR_MCG_STATUS 0x17a > #define MSR_MCG_CTL 0x17b > > +#define MSR_IA32_PERF_STATUS 0x198 > + > #define MSR_PAT 0x277 > > #define MSR_EFER 0xc0000080 > @@ -341,6 +343,9 @@ > #define CPUID_VENDOR_AMD_2 0x69746e65 /* "enti" */ > #define CPUID_VENDOR_AMD_3 0x444d4163 /* "cAMD" */ > > +#define CPUID_MWAIT_IBE (1 << 1) /* Interrupts can exit capability */ > +#define CPUID_MWAIT_EMX (0 << 1) /* enumeration supported */ Ehm, should that not be #define CPUID_MWAIT_EMX (1 << 0) -- Jens Axboe