From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1Kp36Z-0002fl-C0 for qemu-devel@nongnu.org; Sun, 12 Oct 2008 11:43:39 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1Kp36Y-0002fJ-Tq for qemu-devel@nongnu.org; Sun, 12 Oct 2008 11:43:39 -0400 Received: from [199.232.76.173] (port=38112 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1Kp36Y-0002f5-FM for qemu-devel@nongnu.org; Sun, 12 Oct 2008 11:43:38 -0400 Received: from mail.codesourcery.com ([65.74.133.4]:39433) by monty-python.gnu.org with esmtps (TLS-1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.60) (envelope-from ) id 1Kp36X-00060t-RV for qemu-devel@nongnu.org; Sun, 12 Oct 2008 11:43:38 -0400 From: Vladimir Prus Date: Sun, 12 Oct 2008 19:43:34 +0400 MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Disposition: inline Message-Id: <200810121943.34699.vladimir@codesourcery.com> Subject: [Qemu-devel] [SH4] Implement MOVUA.L. Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org SH4A has the new MOVUA.L instruction, capable of accessing non-aligned 32-bit data. This patch makes qemu handle it. To the best of my knowledge, from qemu standpoint this is just like ordinary move, no special handling for non-alignment is necessary. - Volodya * target-sh4/translate.c (_decode_opc): Implement MOVUA.L. --- target-sh4/translate.c | 12 ++++++++++++ 1 files changed, 12 insertions(+), 0 deletions(-) diff --git a/target-sh4/translate.c b/target-sh4/translate.c index f279980..43963a8 100644 --- a/target-sh4/translate.c +++ b/target-sh4/translate.c @@ -1520,6 +1520,18 @@ void _decode_opc(DisasContext * ctx) case 0x00c3: /* movca.l R0,@Rm */ tcg_gen_qemu_st32(REG(0), REG(B11_8), ctx->memidx); return; + case 0x40a9: + /* MOVUA.L @Rm,R0 (Rm) -> R0 + Load non-boundary-aligned data */ + tcg_gen_qemu_ld32u(REG(0), REG(B11_8), ctx->memidx); + return; + case 0x40e9: + /* MOVUA.L @Rm+,R0 (Rm) -> R0, Rm + 4 -> Rm + Load non-boundary-aligned + data */ + tcg_gen_qemu_ld32u(REG(0), REG(B11_8), ctx->memidx); + tcg_gen_addi_i32(REG(B11_8), REG(B11_8), 4); + return; case 0x0029: /* movt Rn */ tcg_gen_andi_i32(REG(B11_8), cpu_sr, SR_T); return; -- 1.5.3.5