From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1Kpvp9-000314-Rv for qemu-devel@nongnu.org; Tue, 14 Oct 2008 22:09:19 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1Kpvp9-00030g-8Z for qemu-devel@nongnu.org; Tue, 14 Oct 2008 22:09:19 -0400 Received: from [199.232.76.173] (port=53454 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1Kpvp9-00030c-1u for qemu-devel@nongnu.org; Tue, 14 Oct 2008 22:09:19 -0400 Received: from mail.codesourcery.com ([65.74.133.4]:50089) by monty-python.gnu.org with esmtps (TLS-1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.60) (envelope-from ) id 1Kpvp8-0007B7-P2 for qemu-devel@nongnu.org; Tue, 14 Oct 2008 22:09:19 -0400 Date: Tue, 14 Oct 2008 19:09:16 -0700 From: Nathan Froyd Subject: Re: [Qemu-devel] [PATCH][ppc] convert SPE logical instructions to TCG Message-ID: <20081015020915.GM18389@codesourcery.com> References: <20081014171934.GL18389@codesourcery.com> <20081014191617.GA24989@hall.aurel32.net> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20081014191617.GA24989@hall.aurel32.net> Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org On Tue, Oct 14, 2008 at 09:16:17PM +0200, Aurelien Jarno wrote: > Yes, you should use local variable, cpu_T array will eventually > disappear. However, I am more concerned by the fact that it may not be a > good idea to expand the macro. IMHO you should put the common code in > the macro and pass the name of the function that does the logical > operation as an argument. Done thusly. -Nathan diff -r 5ed4e3fd0fe7 -r cac4af009435 target-ppc/op.c --- a/target-ppc/op.c Tue Oct 14 15:23:35 2008 -0400 +++ b/target-ppc/op.c Tue Oct 14 22:06:28 2008 -0400 @@ -2513,54 +2513,6 @@ RETURN(); } -void OPPROTO op_evand (void) -{ - T0_64 &= T1_64; - RETURN(); -} - -void OPPROTO op_evandc (void) -{ - T0_64 &= ~T1_64; - RETURN(); -} - -void OPPROTO op_evor (void) -{ - T0_64 |= T1_64; - RETURN(); -} - -void OPPROTO op_evxor (void) -{ - T0_64 ^= T1_64; - RETURN(); -} - -void OPPROTO op_eveqv (void) -{ - T0_64 = ~(T0_64 ^ T1_64); - RETURN(); -} - -void OPPROTO op_evnor (void) -{ - T0_64 = ~(T0_64 | T1_64); - RETURN(); -} - -void OPPROTO op_evorc (void) -{ - T0_64 |= ~T1_64; - RETURN(); -} - -void OPPROTO op_evnand (void) -{ - T0_64 = ~(T0_64 & T1_64); - RETURN(); -} - void OPPROTO op_evsrws (void) { do_evsrws(); diff -r 5ed4e3fd0fe7 -r cac4af009435 target-ppc/translate.c --- a/target-ppc/translate.c Tue Oct 14 15:23:35 2008 -0400 +++ b/target-ppc/translate.c Tue Oct 14 22:06:28 2008 -0400 @@ -5427,6 +5427,23 @@ gen_store_gpr64(rD(ctx->opcode), cpu_T64[0]); \ } +#define GEN_SPEOP_TCG_ARITH2(name) \ +static always_inline void gen_##name (DisasContext *ctx) \ +{ \ + if (unlikely(!ctx->spe_enabled)) { \ + GEN_EXCP_NO_AP(ctx); \ + return; \ + } \ + TCGv t0 = tcg_temp_local_new(TCG_TYPE_I64); \ + TCGv t1 = tcg_temp_local_new(TCG_TYPE_I64); \ + gen_load_gpr64(t0, rA(ctx->opcode)); \ + gen_load_gpr64(t1, rB(ctx->opcode)); \ + gen_op_##name(t0, t1); \ + gen_store_gpr64(rD(ctx->opcode), t0); \ + tcg_temp_free(t0); \ + tcg_temp_free(t1); \ +} + #define GEN_SPEOP_ARITH1(name) \ static always_inline void gen_##name (DisasContext *ctx) \ { \ @@ -5453,14 +5470,59 @@ } /* Logical */ -GEN_SPEOP_ARITH2(evand); -GEN_SPEOP_ARITH2(evandc); -GEN_SPEOP_ARITH2(evxor); -GEN_SPEOP_ARITH2(evor); -GEN_SPEOP_ARITH2(evnor); -GEN_SPEOP_ARITH2(eveqv); -GEN_SPEOP_ARITH2(evorc); -GEN_SPEOP_ARITH2(evnand); +static always_inline void gen_op_evand (TCGv t0, TCGv t1) +{ + tcg_gen_and_i64(t0, t0, t1); +} + +static always_inline void gen_op_evandc (TCGv t0, TCGv t1) +{ + tcg_gen_not_i64(t1, t1); + tcg_gen_and_i64(t0, t0, t1); +} + +static always_inline void gen_op_evxor (TCGv t0, TCGv t1) +{ + tcg_gen_xor_i64(t0, t0, t1); +} + +static always_inline void gen_op_evor (TCGv t0, TCGv t1) +{ + tcg_gen_or_i64(t0, t0, t1); +} + +static always_inline void gen_op_evnor (TCGv t0, TCGv t1) +{ + tcg_gen_or_i64(t0, t0, t1); + tcg_gen_not_i64(t0, t0); +} + +static always_inline void gen_op_eveqv (TCGv t0, TCGv t1) +{ + tcg_gen_xor_i64(t0, t0, t1); + tcg_gen_not_i64(t0, t0); +} + +static always_inline void gen_op_evorc (TCGv t0, TCGv t1) +{ + tcg_gen_not_i64(t1, t1); + tcg_gen_or_i64(t0, t0, t1); +} + +static always_inline void gen_op_evnand (TCGv t0, TCGv t1) +{ + tcg_gen_and_i64(t0, t0, t1); + tcg_gen_not_i64(t0, t0); +} + +GEN_SPEOP_TCG_ARITH2(evand); +GEN_SPEOP_TCG_ARITH2(evandc); +GEN_SPEOP_TCG_ARITH2(evxor); +GEN_SPEOP_TCG_ARITH2(evor); +GEN_SPEOP_TCG_ARITH2(evnor); +GEN_SPEOP_TCG_ARITH2(eveqv); +GEN_SPEOP_TCG_ARITH2(evorc); +GEN_SPEOP_TCG_ARITH2(evnand); GEN_SPEOP_ARITH2(evsrwu); GEN_SPEOP_ARITH2(evsrws); GEN_SPEOP_ARITH2(evslw);