From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1Krxb9-0001sz-1A for qemu-devel@nongnu.org; Mon, 20 Oct 2008 12:27:15 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1Krxb5-0001qW-PD for qemu-devel@nongnu.org; Mon, 20 Oct 2008 12:27:14 -0400 Received: from [199.232.76.173] (port=56420 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1Krxb5-0001qT-Ic for qemu-devel@nongnu.org; Mon, 20 Oct 2008 12:27:11 -0400 Received: from mail.codesourcery.com ([65.74.133.4]:41206) by monty-python.gnu.org with esmtps (TLS-1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.60) (envelope-from ) id 1Krxb5-000692-2Y for qemu-devel@nongnu.org; Mon, 20 Oct 2008 12:27:11 -0400 From: Paul Brook Subject: Re: [Qemu-devel] [PATCH] SH: Add prefi, icbi, synco Date: Mon, 20 Oct 2008 17:27:00 +0100 References: <200810171652.46611.vladimir@codesourcery.com> <200810201154.21179.paul@codesourcery.com> <20081020130021.GB20548@linux-sh.org> In-Reply-To: <20081020130021.GB20548@linux-sh.org> MIME-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: 7bit Content-Disposition: inline Message-Id: <200810201727.01042.paul@codesourcery.com> Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Vladimir Prus > > I disagree. This is something that should be done right from the start. > > Trying to fix it up later is a real pain. Doing fine grained features > > isn't that hard. MIPS, sparc, arm, ppc, m68k and sparc already do this. > > IIRC binutils is only complicated because it tried to create a strict > > hieracy of features, rather than using feature bits. > > When we do it does not matter, but it is completely unrelated from this > patch, in that there are already plenty of instructions that are specific > to a certain CPU family that we don't perform an illegal instruction > exception for. Trying to force the prefi/icbi/synco cases to rework all > of the existing instructions that aren't universal doesn't make a lot of > sense, as it is a clear incremental change of existing behaviour, rather > than a situation caused purely by the addition of these new instructions. The only cpu we currently claim to support is SH4. When adding support for other cores these should be properly conditionalized. Unconditionally implementing additional instructions is a regression. I don't consider "we'll fix this at some undefined point in the future" to be a good enough answer. Paul