From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1KrxuC-0006WG-SJ for qemu-devel@nongnu.org; Mon, 20 Oct 2008 12:46:56 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1KrxuB-0006Vp-04 for qemu-devel@nongnu.org; Mon, 20 Oct 2008 12:46:56 -0400 Received: from [199.232.76.173] (port=36822 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1KrxuA-0006Vm-P8 for qemu-devel@nongnu.org; Mon, 20 Oct 2008 12:46:54 -0400 Received: from mail.codesourcery.com ([65.74.133.4]:50732) by monty-python.gnu.org with esmtps (TLS-1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.60) (envelope-from ) id 1KrxuA-0000rc-8e for qemu-devel@nongnu.org; Mon, 20 Oct 2008 12:46:55 -0400 From: Paul Brook Subject: Re: [Qemu-devel] [PATCH] SH: Add prefi, icbi, synco Date: Mon, 20 Oct 2008 17:46:42 +0100 References: <200810171652.46611.vladimir@codesourcery.com> <200810201727.01042.paul@codesourcery.com> <200810202031.19287.vladimir@codesourcery.com> In-Reply-To: <200810202031.19287.vladimir@codesourcery.com> MIME-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: 7bit Content-Disposition: inline Message-Id: <200810201746.43167.paul@codesourcery.com> Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Vladimir Prus Cc: qemu-devel@nongnu.org > > The only cpu we currently claim to support is SH4. When adding support > > for other cores these should be properly conditionalized. > > Unconditionally implementing additional instructions is a regression. I > > don't consider "we'll fix this at some undefined point in the future" to > > be a good enough answer. > > Can you outline what changes should I make to implement proper > conditionalization? You probably want something like ARM arm_feature, MIPS check_insn or SPARC CHECK_*_FEATURE. Paul