From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1KytFe-0006uk-04 for qemu-devel@nongnu.org; Sat, 08 Nov 2008 14:13:42 -0500 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1KytFa-0006tL-CT for qemu-devel@nongnu.org; Sat, 08 Nov 2008 14:13:41 -0500 Received: from [199.232.76.173] (port=41022 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1KytFa-0006tG-5Z for qemu-devel@nongnu.org; Sat, 08 Nov 2008 14:13:38 -0500 Received: from hall.aurel32.net ([88.191.82.174]:47999) by monty-python.gnu.org with esmtps (TLS-1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.60) (envelope-from ) id 1KytFX-0003lO-VU for qemu-devel@nongnu.org; Sat, 08 Nov 2008 14:13:38 -0500 Received: from volta-wlan.aurel32.net ([2002:52e8:2fb:ffff:21d:e0ff:fe49:1047] helo=volta.aurel32.net) by hall.aurel32.net with esmtpsa (TLS-1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.63) (envelope-from ) id 1KytFM-0001ZF-TZ for qemu-devel@nongnu.org; Sat, 08 Nov 2008 20:13:25 +0100 Received: from aurel32 by volta.aurel32.net with local (Exim 4.69) (envelope-from ) id 1KytFL-0005UG-Vy for qemu-devel@nongnu.org; Sat, 08 Nov 2008 20:13:24 +0100 Date: Sat, 8 Nov 2008 20:13:23 +0100 From: Aurelien Jarno Subject: Re: [Qemu-devel] [PATCH 04/11] target-mips: convert bitfield ops to TCG Message-ID: <20081108191323.GA15084@volta.aurel32.net> References: <20081108083118.GB9549@volta.aurel32.net> <20081108083416.GF9549@volta.aurel32.net> <761ea48b0811080457u6c57f1a7tf43c99903bc32d78@mail.gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-15 Content-Disposition: inline In-Reply-To: <761ea48b0811080457u6c57f1a7tf43c99903bc32d78@mail.gmail.com> Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org On Sat, Nov 08, 2008 at 01:57:21PM +0100, Laurent Desnogues wrote: > On Sat, Nov 8, 2008 at 9:34 AM, Aurelien Jarno wrote: > > Bitfield operations can be written with very few TCG instructions > > (between 2 and 5), so it is worth converting them to TCG. > > > > Signed-off-by: Aurelien Jarno > > --- > > target-mips/helper.h | 6 +---- > > target-mips/op_helper.c | 26 +------------------------ > > target-mips/translate.c | 49 +++++++++++++++++++++++++++++++++++++--------- > > 3 files changed, 41 insertions(+), 40 deletions(-) > [...] > > diff --git a/target-mips/translate.c b/target-mips/translate.c > > index af01f73..2cd1868 100644 > > --- a/target-mips/translate.c > > +++ b/target-mips/translate.c > > @@ -2682,57 +2682,86 @@ static void gen_compute_branch (DisasContext *ctx, uint32_t opc, > > static void gen_bitops (DisasContext *ctx, uint32_t opc, int rt, > > int rs, int lsb, int msb) > > { > > - TCGv t0 = tcg_temp_local_new(TCG_TYPE_TL); > > - TCGv t1 = tcg_temp_local_new(TCG_TYPE_TL); > > + TCGv t0 = tcg_temp_new(TCG_TYPE_TL); > > + TCGv t1 = tcg_temp_new(TCG_TYPE_TL); > > + target_ulong mask; > > > > gen_load_gpr(t1, rs); > > switch (opc) { > > case OPC_EXT: > > if (lsb + msb > 31) > > goto fail; > > - tcg_gen_helper_1_1ii(do_ext, t0, t1, lsb, msb + 1); > > + tcg_gen_shri_tl(t0, t1, lsb); > > + if (msb + 1 < 32) { > > Given the above restriction of lsb + msb <= 31, this test can > be rewritten as: > > if (msb != 31) > > I find this more readable, but that's personal taste :-) Fixed. > > + tcg_gen_andi_tl(t0, t0, (1 << (msb + 1)) - 1); > > + } else { > > + tcg_gen_ext32s_tl(t0, t0); > > + } > > break; > > #if defined(TARGET_MIPS64) > > case OPC_DEXTM: > > if (lsb + msb > 63) > > goto fail; > > Can this really happen? lsb and msb are 5 bit wide as far > as I could see. Not it can't. It comes for the previous code, and I forget to "optimize" this part. > > - tcg_gen_helper_1_1ii(do_dext, t0, t1, lsb, msb + 1 + 32); > > + tcg_gen_shri_tl(t0, t1, lsb); > > + if (msb + 1 + 32 < 64) { > > This can be rewritten as > > if (msb != 31) Fixed. > > + tcg_gen_andi_tl(t0, t0, (1ULL << (msb + 1 + 32)) - 1); > > + } > > break; > > case OPC_DEXTU: > > if (lsb + msb > 63) > > goto fail; > > Same as above. Fixed. > > - tcg_gen_helper_1_1ii(do_dext, t0, t1, lsb + 32, msb + 1); > > + tcg_gen_shri_tl(t0, t1, lsb + 32); > > + tcg_gen_andi_tl(t0, t0, (1ULL << (msb + 1)) - 1); > > break; > > case OPC_DEXT: > > if (lsb + msb > 63) > > goto fail; > > Same as above. > Fixed. > > Laurent > > > -- .''`. Aurelien Jarno | GPG: 1024D/F1BCDB73 : :' : Debian developer | Electrical Engineer `. `' aurel32@debian.org | aurelien@aurel32.net `- people.debian.org/~aurel32 | www.aurel32.net