[Qemu-devel] Re: Qemu SH4 status #2

[Qemu-devel] Re: Qemu SH4 status #2

[Kristoffer Ericson]

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On Tue, 11 Nov 2008 14:13:35 +0900
yoshii.takashi@gmail.com wrote:

> Hi,
> > My best guess is that id for whatever reason is tooo
> > high, but thats just my #1 attempt at qemu debugging.
> Yes, but wrong code is in hw/r2d.c. I should not have called mmio_ide_init()
> if no HDD image given. I fixed it but haven't posted the new one yet.
> My code is now like the following,
>     if ((i = drive_get_index(IF_IDE, 0, 0)) != -1)
>         mmio_ide_init(0x14001000, 0x1400080c, irq[CF_IDE], 1,
>                      drives_table[i].bdrv, NULL);
> # I think these mails should go to qemu ML, though.
> /yoshii

I'm still getting segmentation fault at exact same
location. Have you made additional patches?


-- 
Kristoffer Ericson <kristoffer.ericson@gmail.com>

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[Qemu-devel] Re: Qemu SH4 status #2

[yoshii.takashi]

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Hi,

> I'm still getting segmentation fault at exact same
> location. Have you made additional patches?
Please find attached file "qemu081111.diff".
Basically, this is an aggregate of patches found on qemu-devel ML,
 with some conflicts against current svn source being resolved,
 and some small fix are added, which are scheduled to be posted after
 I finished with my pending patches.

I post this to share information between qemu and linux/sh people,
 and hopefully accelerate debugging with linux people's help.

Another file "linuxconfig_r2d_qemu.diff" is diff for linux kernel
 configuretion. It changes following parameters from r2d+'s defconfig.
- Cache -> off (qemu has no cache)
- commandline change (for debugging)
- 8139too -> 8139cp (qemu's default is c+, still thinking how to switch)
- SH SPI -> off (sci emulation is not mature enough to handle it)

Build procedure is as follows,
Configure kernel:
 make ARCH=sh rts7751r2dplus_defconfig
 patch .config < linuxconfig_r2d_qemu.diff
 (and build)

Configure Qemu:
 ./configure --disable-system --target-list=sh4-softmmu \
  --disable-linux-user --disable-kqemu

Execute:
 sh4-softmmu/qemu-system-sh4 -M r2d --serial vc --serial /dev/tty \
  --kernel zImage --append "console=tty0 root=/dev/sda" \
  -usb --usbdevice keyboard --usbdevice mouse disk.img

I've tested it on qemu svn head this morning.
You will see penguin logo, and fbcon input/output working.
For debugging purpose, console=ttySC0,115200 might help.
/yoshii

[-- Attachment #2: qemu081111.diff --]
[-- Type: text/x-patch, Size: 22795 bytes --]

--- svn/target-sh4/helper.c	(revision 5703)
+++ svn/target-sh4/helper.c	(working copy)
@@ -359,14 +359,12 @@
 			   int *prot, target_ulong address,
 			   int rw, int access_type)
 {
-    int use_asid, is_code, n;
+    int use_asid, n;
     tlb_t *matching = NULL;
 
-    use_asid = (env->mmucr & MMUCR_SV) == 0 || (env->sr & SR_MD) == 0;
-    is_code = env->pc == address;	/* Hack */
+    use_asid = (env->mmucr & MMUCR_SV) == 0 || (env->sr & SR_MD) == 0;    
 
-    /* Use a hack to find if this is an instruction or data access */
-    if (env->pc == address && !(rw & PAGE_WRITE)) {
+    if (rw == 2) {
 	n = find_itlb_entry(env, address, use_asid, 1);
 	if (n >= 0) {
 	    matching = &env->itlb[n];
@@ -382,13 +380,13 @@
 	    switch ((matching->pr << 1) | ((env->sr & SR_MD) ? 1 : 0)) {
 	    case 0:		/* 000 */
 	    case 2:		/* 010 */
-		n = (rw & PAGE_WRITE) ? MMU_DTLB_VIOLATION_WRITE :
+	      n = (rw == 1) ? MMU_DTLB_VIOLATION_WRITE :
 		    MMU_DTLB_VIOLATION_READ;
 		break;
 	    case 1:		/* 001 */
 	    case 4:		/* 100 */
 	    case 5:		/* 101 */
-		if (rw & PAGE_WRITE)
+		if (rw == 1)
 		    n = MMU_DTLB_VIOLATION_WRITE;
 		else
 		    *prot = PAGE_READ;
@@ -396,11 +394,11 @@
 	    case 3:		/* 011 */
 	    case 6:		/* 110 */
 	    case 7:		/* 111 */
-		*prot = rw & (PAGE_READ | PAGE_WRITE);
+	        *prot = (rw == 1)? PAGE_WRITE : PAGE_READ;
 		break;
 	    }
 	} else if (n == MMU_DTLB_MISS) {
-	    n = (rw & PAGE_WRITE) ? MMU_DTLB_MISS_WRITE :
+	    n = (rw == 1) ? MMU_DTLB_MISS_WRITE :
 		MMU_DTLB_MISS_READ;
 	}
     }
@@ -426,12 +424,19 @@
 	    && (address < 0xe0000000 || address > 0xe4000000)) {
 	    /* Unauthorized access in user mode (only store queues are available) */
 	    fprintf(stderr, "Unauthorized access\n");
-	    return (rw & PAGE_WRITE) ? MMU_DTLB_MISS_WRITE :
-		MMU_DTLB_MISS_READ;
+	    if (rw == 0)
+	        return MMU_DTLB_MISS_READ;
+	    else if (rw == 1)
+	        return MMU_DTLB_MISS_WRITE;
+	    else
+	        return MMU_ITLB_MISS;
 	}
 	if (address >= 0x80000000 && address < 0xc0000000) {
 	    /* Mask upper 3 bits for P1 and P2 areas */
 	    *physical = address & 0x1fffffff;
+	} else if (address >= 0xfd000000 && address < 0xfe000000) {
+	    /* PCI memory space */
+	    *physical = address;
 	} else if (address >= 0xfc000000) {
 	    /*
 	     * Mask upper 3 bits for control registers in P4 area,
@@ -465,27 +470,6 @@
     target_ulong physical, page_offset, page_size;
     int prot, ret, access_type;
 
-    switch (rw) {
-    case 0:
-        rw = PAGE_READ;
-        break;
-    case 1:
-        rw = PAGE_WRITE;
-        break;
-    case 2: /* READ_ACCESS_TYPE == 2 defined in softmmu_template.h */
-        rw = PAGE_READ;
-        break;
-    default:
-        /* fatal error */
-        assert(0);
-    }
-
-    /* XXXXX */
-#if 0
-    fprintf(stderr, "%s pc %08x ad %08x rw %d mmu_idx %d smmu %d\n",
-	    __func__, env->pc, address, rw, mmu_idx, is_softmmu);
-#endif
-
     access_type = ACCESS_INT;
     ret =
 	get_physical_address(env, &physical, &prot, address, rw,
@@ -537,7 +521,7 @@
     target_ulong physical;
     int prot;
 
-    get_physical_address(env, &physical, &prot, addr, PAGE_READ, 0);
+    get_physical_address(env, &physical, &prot, addr, 0, 0);
     return physical;
 }
 
--- svn/Makefile.target	(revision 5703)
+++ svn/Makefile.target	(working copy)
@@ -736,7 +736,8 @@
 endif
 ifeq ($(TARGET_BASE_ARCH), sh4)
 OBJS+= shix.o r2d.o sh7750.o sh7750_regnames.o tc58128.o
-OBJS+= sh_timer.o ptimer.o sh_serial.o sh_intc.o sm501.o serial.o
+OBJS+= sh_timer.o ptimer.o sh_serial.o sh_intc.o sh_pci.o sm501.o serial.o
+OBJS+= ide.o
 endif
 ifeq ($(TARGET_BASE_ARCH), m68k)
 OBJS+= an5206.o mcf5206.o ptimer.o mcf_uart.o mcf_intc.o mcf5208.o mcf_fec.o
--- svn/hw/r2d.c	(revision 5703)
+++ svn/hw/r2d.c	(working copy)
@@ -28,12 +28,16 @@
 #include "devices.h"
 #include "sysemu.h"
 #include "boards.h"
+#include "pci.h"
+#include "net.h"
+#include "sh7750_regs.h"
 
 #define SDRAM_BASE 0x0c000000 /* Physical location of SDRAM: Area 3 */
 #define SDRAM_SIZE 0x04000000
 
 #define SM501_VRAM_SIZE 0x800000
 
+#define PA_IRLMSK	0x00
 #define PA_POWOFF	0x30
 #define PA_VERREG	0x32
 #define PA_OUTPORT	0x36
@@ -41,6 +45,8 @@
 typedef struct {
     target_phys_addr_t base;
 
+/* register */
+    uint16_t irlmsk;
     uint16_t bcr;
     uint16_t irlmon;
     uint16_t cfctl;
@@ -62,8 +68,53 @@
     uint16_t inport;
     uint16_t outport;
     uint16_t bverreg;
+
+/* output pin */
+    qemu_irq irl;
 } r2d_fpga_t;
 
+enum r2d_fpga_irq {
+    PCI_INTD, CF_IDE, CF_CD, PCI_INTC, SM501, KEY, RTC_A, RTC_T,
+    SDCARD, PCI_INTA, PCI_INTB, EXT, TP,
+    NR_IRQS
+};
+
+static const struct { short irl; uint16_t msk; } irqtab[NR_IRQS] = {
+    [CF_IDE]	= {  1, 1<<9 },
+    [CF_CD]	= {  2, 1<<8 },
+    [PCI_INTA]	= {  9, 1<<14 },
+    [PCI_INTB]	= { 10, 1<<13 },
+    [PCI_INTC]	= {  3, 1<<12 },
+    [PCI_INTD]	= {  0, 1<<11 },
+    [SM501]	= {  4, 1<<10 },
+    [KEY]	= {  5, 1<<6 },
+    [RTC_A]	= {  6, 1<<5 },
+    [RTC_T]	= {  7, 1<<4 },
+    [SDCARD]	= {  8, 1<<7 },
+    [EXT]	= { 11, 1<<0 },
+    [TP]	= { 12, 1<<15 },
+};
+
+static void update_irl(r2d_fpga_t *fpga)
+{
+    int i, irl = 15;
+    for (i = 0; i < NR_IRQS; i++)
+        if (fpga->irlmon & fpga->irlmsk & irqtab[i].msk)
+            if (irqtab[i].irl < irl)
+                irl = irqtab[i].irl;
+    qemu_set_irq(fpga->irl, irl ^ 15);
+}
+
+static void r2d_fpga_irq_set(void *opaque, int n, int level)
+{
+    r2d_fpga_t *fpga = opaque;
+    if (level)
+        fpga->irlmon |= irqtab[n].msk;
+    else
+        fpga->irlmon &= ~irqtab[n].msk;
+    update_irl(fpga);
+}
+
 static uint32_t r2d_fpga_read(void *opaque, target_phys_addr_t addr)
 {
     r2d_fpga_t *s = opaque;
@@ -71,6 +122,8 @@
     addr -= s->base;
 
     switch (addr) {
+    case PA_IRLMSK:
+        return s->irlmsk;
     case PA_OUTPORT:
 	return s->outport;
     case PA_POWOFF:
@@ -90,6 +143,10 @@
     addr -= s->base;
 
     switch (addr) {
+    case PA_IRLMSK:
+        s->irlmsk = value;
+        update_irl(s);
+	break;
     case PA_OUTPORT:
 	s->outport = value;
 	break;
@@ -114,21 +171,35 @@
     NULL,
 };
 
-static void r2d_fpga_init(target_phys_addr_t base)
+static qemu_irq *r2d_fpga_init(target_phys_addr_t base, qemu_irq irl)
 {
     int iomemtype;
     r2d_fpga_t *s;
 
     s = qemu_mallocz(sizeof(r2d_fpga_t));
     if (!s)
-	return;
+	return NULL;
 
+    s->irl = irl;
+
     s->base = base;
     iomemtype = cpu_register_io_memory(0, r2d_fpga_readfn,
 				       r2d_fpga_writefn, s);
     cpu_register_physical_memory(base, 0x40, iomemtype);
+    return qemu_allocate_irqs(r2d_fpga_irq_set, s, NR_IRQS);
 }
 
+static void r2d_pci_set_irq(qemu_irq *p, int n, int l)
+{
+    qemu_set_irq(p[n], l);
+}
+
+static int r2d_pci_map_irq(PCIDevice *d, int irq_num)
+{
+    const int intx[] = { PCI_INTA, PCI_INTB, PCI_INTC, PCI_INTD };
+    return intx[d->devfn>>3];
+}
+
 static void r2d_init(ram_addr_t ram_size, int vga_ram_size,
               const char *boot_device, DisplayState * ds,
 	      const char *kernel_filename, const char *kernel_cmdline,
@@ -137,6 +208,9 @@
     CPUState *env;
     struct SH7750State *s;
     ram_addr_t sdram_addr, sm501_vga_ram_addr;
+    qemu_irq *irq;
+    PCIBus *pci;
+    int i;
 
     if (!cpu_model)
         cpu_model = "SH7751R";
@@ -151,23 +225,50 @@
     sdram_addr = qemu_ram_alloc(SDRAM_SIZE);
     cpu_register_physical_memory(SDRAM_BASE, SDRAM_SIZE, sdram_addr);
     /* Register peripherals */
-    r2d_fpga_init(0x04000000);
     s = sh7750_init(env);
+    irq = r2d_fpga_init(0x04000000, sh7750_irl(s));
+
     sm501_vga_ram_addr = qemu_ram_alloc(SM501_VRAM_SIZE);
     sm501_init(ds, 0x10000000, sm501_vga_ram_addr, SM501_VRAM_SIZE,
 	       serial_hds[2]);
+
+    /* onboard CF (True IDE mode, Master only). */
+    if ((i = drive_get_index(IF_IDE, 0, 0)) != -1)
+        mmio_ide_init(0x14001000, 0x1400080c, irq[CF_IDE], 1,
+                      drives_table[i].bdrv, NULL);
+
+    /* PCI host and peripherals */
+    pci = sh_pci_register_bus(r2d_pci_set_irq, r2d_pci_map_irq, irq, 0, 4);
+
+    /* NIC: rtl8139 on-board, and 2 slots. */
+    if (nb_nics)
+        pci_rtl8139_init(pci, &nd_table[0], 2<<3);
+    for (i = 1; i < nb_nics; i++)
+        pci_nic_init(pci, &nd_table[i], -1);
+    /* USB OHCI for keyboard & mouse */
+    if (usb_enabled)
+        usb_ohci_init_pci(pci, 4, -1);
     /* Todo: register on board registers */
-    {
+    if (kernel_filename) {
       int kernel_size;
+      /* initialization which should be done by firmware */
+      uint32_t bcr1 = 1<<3; // cs3 SDRAM
+      uint16_t bcr2 = 3<<(3*2); // cs3 32bit
+      cpu_physical_memory_write(SH7750_BCR1_A7,&bcr1,4);
+      cpu_physical_memory_write(SH7750_BCR2_A7,&bcr2,2);
 
-      kernel_size = load_image(kernel_filename, phys_ram_base);
-
+      if (kernel_cmdline) {
+          kernel_size = load_image(kernel_filename, phys_ram_base + 0x80000);
+          env->pc = (SDRAM_BASE + 0x80000) | 0xa0000000;
+          pstrcpy(phys_ram_base + 0x10100, 256, kernel_cmdline);
+      } else {
+          kernel_size = load_image(kernel_filename, phys_ram_base);
+          env->pc = SDRAM_BASE | 0xa0000000; /* Start from P2 area */
+      }
       if (kernel_size < 0) {
         fprintf(stderr, "qemu: could not load kernel '%s'\n", kernel_filename);
         exit(1);
       }
-
-      env->pc = SDRAM_BASE | 0xa0000000; /* Start from P2 area */
     }
 }
 
--- svn/hw/sh_pci.c	(revision 0)
+++ svn/hw/sh_pci.c	(revision 0)
@@ -0,0 +1,207 @@
+/*
+ * SuperH on-chip PCIC emulation.	
+ *
+ * Copyright (c) 2008 Takashi YOSHII
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+#include "hw.h"
+#include "sh.h"
+#include "pci.h"
+#include "bswap.h"
+
+typedef struct {
+    PCIBus *bus;
+    PCIDevice *dev;
+    uint32_t regbase;
+    uint32_t iopbase;
+    uint32_t membase;
+    uint32_t par;
+    uint32_t mbr;
+    uint32_t iobr;
+} SHPCIC;
+
+static void sh_pci_reg_write (void *p, target_phys_addr_t addr, uint32_t val)
+{
+    SHPCIC *pcic = p;
+    addr -= pcic->regbase;
+    switch(addr) {
+      case 0 ... 0xfc:
+        cpu_to_le32w((uint32_t*)(pcic->dev->config + addr), val);
+        break;
+      case 0x1c0:
+        pcic->par = val;
+        break;
+      case 0x1c4:
+        pcic->mbr = val;
+        break;
+      case 0x1c8:
+        pcic->iobr = val;
+        break;
+      case 0x220:
+        pci_data_write(pcic->bus, pcic->par, val, 4);
+        break;
+    }
+}
+
+static uint32_t sh_pci_reg_read (void *p, target_phys_addr_t addr)
+{
+    SHPCIC *pcic = p;
+    addr -= pcic->regbase;
+    switch(addr) {
+      case 0 ... 0xfc:
+        return le32_to_cpup((uint32_t*)(pcic->dev->config + addr));
+      case 0x1c0:
+        return pcic->par;
+      case 0x220:
+        return pci_data_read(pcic->bus, pcic->par, 4);
+    }
+    return 0;
+}
+
+static void sh_pci_data_write (SHPCIC *pcic, target_phys_addr_t addr,
+                               uint32_t val, int size)
+{
+    pci_data_write(pcic->bus, addr - pcic->membase + pcic->mbr, val, size);
+}
+
+static uint32_t sh_pci_mem_read (SHPCIC *pcic, target_phys_addr_t addr,
+                                 int size)
+{
+    return pci_data_read(pcic->bus, addr - pcic->membase + pcic->mbr, size);
+}
+
+static void sh_pci_writeb (void *p, target_phys_addr_t addr, uint32_t val)
+{
+    sh_pci_data_write(p, addr, val, 1);
+}
+
+static void sh_pci_writew (void *p, target_phys_addr_t addr, uint32_t val)
+{
+    sh_pci_data_write(p, addr, val, 2);
+}
+
+static void sh_pci_writel (void *p, target_phys_addr_t addr, uint32_t val)
+{
+    sh_pci_data_write(p, addr, val, 4);
+}
+
+static uint32_t sh_pci_readb (void *p, target_phys_addr_t addr)
+{
+    return sh_pci_mem_read(p, addr, 1);
+}
+
+static uint32_t sh_pci_readw (void *p, target_phys_addr_t addr)
+{
+    return sh_pci_mem_read(p, addr, 2);
+}
+
+static uint32_t sh_pci_readl (void *p, target_phys_addr_t addr)
+{
+    return sh_pci_mem_read(p, addr, 4);
+}
+
+static int sh_pci_addr2port(SHPCIC *pcic, target_phys_addr_t addr)
+{
+    return addr - pcic->iopbase + pcic->iobr;
+}
+
+static void sh_pci_outb (void *p, target_phys_addr_t addr, uint32_t val)
+{
+    cpu_outb(NULL, sh_pci_addr2port(p, addr), val);
+}
+
+static void sh_pci_outw (void *p, target_phys_addr_t addr, uint32_t val)
+{
+    cpu_outw(NULL, sh_pci_addr2port(p, addr), val);
+}
+
+static void sh_pci_outl (void *p, target_phys_addr_t addr, uint32_t val)
+{
+    cpu_outl(NULL, sh_pci_addr2port(p, addr), val);
+}
+
+static uint32_t sh_pci_inb (void *p, target_phys_addr_t addr)
+{
+    return cpu_inb(NULL, sh_pci_addr2port(p, addr));
+}
+
+static uint32_t sh_pci_inw (void *p, target_phys_addr_t addr)
+{
+    return cpu_inw(NULL, sh_pci_addr2port(p, addr));
+}
+
+static uint32_t sh_pci_inl (void *p, target_phys_addr_t addr)
+{
+    return cpu_inl(NULL, sh_pci_addr2port(p, addr));
+}
+
+typedef struct {
+    CPUReadMemoryFunc *r[3];
+    CPUWriteMemoryFunc *w[3];
+} MemOp;
+
+static MemOp sh_pci_reg = {
+    { NULL, NULL, sh_pci_reg_read },
+    { NULL, NULL, sh_pci_reg_write },
+};
+
+static MemOp sh_pci_mem = {
+    { sh_pci_readb, sh_pci_readw, sh_pci_readl },
+    { sh_pci_writeb, sh_pci_writew, sh_pci_writel },
+};
+
+static MemOp sh_pci_iop = {
+    { sh_pci_inb, sh_pci_inw, sh_pci_inl },
+    { sh_pci_outb, sh_pci_outw, sh_pci_outl },
+};
+
+PCIBus *sh_pci_register_bus(pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
+                            qemu_irq *pic, int devfn_min, int nirq)
+{
+    SHPCIC *p;
+    int mem, reg, iop;
+
+    p = qemu_mallocz(sizeof(SHPCIC));
+    p->bus = pci_register_bus(set_irq, map_irq, pic, devfn_min, nirq);
+
+    p->dev = pci_register_device(p->bus, "SH PCIC", sizeof(PCIDevice),
+                                 -1, NULL, NULL);
+    p->regbase = 0x1e200000;
+    p->iopbase = 0x1e240000;
+    p->membase = 0xfd000000;
+    reg = cpu_register_io_memory(0, sh_pci_reg.r, sh_pci_reg.w, p);
+    mem = cpu_register_io_memory(0, sh_pci_mem.r, sh_pci_mem.w, p);
+    iop = cpu_register_io_memory(0, sh_pci_iop.r, sh_pci_iop.w, p);
+    cpu_register_physical_memory(p->regbase, 0x224, reg);
+    cpu_register_physical_memory(p->iopbase, 0x40000, iop);
+    cpu_register_physical_memory(p->membase, 0x1000000, mem);
+
+    p->dev->config[0x00] = 0x54; // HITACHI
+    p->dev->config[0x01] = 0x10; //
+    p->dev->config[0x02] = 0x0e; // SH7751R
+    p->dev->config[0x03] = 0x35; //
+    p->dev->config[0x04] = 0x80;
+    p->dev->config[0x05] = 0x00;
+    p->dev->config[0x06] = 0x90;
+    p->dev->config[0x07] = 0x02;
+
+    return p->bus;
+}
+
--- svn/hw/sh.h	(revision 5703)
+++ svn/hw/sh.h	(working copy)
@@ -42,7 +42,14 @@
 		     struct intc_source *tei_source,
 		     struct intc_source *bri_source);
 
+/* sh7750.c */
+qemu_irq sh7750_irl(struct SH7750State *s);
+
 /* tc58128.c */
 int tc58128_init(struct SH7750State *s, const char *zone1, const char *zone2);
 
+/* ide.c */
+void mmio_ide_init(target_phys_addr_t membase, target_phys_addr_t membase2,
+                   qemu_irq irq, int shift,
+                   BlockDriverState *hd0, BlockDriverState *hd1);
 #endif
--- svn/hw/sh7750.c	(revision 5703)
+++ svn/hw/sh7750.c	(working copy)
@@ -41,6 +41,8 @@
     /* Peripheral frequency in Hz */
     uint32_t periph_freq;
     /* SDRAM controller */
+    uint32_t bcr1;
+    uint32_t bcr2;
     uint16_t rfcr;
     /* IO ports */
     uint16_t gpioic;
@@ -208,6 +210,8 @@
     SH7750State *s = opaque;
 
     switch (addr) {
+    case SH7750_BCR2_A7:
+	return s->bcr2;
     case SH7750_FRQCR_A7:
 	return 0;
     case SH7750_RFCR_A7:
@@ -231,6 +235,15 @@
     SH7750State *s = opaque;
 
     switch (addr) {
+    case SH7750_BCR1_A7:
+	return s->bcr1;
+    case SH7750_BCR4_A7:
+    case SH7750_WCR1_A7:
+    case SH7750_WCR2_A7:
+    case SH7750_WCR3_A7:
+    case SH7750_MCR_A7:
+	ignore_access("long read", addr);
+	return 0;
     case SH7750_MMUCR_A7:
 	return s->cpu->mmucr;
     case SH7750_PTEH_A7:
@@ -285,6 +298,8 @@
     switch (addr) {
 	/* SDRAM controller */
     case SH7750_BCR2_A7:
+	s->bcr2 = mem_value;
+	return;
     case SH7750_BCR3_A7:
     case SH7750_RTCOR_A7:
     case SH7750_RTCNT_A7:
@@ -331,6 +346,8 @@
     switch (addr) {
 	/* SDRAM controller */
     case SH7750_BCR1_A7:
+	s->bcr1 = mem_value;
+        return;
     case SH7750_BCR4_A7:
     case SH7750_WCR1_A7:
     case SH7750_WCR2_A7:
@@ -412,7 +429,9 @@
 	UNUSED = 0,
 
 	/* interrupt sources */
-	IRL0, IRL1, IRL2, IRL3, /* only IRLM mode supported */
+	IRL_0, IRL_1, IRL_2, IRL_3, IRL_4, IRL_5, IRL_6, IRL_7,
+	IRL_8, IRL_9, IRL_A, IRL_B, IRL_C, IRL_D, IRL_E,
+	IRL0, IRL1, IRL2, IRL3,
 	HUDI, GPIOI,
 	DMAC_DMTE0, DMAC_DMTE1, DMAC_DMTE2, DMAC_DMTE3,
 	DMAC_DMTE4, DMAC_DMTE5, DMAC_DMTE6, DMAC_DMTE7,
@@ -428,6 +447,8 @@
 
 	/* interrupt groups */
 	DMAC, PCIC1, TMU2, RTC, SCI1, SCIF, REF,
+	/* irl bundle */
+	IRL,
 
 	NR_SOURCES,
 };
@@ -529,6 +550,29 @@
 		   PCIC1_PCIDMA0, PCIC1_PCIDMA1, PCIC1_PCIDMA2, PCIC1_PCIDMA3),
 };
 
+static struct intc_vect vectors_irl[] = {
+	INTC_VECT(IRL_0, 0x200),
+	INTC_VECT(IRL_1, 0x220),
+	INTC_VECT(IRL_2, 0x240),
+	INTC_VECT(IRL_3, 0x260),
+	INTC_VECT(IRL_4, 0x280),
+	INTC_VECT(IRL_5, 0x2a0),
+	INTC_VECT(IRL_6, 0x2c0),
+	INTC_VECT(IRL_7, 0x2e0),
+	INTC_VECT(IRL_8, 0x300),
+	INTC_VECT(IRL_9, 0x320),
+	INTC_VECT(IRL_A, 0x340),
+	INTC_VECT(IRL_B, 0x360),
+	INTC_VECT(IRL_C, 0x380),
+	INTC_VECT(IRL_D, 0x3a0),
+	INTC_VECT(IRL_E, 0x3c0),
+};
+
+static struct intc_group groups_irl[] = {
+	INTC_GROUP(IRL, IRL_0, IRL_1, IRL_2, IRL_3, IRL_4, IRL_5, IRL_6,
+		IRL_7, IRL_8, IRL_9, IRL_A, IRL_B, IRL_C, IRL_D, IRL_E),
+};
+
 /**********************************************************************
  Memory mapped cache and TLB
 **********************************************************************/
@@ -717,5 +761,16 @@
 				 NULL, 0);
     }
 
+    sh_intc_register_sources(&s->intc,
+				_INTC_ARRAY(vectors_irl),
+				_INTC_ARRAY(groups_irl));
     return s;
 }
+
+qemu_irq sh7750_irl(SH7750State *s)
+{
+    sh_intc_toggle_source(sh_intc_source(&s->intc, IRL), 1, 0); /* enable */
+    return qemu_allocate_irqs(sh_intc_set_irl, sh_intc_source(&s->intc, IRL),
+                               1)[0];
+}
+
--- svn/hw/ide.c	(revision 5703)
+++ svn/hw/ide.c	(working copy)
@@ -3512,6 +3512,98 @@
 }
 
 /***********************************************************/
+/* MMIO based ide port
+ * This emulates IDE device connected directly to the CPU bus without
+ * dedicated ide controller, which is often seen on embedded boards.
+ */
+
+typedef struct {
+    void *dev;
+    int shift;
+} MMIOState;
+
+static uint32_t mmio_ide_read (void *opaque, target_phys_addr_t addr)
+{
+    MMIOState *s = (MMIOState*)opaque;
+    IDEState *ide = (IDEState*)s->dev;
+    addr >>= s->shift;
+    if (addr & 7)
+        return ide_ioport_read(ide, addr);
+    else
+        return ide_data_readw(ide, 0);
+}
+
+static void mmio_ide_write (void *opaque, target_phys_addr_t addr,
+	uint32_t val)
+{
+    MMIOState *s = (MMIOState*)opaque;
+    IDEState *ide = (IDEState*)s->dev;
+    addr >>= s->shift;
+    if (addr & 7)
+        ide_ioport_write(ide, addr, val);
+    else
+        ide_data_writew(ide, 0, val);
+}
+
+static CPUReadMemoryFunc *mmio_ide_reads[] = {
+    mmio_ide_read,
+    mmio_ide_read,
+    mmio_ide_read,
+};
+
+static CPUWriteMemoryFunc *mmio_ide_writes[] = {
+    mmio_ide_write,
+    mmio_ide_write,
+    mmio_ide_write,
+};
+
+static uint32_t mmio_ide_status_read (void *opaque, target_phys_addr_t addr)
+{
+    MMIOState *s= (MMIOState*)opaque;
+    IDEState *ide = (IDEState*)s->dev;
+    return ide_status_read(ide, 0);
+}
+
+static void mmio_ide_cmd_write (void *opaque, target_phys_addr_t addr,
+	uint32_t val)
+{
+    MMIOState *s = (MMIOState*)opaque;
+    IDEState *ide = (IDEState*)s->dev;
+    ide_cmd_write(ide, 0, val);
+}
+
+static CPUReadMemoryFunc *mmio_ide_status[] = {
+    mmio_ide_status_read,
+    mmio_ide_status_read,
+    mmio_ide_status_read,
+};
+
+static CPUWriteMemoryFunc *mmio_ide_cmd[] = {
+    mmio_ide_cmd_write,
+    mmio_ide_cmd_write,
+    mmio_ide_cmd_write,
+};
+
+void mmio_ide_init (target_phys_addr_t membase, target_phys_addr_t membase2, 
+	            qemu_irq irq, int shift,
+                    BlockDriverState *hd0, BlockDriverState *hd1)
+{
+    MMIOState *s = qemu_mallocz(sizeof(MMIOState));
+    IDEState *ide = qemu_mallocz(sizeof(IDEState) * 2);
+    int mem1, mem2;
+
+    ide_init2(ide, hd0, hd1, irq);
+
+    s->dev = ide;
+    s->shift = shift;
+
+    mem1 = cpu_register_io_memory(0, mmio_ide_reads, mmio_ide_writes, s);
+    mem2 = cpu_register_io_memory(0, mmio_ide_status, mmio_ide_cmd, s);
+    cpu_register_physical_memory(membase, 16<<shift, mem1);
+    cpu_register_physical_memory(membase2, 2<<shift, mem2);
+}
+
+/***********************************************************/
 /* CF-ATA Microdrive */
 
 #define METADATA_SIZE	0x20
--- svn/hw/sh_intc.c	(revision 5703)
+++ svn/hw/sh_intc.c	(working copy)
@@ -451,3 +451,18 @@
 
     return 0;
 }
+
+/* Assert level <n> IRL interrupt. 
+   0:deassert. 1:lowest priority,... 15:highest priority. */
+void sh_intc_set_irl(void *opaque, int n, int level)
+{
+    struct intc_source *s = opaque;
+    int i, irl = level ^ 15;
+    for (i = 0; (s = sh_intc_source(s->parent, s->next_enum_id)); i++) {
+	if (i == irl)
+	    sh_intc_toggle_source(s, s->enable_count?0:1, s->asserted?0:1);
+	else
+	    if (s->asserted)
+	        sh_intc_toggle_source(s, 0, -1);
+    }
+}
--- svn/hw/sh_intc.h	(revision 5703)
+++ svn/hw/sh_intc.h	(working copy)
@@ -72,4 +72,6 @@
 		 struct intc_prio_reg *prio_regs,
 		 int nr_prio_regs);
 
+void sh_intc_set_irl(void *opaque, int n, int level);
+
 #endif /* __SH_INTC_H__ */

[-- Attachment #3: linuxconfig_r2d_qemu.diff --]
[-- Type: text/x-patch, Size: 1150 bytes --]

--- arch/sh/configs/rts7751r2dplus_defconfig	2008-11-11 16:18:39.000000000 +0900
+++ .config	2008-11-12 13:09:59.000000000 +0900
@@ -197,9 +197,9 @@
 # Cache configuration
 #
 # CONFIG_SH_DIRECT_MAPPED is not set
-CONFIG_CACHE_WRITEBACK=y
+# CONFIG_CACHE_WRITEBACK is not set
 # CONFIG_CACHE_WRITETHROUGH is not set
-# CONFIG_CACHE_OFF is not set
+CONFIG_CACHE_OFF=y
 
 #
 # Processor features
@@ -283,8 +283,7 @@
 CONFIG_ZERO_PAGE_OFFSET=0x00010000
 CONFIG_BOOT_LINK_OFFSET=0x00800000
 # CONFIG_UBC_WAKEUP is not set
-CONFIG_CMDLINE_BOOL=y
-CONFIG_CMDLINE="console=tty0 console=ttySC0,115200 root=/dev/sda1 earlyprintk=serial"
+# CONFIG_CMDLINE_BOOL is not set
 
 #
 # Bus options
@@ -613,8 +612,8 @@
 # CONFIG_FEALNX is not set
 # CONFIG_NATSEMI is not set
 # CONFIG_NE2K_PCI is not set
-# CONFIG_8139CP is not set
-CONFIG_8139TOO=y
+CONFIG_8139CP=y
+# CONFIG_8139TOO is not set
 # CONFIG_8139TOO_PIO is not set
 # CONFIG_8139TOO_TUNE_TWISTER is not set
 # CONFIG_8139TOO_8129 is not set
@@ -772,7 +772,7 @@
 # SPI Master Controller Drivers
 #
 CONFIG_SPI_BITBANG=y
-CONFIG_SPI_SH_SCI=y
+# CONFIG_SPI_SH_SCI is not set
 
 #
 # SPI Protocol Masters

[Qemu-devel] Re: Qemu SH4 status #2

[Paul Mundt]

On Wed, Nov 12, 2008 at 01:33:13PM +0900, yoshii.takashi@gmail.com wrote:
> Hi,
> 
> > I'm still getting segmentation fault at exact same
> > location. Have you made additional patches?
> Please find attached file "qemu081111.diff".
> Basically, this is an aggregate of patches found on qemu-devel ML,
>  with some conflicts against current svn source being resolved,
>  and some small fix are added, which are scheduled to be posted after
>  I finished with my pending patches.
> 
> I post this to share information between qemu and linux/sh people,
>  and hopefully accelerate debugging with linux people's help.
> 
> Another file "linuxconfig_r2d_qemu.diff" is diff for linux kernel
>  configuretion. It changes following parameters from r2d+'s defconfig.
> - Cache -> off (qemu has no cache)
> - commandline change (for debugging)
> - 8139too -> 8139cp (qemu's default is c+, still thinking how to switch)
> - SH SPI -> off (sci emulation is not mature enough to handle it)
> 
This is precisely what rts7751r2dplus_qemu_defconfig is for. Please patch
that instead, as new features are added.

[Qemu-devel] Re: Qemu SH4 status #2

[Kristoffer Ericson]

[-- Attachment #1: Type: text/plain, Size: 1787 bytes --]

On Wed, 12 Nov 2008 13:33:13 +0900
yoshii.takashi@gmail.com wrote:

> Hi,
> 
> > I'm still getting segmentation fault at exact same
> > location. Have you made additional patches?
> Please find attached file "qemu081111.diff".
> Basically, this is an aggregate of patches found on qemu-devel ML,
>  with some conflicts against current svn source being resolved,
>  and some small fix are added, which are scheduled to be posted after
>  I finished with my pending patches.
> 
> I post this to share information between qemu and linux/sh people,
>  and hopefully accelerate debugging with linux people's help.
> 

I will give it a try later today. Big thx!

> Another file "linuxconfig_r2d_qemu.diff" is diff for linux kernel
>  configuretion. It changes following parameters from r2d+'s defconfig.
> - Cache -> off (qemu has no cache)
> - commandline change (for debugging)
> - 8139too -> 8139cp (qemu's default is c+, still thinking how to switch)
> - SH SPI -> off (sci emulation is not mature enough to handle it)
> 
> Build procedure is as follows,
> Configure kernel:
>  make ARCH=sh rts7751r2dplus_defconfig
>  patch .config < linuxconfig_r2d_qemu.diff
>  (and build)
> 
> Configure Qemu:
>  ./configure --disable-system --target-list=sh4-softmmu \
>   --disable-linux-user --disable-kqemu
> 
> Execute:
>  sh4-softmmu/qemu-system-sh4 -M r2d --serial vc --serial /dev/tty \
>   --kernel zImage --append "console=tty0 root=/dev/sda" \
>   -usb --usbdevice keyboard --usbdevice mouse disk.img
> 
> I've tested it on qemu svn head this morning.
> You will see penguin logo, and fbcon input/output working.
> For debugging purpose, console=ttySC0,115200 might help.
> /yoshii
> 


-- 
Kristoffer Ericson <kristoffer.ericson@gmail.com>

[-- Attachment #2: Type: application/pgp-signature, Size: 197 bytes --]

[Qemu-devel] Re: Qemu SH4 status #2

[Kristoffer Ericson]

[-- Attachment #1: Type: text/plain, Size: 15729 bytes --]

Still not working properly for me, but might be due
to my .img file since it complains about the partitioning.

Anyhow this is what I get:
[kristoffer@BoTux qemu-land]$ qemu-system-sh4 -M r2d --serial vc --serial /dev/tty -kernel zImage_3 --append "console=ttySC0,115200 root=/dev/sda" -usb --usbdevice keyboard --usbdevice mouse qemu-sh3-img.img 
long read to SH7750_WCR1_A7 (0x1f800008) ignored
long read to SH7750_WCR2_A7 (0x1f80000c) ignored
long read to SH7750_WCR3_A7 (0x1f800010) ignored
long read to SH7750_MCR_A7 (0x1f800014) ignored
long read to SH7750_MCR_A7 (0x1f800014) ignored
Linux version 2.6.27-hpc-00015-g56be9ec-dirty (kristoffer@BoTux) (gcc version 3.4.5) #9 Wed Nov 12 17:39:55 CET 2008
Boot params:
... MOUNT_ROOT_RDONLY - 00000000
... RAMDISK_FLAGS     - 00000000
... ORIG_ROOT_DEV     - 00000000
... LOADER_TYPE       - 00000000
... INITRD_START      - 00000000
... INITRD_SIZE       - 00000000
Booting machvec: RTS7751R2D
Renesas Technology Sales RTS7751R2D support.
FPGA version:1 (revision:0)
Node 0: start_pfn = 0xc000, low = 0x10000
Zone PFN ranges:
  Normal   0x0000c000 -> 0x00010000
Movable zone start PFN for each node
early_node_map[1] active PFN ranges
    0: 0x0000c000 -> 0x00010000
Built 1 zonelists in Zone order, mobility grouping on.  Total pages: 16256
Kernel command line: console=ttySC0,115200 root=/dev/sda
Using R2D-PLUS interrupt controller.
PID hash table entries: 256 (order: 8, 1024 bytes)
Using tmu for system timer
Using 15.000 MHz high precision timer.
Console: colour dummy device 80x25
Dentry cache hash table entries: 8192 (order: 3, 32768 bytes)
Inode-cache hash table entries: 4096 (order: 2, 16384 bytes)
Memory: 61896k/65536k available (2129k kernel code, 605k data, 112k init)
Calibrating delay loop... 86.27 BogoMIPS (lpj=172544)
Mount-cache hash table entries: 512
CPU: SH7751R
net_namespace: 288 bytes
NET: Registered protocol family 16
SCSI subsystem initialized
usbcore: registered new interface driver usbfs
usbcore: registered new interface driver hub
usbcore: registered new device driver usb
Autoconfig PCI channel 0x8c2b723c
Scanning bus 00, I/O 0x00004000:0x00040000, Mem 0xfd000000:0xfe000000
00:00.0 Class 0000: 1054:350e
00:01.0 Class 0c03: 106b:003f
        Mem at 0xfd000000 [size=0x100]
00:02.0 Class 0200: 10ec:8139 (rev 20)
        I/O at 0x00004000 [size=0x100]
        Mem at 0xfd000100 [size=0x100]
PCI: Using configuration type 1
NET: Registered protocol family 2
IP route cache hash table entries: 1024 (order: 0, 4096 bytes)
TCP established hash table entries: 2048 (order: 2, 16384 bytes)
TCP bind hash table entries: 2048 (order: 1, 8192 bytes)
TCP: Hash tables configured (established 2048 bind 2048)
TCP reno registered
NET: Registered protocol family 1
trapped io 0xc0000000 overrides mmio 0xb4001000
trapped io 0xc0001000 overrides mmio 0xb400080c
msgmni has been set to 121
io scheduler noop registered
io scheduler anticipatory registered (default)
io scheduler deadline registered
io scheduler cfq registered
pci_hotplug: PCI Hot Plug PCI Core version: 0.5
Serial: 8250/16550 driver4 ports, IRQ sharing disabled
SuperH SCI(F) driver initialized
sh-sci: ttySC0 at MMIO 0xffe80000 (irq = 43) is a scif
console [ttySC0] enabled
brd: module loaded
sm501 sm501: SM501 At b3e00000: Version 050100a0, 8 Mb, IRQ 100
sm501-usb[0] flags 00000200: 13e40000..13e5ffff
sm501-usb[1] flags 00000200: 107c0000..107fffff
sm501-usb[2] flags 00000400: 00000064..00000064
sm501-fb[0] flags 00000200: 13e80000..13e8ffff
sm501-fb[1] flags 00000200: 13f00000..13f4ffff
sm501-fb[2] flags 00000200: 10000000..107bffff
sm501-fb[3] flags 00000400: 00000064..00000064
sm501-fb sm501-fb: fb sm501fb-crt disabled at start
sm501 sm501: gate 00021807, clock 2a090a09, mode 00000000
sm501 sm501: gate 00021807, clock 2a090a09, mode 00000001
Console: switching to colour frame buffer device 80x25
sm501-fb sm501-fb: fb0: sm501fb-crt frame buffer
sm501-fb sm501-fb: fb sm501fb-panel disabled at start
sm501-fb sm501-fb: using supplied mode
sm501 sm501: gate 00021807, clock 291a0a09, mode 00000000
sm501-fb sm501-fb: fb1: sm501fb-panel frame buffer
8139cp: 10/100 PCI Ethernet driver v1.3 (Mar 22, 2004)
eth0: RTL-8139C+ at 0xfd000100, 52:54:00:12:34:56, IRQ 112
Driver 'sd' needs updating - please use bus_type methods
scsi0 : pata_platform
ata1: PATA max PIO0 mmio cmd 0xb4001000 ctl 0xb400080c irq 107
ata1.00: ATA-7: QEMU HARDDISK, 0.9.1, max UDMA/100
ata1.00: 40000 sectors, multi 16: LBA48 
ata1.00: configured for PIO
scsi 0:0:0:0: Direct-Access     ATA      QEMU HARDDISK    0.9. PQ: 0 ANSI: 5
sd 0:0:0:0: [sda] 40000 512-byte hardware sectors (20 MB)
sd 0:0:0:0: [sda] Write Protect is off
sd 0:0:0:0: [sda] Write cache: disabled, read cache: enabled, doesn't support DPO or FUA
sd 0:0:0:0: [sda] 40000 512-byte hardware sectors (20 MB)
sd 0:0:0:0: [sda] Write Protect is off
sd 0:0:0:0: [sda] Write cache: disabled, read cache: enabled, doesn't support DPO or FUA
 sda: unknown partition table
sd 0:0:0:0: [sda] Attached SCSI disk
ohci_hcd 0000:00:01.0: OHCI Host Controller
ohci_hcd 0000:00:01.0: new USB bus registered, assigned bus number 1
ohci_hcd 0000:00:01.0: irq 111, io mem 0xfd000000
usb usb1: configuration #1 chosen from 1 choice
hub 1-0:1.0: USB hub found
hub 1-0:1.0: 4 ports detected
irq 111: nobody cared (try booting with the "irqpoll" option)
Stack: (0x8f819948 to 0x8f81a000)
9940:                   8c04c5c0 0000006f 8c2a9350 8c04c84a 0000001a 0000006f 
9960: 00000000 0000000a 0000006f 8c04d20a 00000000 8c2deba0 0000000a 8c2e1270 
9980: 0000001a 0000006f 8c2a9350 8c012752 8f819a3c 8c2e2a4c 8c0170e0 00000001 
99a0: 8c012720 ffffffff 00000001 8c02ef40 40008000 8f818000 8c2debd8 00000c2d 
99c0: 00002000 000000f0 00000000 8c2debdc 00000001 8c2e1270 0000000a 8c2deba0 
99e0: 00000000 8f819a08 8c02ef40 8c02a79a 40008001 00000000 00010a8b 00001848 
9a00: ffffffff ffffffff 8c02a8a6 00000000 00000000 00000000 0000001a 00000000 
9a20: 000000f0 8c012758 8c2e2a4c 8c0170e0 8f9354b8 8c012720 ffffffff 00010000 
9a40: 8c0124c0 00000010 00000004 00010000 fd00005c 0000001e 00000003 8f935400 
9a60: 8f819ac8 8f9354b8 00000000 00000000 00000000 00000000 8f819a9c 8c1875f8 
9a80: 8c1875f8 40000000 00000000 00010a8b 00000000 ffffffff ffffffff 8c17bc26 
9aa0: 8c17bba4 00000000 00000000 8f935400 00000000 8f947de0 00000010 00000000 
9ac0: 8f819ac8 00000000 00000000 8c17bc26 00000000 9e75a1a9 8f817b6c 00000000 
9ae0: 8c01f860 8f819af8 8c2a3560 8c2d9e88 8c2d9eb8 8f817b6c 8c02109c 8f819b0c 
9b00: 8f817b40 8c2da244 8c2d9e9c 8c02ef5a 8f929460 8c2a6e10 0000000a 8f940e40 
9b20: 8f819aa0 00000000 00000000 8f947e20 8c17d9b0 8c17d9c4 80000180 8c0f63e4 
9b40: 8f947de0 00000000 8f819ac8 00000000 00000000 8f947e20 8c17d9b0 80000100 
9b60: 8f935000 8f819ba8 000003e8 8f947de0 8f947e20 00000000 00000000 8f819b7c 
9b80: 8f819b7c 8c17d0ee 8c17db0c 8f819ba2 00000001 00000000 fffffff4 8f940e00 
9ba0: 00030010 00000000 00000003 8c176a28 8f935240 8f935000 8f819be6 ffffff0f 
9bc0: 8f83fc80 00000003 00000000 00000010 00000003 00000000 00000000 000003e8 
9be0: 8c17798e 00010101 00000000 00000001 8f83fcbc 8c178404 8f929466 8f935000 
9c00: 8f83fc80 8c27bde4 8f942600 00000002 40408180 00000000 8c0bdbfa 8c08d78c 
9c20: 8f809a00 00000000 8c0be9ac 00000000 8f942698 00000001 00000000 8f94261c 
9c40: 8f83fcc0 8f948a04 8c180006 00000000 ffffffed 8c2b4504 8c2b44d4 8c2b453c 
9c60: 8f935000 8f942600 8c142ae4 8f942698 8c2e75a4 8f942698 00000000 8c2b4504 
9c80: 8f94261c 8c141bae 8f94265c 8f94261c 8c142be0 8c219e60 00000000 8f862e68 
9ca0: 8f862e68 8f830934 8c142c6e ffffffec 8f9426d8 8f94261c 8c2b45f0 8c141f06 
9cc0: 8f94261c 8f94261c 8c2b45f0 8c13fef2 00000000 00000000 8c27cb73 ffffffff 
9ce0: 8c13fc96 8f942850 8f93505c 8c2b45d4 8f942684 8c17f592 8f93505c 0000008c 
9d00: 00000000 8f942854 8f9294aa 8f942600 8f94261c 8f935000 00000001 8f940f40 
9d20: 00000001 00000000 8f9350fc 8f93505c 8f935004 8f9428d4 00000004 8c186b54 
9d40: 00000000 8f9350d8 8c2e75a4 8f9350d8 00000001 8f935000 8f93505c 8c17f9f4 
9d60: 8f9350d8 00000000 8c2b4bc0 8f93505c 8c142ae4 8c141bae 8f93509c 8f93505c 
9d80: 8c142be0 8c219e60 00000000 8f862e68 8f862e68 8f8308d4 8c142c6e ffffffec 
9da0: 8f935118 8f93505c 8c2b45f0 8c141f06 8f93505c 8f93505c 8c2b45f0 8c13fef2 
9dc0: 00000000 00000000 3a393831 8c170030 8c17e9fa 8f935000 8f80f058 8c2b4494 
9de0: 8f9350c4 8c178800 8f935000 8f935440 8f93505c 8f935000 8f935400 00000000 
9e00: 8f819e10 8c17cd86 8f93547c 00000012 8f935400 8f935000 8f819e10 0000006f 
9e20: 00000080 8f80f058 8c186e74 8f935400 8c242b98 8f80f058 8f80f000 fffffff2 
9e40: 8f93547c e0000000 00000100 8c105b78 00000000 000000ac 8c2e75a4 8f80f0d4 
9e60: ffffffed 8f80f000 8c2b4c4c 8c142ae4 00000000 8c2b4c80 8f80f058 8c142d26 
9e80: 8c2b4c80 8f80f098 8c03f180 8f80f104 8f80f058 8c141808 8f880260 8c2d8080 
9ea0: 8c2b4c80 8c142ca0 8c141780 00000000 8f82f798 8f82f798 8f80f0a0 8c142226 
9ec0: 8c2ade98 8c2b4c80 8c2b4c80 00000000 8c1432d8 00000000 8c2cc240 8c2d8080 
9ee0: 8c2d69a4 8c2b4c80 8c2b4c80 8c2b4c4c 8c1058d6 8c2cc240 8c2d8080 8c2d69a4 
9f00: 8c2b4c80 8c011060 8c2b4c4c 8c2d6b70 8c2cc264 8c2d6bdc 8c011060 8c2d6b70 
9f20: 8c011088 8c2d6b70 00000000 8c2d69a4 8f830f60 8f82f8e0 8c0f4b60 0000008f 
9f40: 8c0b701e 8c2e126c 00000071 8f82f8e0 8f830f60 8c04dc4a 8c2a93c0 00333131 
9f60: 00000000 8c010000 8c2bcc16 00000000 00000000 00000000 8c2d69a4 8c2d6bdc 
9f80: 8c011060 8c2d6b70 00000001 8c0127a4 00000000 00000000 00000000 00000000 
9fa0: 00000000 00000000 00000000 00000000 00000000 8c2bcba0 00000000 00000000 
9fc0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 8f819fa0 
9fe0: 8c0127a0 00000000 40000000 00000000 00000000 00000000 00000000 00000000 

Call trace: 
[<8c026220>] printk+0x0/0x20
[<8c04c84a>] note_interrupt+0x20a/0x240
[<8c04d20a>] handle_level_irq+0xaa/0x100
[<8c012752>] do_IRQ+0x32/0x60
[<8c0170e0>] ret_from_exception+0x0/0xc
[<8c012720>] do_IRQ+0x0/0x60
[<8c02ef40>] run_timer_softirq+0x0/0x180
[<8c02ef40>] run_timer_softirq+0x0/0x180
[<8c02a79a>] __do_softirq+0x5a/0xe0
[<8c02a8a6>] do_softirq+0x86/0xa0
[<8c012758>] do_IRQ+0x38/0x60
[<8c0170e0>] ret_from_exception+0x0/0xc
[<8c012720>] do_IRQ+0x0/0x60
[<8c0124c0>] generic_writel+0x0/0x20
[<8c1875f8>] ohci_hub_control+0xf8/0x620
[<8c1875f8>] ohci_hub_control+0xf8/0x620
[<8c17bc26>] usb_hcd_submit_urb+0x466/0x9c0
[<8c17bba4>] usb_hcd_submit_urb+0x3e4/0x9c0
[<8c17bc26>] usb_hcd_submit_urb+0x466/0x9c0
[<8c01f860>] task_tick_fair+0x20/0x80
[<8c02109c>] scheduler_tick+0x5c/0x80
[<8c02ef5a>] run_timer_softirq+0x1a/0x180
[<8c17d9b0>] usb_start_wait_urb+0x30/0xe0
[<8c17d9c4>] usb_start_wait_urb+0x44/0xe0
[<8c0f63e4>] kref_put+0x44/0xa0
[<8c17d9b0>] usb_start_wait_urb+0x30/0xe0
[<8c17d0ee>] usb_alloc_urb+0xe/0x60
[<8c17db0c>] usb_control_msg+0xac/0x100
[<8c176a28>] clear_port_feature+0x28/0x40
[<8c17798e>] hub_activate+0x18e/0x2c0
[<8c178404>] hub_probe+0x544/0x7a0
[<8c0bdbfa>] sysfs_addrm_finish+0x1a/0x2e0
[<8c08d78c>] ilookup5_nowait+0x2c/0x60
[<8c0be9ac>] sysfs_do_create_link+0x6c/0x200
[<8c180006>] usb_probe_interface+0x86/0x160
[<8c142ae4>] driver_probe_device+0xe4/0x1e0
[<8c141bae>] bus_for_each_drv+0x4e/0x80
[<8c142be0>] __device_attach+0x0/0x20
[<8c219e60>] klist_next+0x0/0xc0
[<8c142c6e>] device_attach+0x6e/0xa0
[<8c141f06>] bus_attach_device+0x66/0xa0
[<8c13fef2>] device_add+0x192/0x600
[<8c13fc96>] dev_set_name+0x16/0x40
[<8c17f592>] usb_set_configuration+0x292/0x520
[<8c186b54>] generic_probe+0x74/0xe0
[<8c17f9f4>] usb_probe_device+0x34/0x60
[<8c142ae4>] driver_probe_device+0xe4/0x1e0
[<8c141bae>] bus_for_each_drv+0x4e/0x80
[<8c142be0>] __device_attach+0x0/0x20
[<8c219e60>] klist_next+0x0/0xc0
[<8c142c6e>] device_attach+0x6e/0xa0
[<8c141f06>] bus_attach_device+0x66/0xa0
[<8c13fef2>] device_add+0x192/0x600
[<8c170030>] ata_sff_irq_on+0x50/0xa0
[<8c17e9fa>] usb_cache_string+0x5a/0xa0
[<8c178800>] usb_new_device+0x40/0x160
[<8c17cd86>] usb_add_hcd+0x5a6/0x740
[<8c186e74>] usb_hcd_pci_probe+0x194/0x2e0
[<8c105b78>] pci_device_probe+0x58/0xa0
[<8c142ae4>] driver_probe_device+0xe4/0x1e0
[<8c142d26>] __driver_attach+0x86/0xc0
[<8c03f180>] down+0x0/0x80
[<8c141808>] bus_for_each_dev+0x48/0xa0
[<8c142ca0>] __driver_attach+0x0/0xc0
[<8c141780>] next_device+0x0/0x40
[<8c142226>] bus_add_driver+0x166/0x220
[<8c1432d8>] driver_register+0x38/0x160
[<8c2cc240>] ohci_hcd_mod_init+0x0/0x80
[<8c1058d6>] __pci_register_driver+0x36/0xc0
[<8c2cc240>] ohci_hcd_mod_init+0x0/0x80
[<8c011060>] do_one_initcall+0x0/0x1a0
[<8c2cc264>] ohci_hcd_mod_init+0x24/0x80
[<8c011060>] do_one_initcall+0x0/0x1a0
[<8c011088>] do_one_initcall+0x28/0x1a0
[<8c0f4b60>] ida_pre_get+0x0/0x80
[<8c0b701e>] create_proc_entry+0x3e/0xe0
[<8c04dc4a>] register_irq_proc+0x6a/0xc0
[<8c2bcc16>] kernel_init+0x76/0x140
[<8c011060>] do_one_initcall+0x0/0x1a0
[<8c0127a4>] kernel_thread_helper+0x4/0x20
[<8c2bcba0>] kernel_init+0x0/0x140
[<8c0127a0>] kernel_thread_helper+0x0/0x20

handlers:
[<8c17c580>] (usb_hcd_irq+0x0/0x120)
Disabling IRQ #111
usb usb1: New USB device found, idVendor=1d6b, idProduct=0001
usb usb1: New USB device strings: Mfr=3, Product=2, SerialNumber=1
usb usb1: Product: OHCI Host Controller
usb usb1: Manufacturer: Linux 2.6.27-hpc-00015-g56be9ec-dirty ohci_hcd
usb usb1: SerialNumber: 0000:00:01.0
sm501-usb sm501-usb: SM501 OHCI
sm501-usb sm501-usb: new USB bus registered, assigned bus number 2
sm501-usb sm501-usb: irq 100, io mem 0x13e40000
sm501-usb sm501-usb: init err (00000000 0000)
sm501-usb sm501-usb: can't start sm501-usb<3>sm501-usb sm501-usb: startup error -75
sm501-usb sm501-usb: USB bus 2 deregistered
sm501-usb: probe of sm501-usb failed with error -75
Initializing USB Mass Storage driver...
usb 1-3: new full speed USB device using ohci_hcd and address 2
...................stands endlessly here.........................

On Wed, 12 Nov 2008 13:33:13 +0900
yoshii.takashi@gmail.com wrote:

> Hi,
> 
> > I'm still getting segmentation fault at exact same
> > location. Have you made additional patches?
> Please find attached file "qemu081111.diff".
> Basically, this is an aggregate of patches found on qemu-devel ML,
>  with some conflicts against current svn source being resolved,
>  and some small fix are added, which are scheduled to be posted after
>  I finished with my pending patches.
> 
> I post this to share information between qemu and linux/sh people,
>  and hopefully accelerate debugging with linux people's help.
> 
> Another file "linuxconfig_r2d_qemu.diff" is diff for linux kernel
>  configuretion. It changes following parameters from r2d+'s defconfig.
> - Cache -> off (qemu has no cache)
> - commandline change (for debugging)
> - 8139too -> 8139cp (qemu's default is c+, still thinking how to switch)
> - SH SPI -> off (sci emulation is not mature enough to handle it)
> 
> Build procedure is as follows,
> Configure kernel:
>  make ARCH=sh rts7751r2dplus_defconfig
>  patch .config < linuxconfig_r2d_qemu.diff
>  (and build)
> 
> Configure Qemu:
>  ./configure --disable-system --target-list=sh4-softmmu \
>   --disable-linux-user --disable-kqemu
> 
> Execute:
>  sh4-softmmu/qemu-system-sh4 -M r2d --serial vc --serial /dev/tty \
>   --kernel zImage --append "console=tty0 root=/dev/sda" \
>   -usb --usbdevice keyboard --usbdevice mouse disk.img
> 
> I've tested it on qemu svn head this morning.
> You will see penguin logo, and fbcon input/output working.
> For debugging purpose, console=ttySC0,115200 might help.
> /yoshii
> 


-- 
Kristoffer Ericson <kristoffer.ericson@gmail.com>

[-- Attachment #2: Type: application/pgp-signature, Size: 197 bytes --]

Re: [Qemu-devel] Re: Qemu SH4 status #2

[Shin-ichiro KAWASAKI]

[-- Attachment #1: Type: text/plain, Size: 2655 bytes --]

Hi,

Aurelien committed Volodya's MMU patch kindly. 
  http://lists.gnu.org/archive/html/qemu-devel/2008-11/msg01182.html

So some part of the big patch is not necessary now.
I omitted the part and generated new big patch and attach it to this mail,
which can be applied to QEMU rev5786.  I hope it helps.


yoshii.takashi@gmail.com wrote:
> Another file "linuxconfig_r2d_qemu.diff" is diff for linux kernel
>  configuretion. It changes following parameters from r2d+'s defconfig.
> - Cache -> off (qemu has no cache)

It seems the kernel with cache works fine.  Even though qemu has no cache
emulation, there is no need to tell it to qemu users, I think.

> - commandline change (for debugging)
> - 8139too -> 8139cp (qemu's default is c+, still thinking how to switch)

> - SH SPI -> off (sci emulation is not mature enough to handle it)
I hope my small patch avoid SPI config problem.
  http://lists.gnu.org/archive/html/qemu-devel/2008-11/msg01229.html

Anyway, your patches on MMIO/ATA and PCI works fine!
Thank you.

Regards,
Shin-ichiro KAWASAKI



yoshii.takashi@gmail.com wrote:
> Hi,
> 
>> I'm still getting segmentation fault at exact same
>> location. Have you made additional patches?
> Please find attached file "qemu081111.diff".
> Basically, this is an aggregate of patches found on qemu-devel ML,
>  with some conflicts against current svn source being resolved,
>  and some small fix are added, which are scheduled to be posted after
>  I finished with my pending patches.
> 
> I post this to share information between qemu and linux/sh people,
>  and hopefully accelerate debugging with linux people's help.
> 
> Another file "linuxconfig_r2d_qemu.diff" is diff for linux kernel
>  configuretion. It changes following parameters from r2d+'s defconfig.
> - Cache -> off (qemu has no cache)
> - commandline change (for debugging)
> - 8139too -> 8139cp (qemu's default is c+, still thinking how to switch)
> - SH SPI -> off (sci emulation is not mature enough to handle it)
> 
> Build procedure is as follows,
> Configure kernel:
>  make ARCH=sh rts7751r2dplus_defconfig
>  patch .config < linuxconfig_r2d_qemu.diff
>  (and build)
> 
> Configure Qemu:
>  ./configure --disable-system --target-list=sh4-softmmu \
>   --disable-linux-user --disable-kqemu
> 
> Execute:
>  sh4-softmmu/qemu-system-sh4 -M r2d --serial vc --serial /dev/tty \
>   --kernel zImage --append "console=tty0 root=/dev/sda" \
>   -usb --usbdevice keyboard --usbdevice mouse disk.img
> 
> I've tested it on qemu svn head this morning.
> You will see penguin logo, and fbcon input/output working.
> For debugging purpose, console=ttySC0,115200 might help.
> /yoshii
> 


[-- Attachment #2: qemu081124.diff --]
[-- Type: text/x-patch, Size: 20846 bytes --]

Index: trunk/target-sh4/helper.c
===================================================================
--- trunk/target-sh4/helper.c	(revision 5786)
+++ trunk/target-sh4/helper.c	(working copy)
@@ -439,6 +439,9 @@
 	if (address >= 0x80000000 && address < 0xc0000000) {
 	    /* Mask upper 3 bits for P1 and P2 areas */
 	    *physical = address & 0x1fffffff;
+	} else if (address >= 0xfd000000 && address < 0xfe000000) {
+	    /* PCI memory space */
+	    *physical = address;
 	} else if (address >= 0xfc000000) {
 	    /*
 	     * Mask upper 3 bits for control registers in P4 area,
Index: trunk/Makefile.target
===================================================================
--- trunk/Makefile.target	(revision 5786)
+++ trunk/Makefile.target	(working copy)
@@ -736,7 +736,8 @@
 endif
 ifeq ($(TARGET_BASE_ARCH), sh4)
 OBJS+= shix.o r2d.o sh7750.o sh7750_regnames.o tc58128.o
-OBJS+= sh_timer.o ptimer.o sh_serial.o sh_intc.o sm501.o serial.o
+OBJS+= sh_timer.o ptimer.o sh_serial.o sh_intc.o sh_pci.o sm501.o serial.o
+OBJS+= ide.o
 endif
 ifeq ($(TARGET_BASE_ARCH), m68k)
 OBJS+= an5206.o mcf5206.o ptimer.o mcf_uart.o mcf_intc.o mcf5208.o mcf_fec.o
Index: trunk/hw/r2d.c
===================================================================
--- trunk/hw/r2d.c	(revision 5786)
+++ trunk/hw/r2d.c	(working copy)
@@ -28,12 +28,16 @@
 #include "devices.h"
 #include "sysemu.h"
 #include "boards.h"
+#include "pci.h"
+#include "net.h"
+#include "sh7750_regs.h"
 
 #define SDRAM_BASE 0x0c000000 /* Physical location of SDRAM: Area 3 */
 #define SDRAM_SIZE 0x04000000
 
 #define SM501_VRAM_SIZE 0x800000
 
+#define PA_IRLMSK	0x00
 #define PA_POWOFF	0x30
 #define PA_VERREG	0x32
 #define PA_OUTPORT	0x36
@@ -41,6 +45,8 @@
 typedef struct {
     target_phys_addr_t base;
 
+/* register */
+    uint16_t irlmsk;
     uint16_t bcr;
     uint16_t irlmon;
     uint16_t cfctl;
@@ -62,8 +68,53 @@
     uint16_t inport;
     uint16_t outport;
     uint16_t bverreg;
+
+/* output pin */
+    qemu_irq irl;
 } r2d_fpga_t;
 
+enum r2d_fpga_irq {
+    PCI_INTD, CF_IDE, CF_CD, PCI_INTC, SM501, KEY, RTC_A, RTC_T,
+    SDCARD, PCI_INTA, PCI_INTB, EXT, TP,
+    NR_IRQS
+};
+
+static const struct { short irl; uint16_t msk; } irqtab[NR_IRQS] = {
+    [CF_IDE]	= {  1, 1<<9 },
+    [CF_CD]	= {  2, 1<<8 },
+    [PCI_INTA]	= {  9, 1<<14 },
+    [PCI_INTB]	= { 10, 1<<13 },
+    [PCI_INTC]	= {  3, 1<<12 },
+    [PCI_INTD]	= {  0, 1<<11 },
+    [SM501]	= {  4, 1<<10 },
+    [KEY]	= {  5, 1<<6 },
+    [RTC_A]	= {  6, 1<<5 },
+    [RTC_T]	= {  7, 1<<4 },
+    [SDCARD]	= {  8, 1<<7 },
+    [EXT]	= { 11, 1<<0 },
+    [TP]	= { 12, 1<<15 },
+};
+
+static void update_irl(r2d_fpga_t *fpga)
+{
+    int i, irl = 15;
+    for (i = 0; i < NR_IRQS; i++)
+        if (fpga->irlmon & fpga->irlmsk & irqtab[i].msk)
+            if (irqtab[i].irl < irl)
+                irl = irqtab[i].irl;
+    qemu_set_irq(fpga->irl, irl ^ 15);
+}
+
+static void r2d_fpga_irq_set(void *opaque, int n, int level)
+{
+    r2d_fpga_t *fpga = opaque;
+    if (level)
+        fpga->irlmon |= irqtab[n].msk;
+    else
+        fpga->irlmon &= ~irqtab[n].msk;
+    update_irl(fpga);
+}
+
 static uint32_t r2d_fpga_read(void *opaque, target_phys_addr_t addr)
 {
     r2d_fpga_t *s = opaque;
@@ -71,6 +122,8 @@
     addr -= s->base;
 
     switch (addr) {
+    case PA_IRLMSK:
+        return s->irlmsk;
     case PA_OUTPORT:
 	return s->outport;
     case PA_POWOFF:
@@ -90,6 +143,10 @@
     addr -= s->base;
 
     switch (addr) {
+    case PA_IRLMSK:
+        s->irlmsk = value;
+        update_irl(s);
+	break;
     case PA_OUTPORT:
 	s->outport = value;
 	break;
@@ -114,21 +171,35 @@
     NULL,
 };
 
-static void r2d_fpga_init(target_phys_addr_t base)
+static qemu_irq *r2d_fpga_init(target_phys_addr_t base, qemu_irq irl)
 {
     int iomemtype;
     r2d_fpga_t *s;
 
     s = qemu_mallocz(sizeof(r2d_fpga_t));
     if (!s)
-	return;
+	return NULL;
 
+    s->irl = irl;
+
     s->base = base;
     iomemtype = cpu_register_io_memory(0, r2d_fpga_readfn,
 				       r2d_fpga_writefn, s);
     cpu_register_physical_memory(base, 0x40, iomemtype);
+    return qemu_allocate_irqs(r2d_fpga_irq_set, s, NR_IRQS);
 }
 
+static void r2d_pci_set_irq(qemu_irq *p, int n, int l)
+{
+    qemu_set_irq(p[n], l);
+}
+
+static int r2d_pci_map_irq(PCIDevice *d, int irq_num)
+{
+    const int intx[] = { PCI_INTA, PCI_INTB, PCI_INTC, PCI_INTD };
+    return intx[d->devfn>>3];
+}
+
 static void r2d_init(ram_addr_t ram_size, int vga_ram_size,
               const char *boot_device, DisplayState * ds,
 	      const char *kernel_filename, const char *kernel_cmdline,
@@ -137,6 +208,9 @@
     CPUState *env;
     struct SH7750State *s;
     ram_addr_t sdram_addr, sm501_vga_ram_addr;
+    qemu_irq *irq;
+    PCIBus *pci;
+    int i;
 
     if (!cpu_model)
         cpu_model = "SH7751R";
@@ -151,23 +225,50 @@
     sdram_addr = qemu_ram_alloc(SDRAM_SIZE);
     cpu_register_physical_memory(SDRAM_BASE, SDRAM_SIZE, sdram_addr);
     /* Register peripherals */
-    r2d_fpga_init(0x04000000);
     s = sh7750_init(env);
+    irq = r2d_fpga_init(0x04000000, sh7750_irl(s));
+
     sm501_vga_ram_addr = qemu_ram_alloc(SM501_VRAM_SIZE);
     sm501_init(ds, 0x10000000, sm501_vga_ram_addr, SM501_VRAM_SIZE,
 	       serial_hds[2]);
+
+    /* onboard CF (True IDE mode, Master only). */
+    if ((i = drive_get_index(IF_IDE, 0, 0)) != -1)
+        mmio_ide_init(0x14001000, 0x1400080c, irq[CF_IDE], 1,
+                      drives_table[i].bdrv, NULL);
+
+    /* PCI host and peripherals */
+    pci = sh_pci_register_bus(r2d_pci_set_irq, r2d_pci_map_irq, irq, 0, 4);
+
+    /* NIC: rtl8139 on-board, and 2 slots. */
+    if (nb_nics)
+        pci_rtl8139_init(pci, &nd_table[0], 2<<3);
+    for (i = 1; i < nb_nics; i++)
+        pci_nic_init(pci, &nd_table[i], -1);
+    /* USB OHCI for keyboard & mouse */
+    if (usb_enabled)
+        usb_ohci_init_pci(pci, 4, -1);
     /* Todo: register on board registers */
-    {
+    if (kernel_filename) {
       int kernel_size;
+      /* initialization which should be done by firmware */
+      uint32_t bcr1 = 1<<3; // cs3 SDRAM
+      uint16_t bcr2 = 3<<(3*2); // cs3 32bit
+      cpu_physical_memory_write(SH7750_BCR1_A7,&bcr1,4);
+      cpu_physical_memory_write(SH7750_BCR2_A7,&bcr2,2);
 
-      kernel_size = load_image(kernel_filename, phys_ram_base);
-
+      if (kernel_cmdline) {
+          kernel_size = load_image(kernel_filename, phys_ram_base + 0x80000);
+          env->pc = (SDRAM_BASE + 0x80000) | 0xa0000000;
+          pstrcpy(phys_ram_base + 0x10100, 256, kernel_cmdline);
+      } else {
+          kernel_size = load_image(kernel_filename, phys_ram_base);
+          env->pc = SDRAM_BASE | 0xa0000000; /* Start from P2 area */
+      }
       if (kernel_size < 0) {
         fprintf(stderr, "qemu: could not load kernel '%s'\n", kernel_filename);
         exit(1);
       }
-
-      env->pc = SDRAM_BASE | 0xa0000000; /* Start from P2 area */
     }
 }
 
Index: trunk/hw/sh_pci.c
===================================================================
--- trunk/hw/sh_pci.c	(revision 0)
+++ trunk/hw/sh_pci.c	(revision 0)
@@ -0,0 +1,207 @@
+/*
+ * SuperH on-chip PCIC emulation.	
+ *
+ * Copyright (c) 2008 Takashi YOSHII
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+#include "hw.h"
+#include "sh.h"
+#include "pci.h"
+#include "bswap.h"
+
+typedef struct {
+    PCIBus *bus;
+    PCIDevice *dev;
+    uint32_t regbase;
+    uint32_t iopbase;
+    uint32_t membase;
+    uint32_t par;
+    uint32_t mbr;
+    uint32_t iobr;
+} SHPCIC;
+
+static void sh_pci_reg_write (void *p, target_phys_addr_t addr, uint32_t val)
+{
+    SHPCIC *pcic = p;
+    addr -= pcic->regbase;
+    switch(addr) {
+      case 0 ... 0xfc:
+        cpu_to_le32w((uint32_t*)(pcic->dev->config + addr), val);
+        break;
+      case 0x1c0:
+        pcic->par = val;
+        break;
+      case 0x1c4:
+        pcic->mbr = val;
+        break;
+      case 0x1c8:
+        pcic->iobr = val;
+        break;
+      case 0x220:
+        pci_data_write(pcic->bus, pcic->par, val, 4);
+        break;
+    }
+}
+
+static uint32_t sh_pci_reg_read (void *p, target_phys_addr_t addr)
+{
+    SHPCIC *pcic = p;
+    addr -= pcic->regbase;
+    switch(addr) {
+      case 0 ... 0xfc:
+        return le32_to_cpup((uint32_t*)(pcic->dev->config + addr));
+      case 0x1c0:
+        return pcic->par;
+      case 0x220:
+        return pci_data_read(pcic->bus, pcic->par, 4);
+    }
+    return 0;
+}
+
+static void sh_pci_data_write (SHPCIC *pcic, target_phys_addr_t addr,
+                               uint32_t val, int size)
+{
+    pci_data_write(pcic->bus, addr - pcic->membase + pcic->mbr, val, size);
+}
+
+static uint32_t sh_pci_mem_read (SHPCIC *pcic, target_phys_addr_t addr,
+                                 int size)
+{
+    return pci_data_read(pcic->bus, addr - pcic->membase + pcic->mbr, size);
+}
+
+static void sh_pci_writeb (void *p, target_phys_addr_t addr, uint32_t val)
+{
+    sh_pci_data_write(p, addr, val, 1);
+}
+
+static void sh_pci_writew (void *p, target_phys_addr_t addr, uint32_t val)
+{
+    sh_pci_data_write(p, addr, val, 2);
+}
+
+static void sh_pci_writel (void *p, target_phys_addr_t addr, uint32_t val)
+{
+    sh_pci_data_write(p, addr, val, 4);
+}
+
+static uint32_t sh_pci_readb (void *p, target_phys_addr_t addr)
+{
+    return sh_pci_mem_read(p, addr, 1);
+}
+
+static uint32_t sh_pci_readw (void *p, target_phys_addr_t addr)
+{
+    return sh_pci_mem_read(p, addr, 2);
+}
+
+static uint32_t sh_pci_readl (void *p, target_phys_addr_t addr)
+{
+    return sh_pci_mem_read(p, addr, 4);
+}
+
+static int sh_pci_addr2port(SHPCIC *pcic, target_phys_addr_t addr)
+{
+    return addr - pcic->iopbase + pcic->iobr;
+}
+
+static void sh_pci_outb (void *p, target_phys_addr_t addr, uint32_t val)
+{
+    cpu_outb(NULL, sh_pci_addr2port(p, addr), val);
+}
+
+static void sh_pci_outw (void *p, target_phys_addr_t addr, uint32_t val)
+{
+    cpu_outw(NULL, sh_pci_addr2port(p, addr), val);
+}
+
+static void sh_pci_outl (void *p, target_phys_addr_t addr, uint32_t val)
+{
+    cpu_outl(NULL, sh_pci_addr2port(p, addr), val);
+}
+
+static uint32_t sh_pci_inb (void *p, target_phys_addr_t addr)
+{
+    return cpu_inb(NULL, sh_pci_addr2port(p, addr));
+}
+
+static uint32_t sh_pci_inw (void *p, target_phys_addr_t addr)
+{
+    return cpu_inw(NULL, sh_pci_addr2port(p, addr));
+}
+
+static uint32_t sh_pci_inl (void *p, target_phys_addr_t addr)
+{
+    return cpu_inl(NULL, sh_pci_addr2port(p, addr));
+}
+
+typedef struct {
+    CPUReadMemoryFunc *r[3];
+    CPUWriteMemoryFunc *w[3];
+} MemOp;
+
+static MemOp sh_pci_reg = {
+    { NULL, NULL, sh_pci_reg_read },
+    { NULL, NULL, sh_pci_reg_write },
+};
+
+static MemOp sh_pci_mem = {
+    { sh_pci_readb, sh_pci_readw, sh_pci_readl },
+    { sh_pci_writeb, sh_pci_writew, sh_pci_writel },
+};
+
+static MemOp sh_pci_iop = {
+    { sh_pci_inb, sh_pci_inw, sh_pci_inl },
+    { sh_pci_outb, sh_pci_outw, sh_pci_outl },
+};
+
+PCIBus *sh_pci_register_bus(pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
+                            qemu_irq *pic, int devfn_min, int nirq)
+{
+    SHPCIC *p;
+    int mem, reg, iop;
+
+    p = qemu_mallocz(sizeof(SHPCIC));
+    p->bus = pci_register_bus(set_irq, map_irq, pic, devfn_min, nirq);
+
+    p->dev = pci_register_device(p->bus, "SH PCIC", sizeof(PCIDevice),
+                                 -1, NULL, NULL);
+    p->regbase = 0x1e200000;
+    p->iopbase = 0x1e240000;
+    p->membase = 0xfd000000;
+    reg = cpu_register_io_memory(0, sh_pci_reg.r, sh_pci_reg.w, p);
+    mem = cpu_register_io_memory(0, sh_pci_mem.r, sh_pci_mem.w, p);
+    iop = cpu_register_io_memory(0, sh_pci_iop.r, sh_pci_iop.w, p);
+    cpu_register_physical_memory(p->regbase, 0x224, reg);
+    cpu_register_physical_memory(p->iopbase, 0x40000, iop);
+    cpu_register_physical_memory(p->membase, 0x1000000, mem);
+
+    p->dev->config[0x00] = 0x54; // HITACHI
+    p->dev->config[0x01] = 0x10; //
+    p->dev->config[0x02] = 0x0e; // SH7751R
+    p->dev->config[0x03] = 0x35; //
+    p->dev->config[0x04] = 0x80;
+    p->dev->config[0x05] = 0x00;
+    p->dev->config[0x06] = 0x90;
+    p->dev->config[0x07] = 0x02;
+
+    return p->bus;
+}
+
Index: trunk/hw/sh.h
===================================================================
--- trunk/hw/sh.h	(revision 5786)
+++ trunk/hw/sh.h	(working copy)
@@ -42,7 +42,14 @@
 		     qemu_irq tei_source,
 		     qemu_irq bri_source);
 
+/* sh7750.c */
+qemu_irq sh7750_irl(struct SH7750State *s);
+
 /* tc58128.c */
 int tc58128_init(struct SH7750State *s, const char *zone1, const char *zone2);
 
+/* ide.c */
+void mmio_ide_init(target_phys_addr_t membase, target_phys_addr_t membase2,
+                   qemu_irq irq, int shift,
+                   BlockDriverState *hd0, BlockDriverState *hd1);
 #endif
Index: trunk/hw/sh7750.c
===================================================================
--- trunk/hw/sh7750.c	(revision 5786)
+++ trunk/hw/sh7750.c	(working copy)
@@ -41,6 +41,8 @@
     /* Peripheral frequency in Hz */
     uint32_t periph_freq;
     /* SDRAM controller */
+    uint32_t bcr1;
+    uint32_t bcr2;
     uint16_t rfcr;
     /* IO ports */
     uint16_t gpioic;
@@ -208,6 +210,8 @@
     SH7750State *s = opaque;
 
     switch (addr) {
+    case SH7750_BCR2_A7:
+	return s->bcr2;
     case SH7750_FRQCR_A7:
 	return 0;
     case SH7750_RFCR_A7:
@@ -231,6 +235,15 @@
     SH7750State *s = opaque;
 
     switch (addr) {
+    case SH7750_BCR1_A7:
+	return s->bcr1;
+    case SH7750_BCR4_A7:
+    case SH7750_WCR1_A7:
+    case SH7750_WCR2_A7:
+    case SH7750_WCR3_A7:
+    case SH7750_MCR_A7:
+	ignore_access("long read", addr);
+	return 0;
     case SH7750_MMUCR_A7:
 	return s->cpu->mmucr;
     case SH7750_PTEH_A7:
@@ -285,6 +298,8 @@
     switch (addr) {
 	/* SDRAM controller */
     case SH7750_BCR2_A7:
+	s->bcr2 = mem_value;
+	return;
     case SH7750_BCR3_A7:
     case SH7750_RTCOR_A7:
     case SH7750_RTCNT_A7:
@@ -331,6 +346,8 @@
     switch (addr) {
 	/* SDRAM controller */
     case SH7750_BCR1_A7:
+	s->bcr1 = mem_value;
+        return;
     case SH7750_BCR4_A7:
     case SH7750_WCR1_A7:
     case SH7750_WCR2_A7:
@@ -412,7 +429,9 @@
 	UNUSED = 0,
 
 	/* interrupt sources */
-	IRL0, IRL1, IRL2, IRL3, /* only IRLM mode supported */
+	IRL_0, IRL_1, IRL_2, IRL_3, IRL_4, IRL_5, IRL_6, IRL_7,
+	IRL_8, IRL_9, IRL_A, IRL_B, IRL_C, IRL_D, IRL_E,
+	IRL0, IRL1, IRL2, IRL3,
 	HUDI, GPIOI,
 	DMAC_DMTE0, DMAC_DMTE1, DMAC_DMTE2, DMAC_DMTE3,
 	DMAC_DMTE4, DMAC_DMTE5, DMAC_DMTE6, DMAC_DMTE7,
@@ -428,6 +447,8 @@
 
 	/* interrupt groups */
 	DMAC, PCIC1, TMU2, RTC, SCI1, SCIF, REF,
+	/* irl bundle */
+	IRL,
 
 	NR_SOURCES,
 };
@@ -529,6 +550,29 @@
 		   PCIC1_PCIDMA0, PCIC1_PCIDMA1, PCIC1_PCIDMA2, PCIC1_PCIDMA3),
 };
 
+static struct intc_vect vectors_irl[] = {
+	INTC_VECT(IRL_0, 0x200),
+	INTC_VECT(IRL_1, 0x220),
+	INTC_VECT(IRL_2, 0x240),
+	INTC_VECT(IRL_3, 0x260),
+	INTC_VECT(IRL_4, 0x280),
+	INTC_VECT(IRL_5, 0x2a0),
+	INTC_VECT(IRL_6, 0x2c0),
+	INTC_VECT(IRL_7, 0x2e0),
+	INTC_VECT(IRL_8, 0x300),
+	INTC_VECT(IRL_9, 0x320),
+	INTC_VECT(IRL_A, 0x340),
+	INTC_VECT(IRL_B, 0x360),
+	INTC_VECT(IRL_C, 0x380),
+	INTC_VECT(IRL_D, 0x3a0),
+	INTC_VECT(IRL_E, 0x3c0),
+};
+
+static struct intc_group groups_irl[] = {
+	INTC_GROUP(IRL, IRL_0, IRL_1, IRL_2, IRL_3, IRL_4, IRL_5, IRL_6,
+		IRL_7, IRL_8, IRL_9, IRL_A, IRL_B, IRL_C, IRL_D, IRL_E),
+};
+
 /**********************************************************************
  Memory mapped cache and TLB
 **********************************************************************/
@@ -717,5 +761,16 @@
 				 NULL, 0);
     }
 
+    sh_intc_register_sources(&s->intc,
+				_INTC_ARRAY(vectors_irl),
+				_INTC_ARRAY(groups_irl));
     return s;
 }
+
+qemu_irq sh7750_irl(SH7750State *s)
+{
+    sh_intc_toggle_source(sh_intc_source(&s->intc, IRL), 1, 0); /* enable */
+    return qemu_allocate_irqs(sh_intc_set_irl, sh_intc_source(&s->intc, IRL),
+                               1)[0];
+}
+
Index: trunk/hw/ide.c
===================================================================
--- trunk/hw/ide.c	(revision 5786)
+++ trunk/hw/ide.c	(working copy)
@@ -3514,6 +3514,98 @@
 }
 
 /***********************************************************/
+/* MMIO based ide port
+ * This emulates IDE device connected directly to the CPU bus without
+ * dedicated ide controller, which is often seen on embedded boards.
+ */
+
+typedef struct {
+    void *dev;
+    int shift;
+} MMIOState;
+
+static uint32_t mmio_ide_read (void *opaque, target_phys_addr_t addr)
+{
+    MMIOState *s = (MMIOState*)opaque;
+    IDEState *ide = (IDEState*)s->dev;
+    addr >>= s->shift;
+    if (addr & 7)
+        return ide_ioport_read(ide, addr);
+    else
+        return ide_data_readw(ide, 0);
+}
+
+static void mmio_ide_write (void *opaque, target_phys_addr_t addr,
+	uint32_t val)
+{
+    MMIOState *s = (MMIOState*)opaque;
+    IDEState *ide = (IDEState*)s->dev;
+    addr >>= s->shift;
+    if (addr & 7)
+        ide_ioport_write(ide, addr, val);
+    else
+        ide_data_writew(ide, 0, val);
+}
+
+static CPUReadMemoryFunc *mmio_ide_reads[] = {
+    mmio_ide_read,
+    mmio_ide_read,
+    mmio_ide_read,
+};
+
+static CPUWriteMemoryFunc *mmio_ide_writes[] = {
+    mmio_ide_write,
+    mmio_ide_write,
+    mmio_ide_write,
+};
+
+static uint32_t mmio_ide_status_read (void *opaque, target_phys_addr_t addr)
+{
+    MMIOState *s= (MMIOState*)opaque;
+    IDEState *ide = (IDEState*)s->dev;
+    return ide_status_read(ide, 0);
+}
+
+static void mmio_ide_cmd_write (void *opaque, target_phys_addr_t addr,
+	uint32_t val)
+{
+    MMIOState *s = (MMIOState*)opaque;
+    IDEState *ide = (IDEState*)s->dev;
+    ide_cmd_write(ide, 0, val);
+}
+
+static CPUReadMemoryFunc *mmio_ide_status[] = {
+    mmio_ide_status_read,
+    mmio_ide_status_read,
+    mmio_ide_status_read,
+};
+
+static CPUWriteMemoryFunc *mmio_ide_cmd[] = {
+    mmio_ide_cmd_write,
+    mmio_ide_cmd_write,
+    mmio_ide_cmd_write,
+};
+
+void mmio_ide_init (target_phys_addr_t membase, target_phys_addr_t membase2, 
+	            qemu_irq irq, int shift,
+                    BlockDriverState *hd0, BlockDriverState *hd1)
+{
+    MMIOState *s = qemu_mallocz(sizeof(MMIOState));
+    IDEState *ide = qemu_mallocz(sizeof(IDEState) * 2);
+    int mem1, mem2;
+
+    ide_init2(ide, hd0, hd1, irq);
+
+    s->dev = ide;
+    s->shift = shift;
+
+    mem1 = cpu_register_io_memory(0, mmio_ide_reads, mmio_ide_writes, s);
+    mem2 = cpu_register_io_memory(0, mmio_ide_status, mmio_ide_cmd, s);
+    cpu_register_physical_memory(membase, 16<<shift, mem1);
+    cpu_register_physical_memory(membase2, 2<<shift, mem2);
+}
+
+/***********************************************************/
 /* CF-ATA Microdrive */
 
 #define METADATA_SIZE	0x20
Index: trunk/hw/sh_intc.c
===================================================================
--- trunk/hw/sh_intc.c	(revision 5786)
+++ trunk/hw/sh_intc.c	(working copy)
@@ -464,3 +464,18 @@
 
     return 0;
 }
+
+/* Assert level <n> IRL interrupt. 
+   0:deassert. 1:lowest priority,... 15:highest priority. */
+void sh_intc_set_irl(void *opaque, int n, int level)
+{
+    struct intc_source *s = opaque;
+    int i, irl = level ^ 15;
+    for (i = 0; (s = sh_intc_source(s->parent, s->next_enum_id)); i++) {
+	if (i == irl)
+	    sh_intc_toggle_source(s, s->enable_count?0:1, s->asserted?0:1);
+	else
+	    if (s->asserted)
+	        sh_intc_toggle_source(s, 0, -1);
+    }
+}
Index: trunk/hw/sh_intc.h
===================================================================
--- trunk/hw/sh_intc.h	(revision 5786)
+++ trunk/hw/sh_intc.h	(working copy)
@@ -75,4 +75,6 @@
 		 struct intc_prio_reg *prio_regs,
 		 int nr_prio_regs);
 
+void sh_intc_set_irl(void *opaque, int n, int level);
+
 #endif /* __SH_INTC_H__ */

Re: [Qemu-devel] Re: Qemu SH4 status #2

[Jean-Christophe PLAGNIOL-VILLARD]

On 16:10 Mon 24 Nov     , Shin-ichiro KAWASAKI wrote:
> Hi,
>
> Aurelien committed Volodya's MMU patch kindly.  
> http://lists.gnu.org/archive/html/qemu-devel/2008-11/msg01182.html
>
> So some part of the big patch is not necessary now.
> I omitted the part and generated new big patch and attach it to this mail,
> which can be applied to QEMU rev5786.  I hope it helps.
>
>
> yoshii.takashi@gmail.com wrote:
>> Another file "linuxconfig_r2d_qemu.diff" is diff for linux kernel
>>  configuretion. It changes following parameters from r2d+'s defconfig.
>> - Cache -> off (qemu has no cache)
>
> It seems the kernel with cache works fine.  Even though qemu has no cache
> emulation, there is no need to tell it to qemu users, I think.
>
>> - commandline change (for debugging)
>> - 8139too -> 8139cp (qemu's default is c+, still thinking how to switch)
>
>> - SH SPI -> off (sci emulation is not mature enough to handle it)
> I hope my small patch avoid SPI config problem.
>  http://lists.gnu.org/archive/html/qemu-devel/2008-11/msg01229.html
>
> Anyway, your patches on MMIO/ATA and PCI works fine!
> Thank you.
>
> Regards,
> Shin-ichiro KAWASAKI
>
>
>
> yoshii.takashi@gmail.com wrote:


> Index: trunk/target-sh4/helper.c
tested on u-boot
we can detect the RTL

Best Regards,
J.